core_t2.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/alpha/kernel/core_t2.c
  4. *
  5. * Written by Jay A Estabrook (jestabro@amt.tay1.dec.com).
  6. * December 1996.
  7. *
  8. * based on CIA code by David A Rusling (david.rusling@reo.mts.dec.com)
  9. *
  10. * Code common to all T2 core logic chips.
  11. */
  12. #define __EXTERN_INLINE
  13. #include <asm/io.h>
  14. #include <asm/core_t2.h>
  15. #undef __EXTERN_INLINE
  16. #include <linux/types.h>
  17. #include <linux/pci.h>
  18. #include <linux/sched.h>
  19. #include <linux/init.h>
  20. #include <asm/ptrace.h>
  21. #include <asm/delay.h>
  22. #include <asm/mce.h>
  23. #include "proto.h"
  24. #include "pci_impl.h"
  25. /* For dumping initial DMA window settings. */
  26. #define DEBUG_PRINT_INITIAL_SETTINGS 0
  27. /* For dumping final DMA window settings. */
  28. #define DEBUG_PRINT_FINAL_SETTINGS 0
  29. /*
  30. * By default, we direct-map starting at 2GB, in order to allow the
  31. * maximum size direct-map window (2GB) to match the maximum amount of
  32. * memory (2GB) that can be present on SABLEs. But that limits the
  33. * floppy to DMA only via the scatter/gather window set up for 8MB
  34. * ISA DMA, since the maximum ISA DMA address is 2GB-1.
  35. *
  36. * For now, this seems a reasonable trade-off: even though most SABLEs
  37. * have less than 1GB of memory, floppy usage/performance will not
  38. * really be affected by forcing it to go via scatter/gather...
  39. */
  40. #define T2_DIRECTMAP_2G 1
  41. #if T2_DIRECTMAP_2G
  42. # define T2_DIRECTMAP_START 0x80000000UL
  43. # define T2_DIRECTMAP_LENGTH 0x80000000UL
  44. #else
  45. # define T2_DIRECTMAP_START 0x40000000UL
  46. # define T2_DIRECTMAP_LENGTH 0x40000000UL
  47. #endif
  48. /* The ISA scatter/gather window settings. */
  49. #define T2_ISA_SG_START 0x00800000UL
  50. #define T2_ISA_SG_LENGTH 0x00800000UL
  51. /*
  52. * NOTE: Herein lie back-to-back mb instructions. They are magic.
  53. * One plausible explanation is that the i/o controller does not properly
  54. * handle the system transaction. Another involves timing. Ho hum.
  55. */
  56. /*
  57. * BIOS32-style PCI interface:
  58. */
  59. #define DEBUG_CONFIG 0
  60. #if DEBUG_CONFIG
  61. # define DBG(args) printk args
  62. #else
  63. # define DBG(args)
  64. #endif
  65. static volatile unsigned int t2_mcheck_any_expected;
  66. static volatile unsigned int t2_mcheck_last_taken;
  67. /* Place to save the DMA Window registers as set up by SRM
  68. for restoration during shutdown. */
  69. static struct
  70. {
  71. struct {
  72. unsigned long wbase;
  73. unsigned long wmask;
  74. unsigned long tbase;
  75. } window[2];
  76. unsigned long hae_1;
  77. unsigned long hae_2;
  78. unsigned long hae_3;
  79. unsigned long hae_4;
  80. unsigned long hbase;
  81. } t2_saved_config __attribute((common));
  82. /*
  83. * Given a bus, device, and function number, compute resulting
  84. * configuration space address and setup the T2_HAXR2 register
  85. * accordingly. It is therefore not safe to have concurrent
  86. * invocations to configuration space access routines, but there
  87. * really shouldn't be any need for this.
  88. *
  89. * Type 0:
  90. *
  91. * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  92. * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  93. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  94. * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
  95. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  96. *
  97. * 31:11 Device select bit.
  98. * 10:8 Function number
  99. * 7:2 Register number
  100. *
  101. * Type 1:
  102. *
  103. * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  104. * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  105. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  106. * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
  107. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  108. *
  109. * 31:24 reserved
  110. * 23:16 bus number (8 bits = 128 possible buses)
  111. * 15:11 Device number (5 bits)
  112. * 10:8 function number
  113. * 7:2 register number
  114. *
  115. * Notes:
  116. * The function number selects which function of a multi-function device
  117. * (e.g., SCSI and Ethernet).
  118. *
  119. * The register selects a DWORD (32 bit) register offset. Hence it
  120. * doesn't get shifted by 2 bits as we want to "drop" the bottom two
  121. * bits.
  122. */
  123. static int
  124. mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
  125. unsigned long *pci_addr, unsigned char *type1)
  126. {
  127. unsigned long addr;
  128. u8 bus = pbus->number;
  129. DBG(("mk_conf_addr(bus=%d, dfn=0x%x, where=0x%x,"
  130. " addr=0x%lx, type1=0x%x)\n",
  131. bus, device_fn, where, pci_addr, type1));
  132. if (bus == 0) {
  133. int device = device_fn >> 3;
  134. /* Type 0 configuration cycle. */
  135. if (device > 8) {
  136. DBG(("mk_conf_addr: device (%d)>20, returning -1\n",
  137. device));
  138. return -1;
  139. }
  140. *type1 = 0;
  141. addr = (0x0800L << device) | ((device_fn & 7) << 8) | (where);
  142. } else {
  143. /* Type 1 configuration cycle. */
  144. *type1 = 1;
  145. addr = (bus << 16) | (device_fn << 8) | (where);
  146. }
  147. *pci_addr = addr;
  148. DBG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
  149. return 0;
  150. }
  151. /*
  152. * NOTE: both conf_read() and conf_write() may set HAE_3 when needing
  153. * to do type1 access. This is protected by the use of spinlock IRQ
  154. * primitives in the wrapper functions pci_{read,write}_config_*()
  155. * defined in drivers/pci/pci.c.
  156. */
  157. static unsigned int
  158. conf_read(unsigned long addr, unsigned char type1)
  159. {
  160. unsigned int value, cpu, taken;
  161. unsigned long t2_cfg = 0;
  162. cpu = smp_processor_id();
  163. DBG(("conf_read(addr=0x%lx, type1=%d)\n", addr, type1));
  164. /* If Type1 access, must set T2 CFG. */
  165. if (type1) {
  166. t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
  167. *(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg;
  168. mb();
  169. }
  170. mb();
  171. draina();
  172. mcheck_expected(cpu) = 1;
  173. mcheck_taken(cpu) = 0;
  174. t2_mcheck_any_expected |= (1 << cpu);
  175. mb();
  176. /* Access configuration space. */
  177. value = *(vuip)addr;
  178. mb();
  179. mb(); /* magic */
  180. /* Wait for possible mcheck. Also, this lets other CPUs clear
  181. their mchecks as well, as they can reliably tell when
  182. another CPU is in the midst of handling a real mcheck via
  183. the "taken" function. */
  184. udelay(100);
  185. if ((taken = mcheck_taken(cpu))) {
  186. mcheck_taken(cpu) = 0;
  187. t2_mcheck_last_taken |= (1 << cpu);
  188. value = 0xffffffffU;
  189. mb();
  190. }
  191. mcheck_expected(cpu) = 0;
  192. t2_mcheck_any_expected = 0;
  193. mb();
  194. /* If Type1 access, must reset T2 CFG so normal IO space ops work. */
  195. if (type1) {
  196. *(vulp)T2_HAE_3 = t2_cfg;
  197. mb();
  198. }
  199. return value;
  200. }
  201. static void
  202. conf_write(unsigned long addr, unsigned int value, unsigned char type1)
  203. {
  204. unsigned int cpu, taken;
  205. unsigned long t2_cfg = 0;
  206. cpu = smp_processor_id();
  207. /* If Type1 access, must set T2 CFG. */
  208. if (type1) {
  209. t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
  210. *(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL;
  211. mb();
  212. }
  213. mb();
  214. draina();
  215. mcheck_expected(cpu) = 1;
  216. mcheck_taken(cpu) = 0;
  217. t2_mcheck_any_expected |= (1 << cpu);
  218. mb();
  219. /* Access configuration space. */
  220. *(vuip)addr = value;
  221. mb();
  222. mb(); /* magic */
  223. /* Wait for possible mcheck. Also, this lets other CPUs clear
  224. their mchecks as well, as they can reliably tell when
  225. this CPU is in the midst of handling a real mcheck via
  226. the "taken" function. */
  227. udelay(100);
  228. if ((taken = mcheck_taken(cpu))) {
  229. mcheck_taken(cpu) = 0;
  230. t2_mcheck_last_taken |= (1 << cpu);
  231. mb();
  232. }
  233. mcheck_expected(cpu) = 0;
  234. t2_mcheck_any_expected = 0;
  235. mb();
  236. /* If Type1 access, must reset T2 CFG so normal IO space ops work. */
  237. if (type1) {
  238. *(vulp)T2_HAE_3 = t2_cfg;
  239. mb();
  240. }
  241. }
  242. static int
  243. t2_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  244. int size, u32 *value)
  245. {
  246. unsigned long addr, pci_addr;
  247. unsigned char type1;
  248. int shift;
  249. long mask;
  250. if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
  251. return PCIBIOS_DEVICE_NOT_FOUND;
  252. mask = (size - 1) * 8;
  253. shift = (where & 3) * 8;
  254. addr = (pci_addr << 5) + mask + T2_CONF;
  255. *value = conf_read(addr, type1) >> (shift);
  256. return PCIBIOS_SUCCESSFUL;
  257. }
  258. static int
  259. t2_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
  260. u32 value)
  261. {
  262. unsigned long addr, pci_addr;
  263. unsigned char type1;
  264. long mask;
  265. if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
  266. return PCIBIOS_DEVICE_NOT_FOUND;
  267. mask = (size - 1) * 8;
  268. addr = (pci_addr << 5) + mask + T2_CONF;
  269. conf_write(addr, value << ((where & 3) * 8), type1);
  270. return PCIBIOS_SUCCESSFUL;
  271. }
  272. struct pci_ops t2_pci_ops =
  273. {
  274. .read = t2_read_config,
  275. .write = t2_write_config,
  276. };
  277. static void __init
  278. t2_direct_map_window1(unsigned long base, unsigned long length)
  279. {
  280. unsigned long temp;
  281. __direct_map_base = base;
  282. __direct_map_size = length;
  283. temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);
  284. *(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */
  285. temp = (length - 1) & 0xfff00000UL;
  286. *(vulp)T2_WMASK1 = temp;
  287. *(vulp)T2_TBASE1 = 0;
  288. #if DEBUG_PRINT_FINAL_SETTINGS
  289. printk("%s: setting WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n",
  290. __func__, *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);
  291. #endif
  292. }
  293. static void __init
  294. t2_sg_map_window2(struct pci_controller *hose,
  295. unsigned long base,
  296. unsigned long length)
  297. {
  298. unsigned long temp;
  299. /* Note we can only do 1 SG window, as the other is for direct, so
  300. do an ISA SG area, especially for the floppy. */
  301. hose->sg_isa = iommu_arena_new(hose, base, length, 0);
  302. hose->sg_pci = NULL;
  303. temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);
  304. *(vulp)T2_WBASE2 = temp | 0xc0000UL; /* OR in ENABLE/SG bits */
  305. temp = (length - 1) & 0xfff00000UL;
  306. *(vulp)T2_WMASK2 = temp;
  307. *(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1;
  308. mb();
  309. t2_pci_tbi(hose, 0, -1); /* flush TLB all */
  310. #if DEBUG_PRINT_FINAL_SETTINGS
  311. printk("%s: setting WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n",
  312. __func__, *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);
  313. #endif
  314. }
  315. static void __init
  316. t2_save_configuration(void)
  317. {
  318. #if DEBUG_PRINT_INITIAL_SETTINGS
  319. printk("%s: HAE_1 was 0x%lx\n", __func__, srm_hae); /* HW is 0 */
  320. printk("%s: HAE_2 was 0x%lx\n", __func__, *(vulp)T2_HAE_2);
  321. printk("%s: HAE_3 was 0x%lx\n", __func__, *(vulp)T2_HAE_3);
  322. printk("%s: HAE_4 was 0x%lx\n", __func__, *(vulp)T2_HAE_4);
  323. printk("%s: HBASE was 0x%lx\n", __func__, *(vulp)T2_HBASE);
  324. printk("%s: WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n", __func__,
  325. *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);
  326. printk("%s: WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n", __func__,
  327. *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);
  328. #endif
  329. /*
  330. * Save the DMA Window registers.
  331. */
  332. t2_saved_config.window[0].wbase = *(vulp)T2_WBASE1;
  333. t2_saved_config.window[0].wmask = *(vulp)T2_WMASK1;
  334. t2_saved_config.window[0].tbase = *(vulp)T2_TBASE1;
  335. t2_saved_config.window[1].wbase = *(vulp)T2_WBASE2;
  336. t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2;
  337. t2_saved_config.window[1].tbase = *(vulp)T2_TBASE2;
  338. t2_saved_config.hae_1 = srm_hae; /* HW is already set to 0 */
  339. t2_saved_config.hae_2 = *(vulp)T2_HAE_2;
  340. t2_saved_config.hae_3 = *(vulp)T2_HAE_3;
  341. t2_saved_config.hae_4 = *(vulp)T2_HAE_4;
  342. t2_saved_config.hbase = *(vulp)T2_HBASE;
  343. }
  344. void __init
  345. t2_init_arch(void)
  346. {
  347. struct pci_controller *hose;
  348. struct resource *hae_mem;
  349. unsigned long temp;
  350. unsigned int i;
  351. for (i = 0; i < NR_CPUS; i++) {
  352. mcheck_expected(i) = 0;
  353. mcheck_taken(i) = 0;
  354. }
  355. t2_mcheck_any_expected = 0;
  356. t2_mcheck_last_taken = 0;
  357. /* Enable scatter/gather TLB use. */
  358. temp = *(vulp)T2_IOCSR;
  359. if (!(temp & (0x1UL << 26))) {
  360. printk("t2_init_arch: enabling SG TLB, IOCSR was 0x%lx\n",
  361. temp);
  362. *(vulp)T2_IOCSR = temp | (0x1UL << 26);
  363. mb();
  364. *(vulp)T2_IOCSR; /* read it back to make sure */
  365. }
  366. t2_save_configuration();
  367. /*
  368. * Create our single hose.
  369. */
  370. pci_isa_hose = hose = alloc_pci_controller();
  371. hose->io_space = &ioport_resource;
  372. hae_mem = alloc_resource();
  373. hae_mem->start = 0;
  374. hae_mem->end = T2_MEM_R1_MASK;
  375. hae_mem->name = pci_hae0_name;
  376. if (request_resource(&iomem_resource, hae_mem) < 0)
  377. printk(KERN_ERR "Failed to request HAE_MEM\n");
  378. hose->mem_space = hae_mem;
  379. hose->index = 0;
  380. hose->sparse_mem_base = T2_SPARSE_MEM - IDENT_ADDR;
  381. hose->dense_mem_base = T2_DENSE_MEM - IDENT_ADDR;
  382. hose->sparse_io_base = T2_IO - IDENT_ADDR;
  383. hose->dense_io_base = 0;
  384. /*
  385. * Set up the PCI->physical memory translation windows.
  386. *
  387. * Window 1 is direct mapped.
  388. * Window 2 is scatter/gather (for ISA).
  389. */
  390. t2_direct_map_window1(T2_DIRECTMAP_START, T2_DIRECTMAP_LENGTH);
  391. /* Always make an ISA DMA window. */
  392. t2_sg_map_window2(hose, T2_ISA_SG_START, T2_ISA_SG_LENGTH);
  393. *(vulp)T2_HBASE = 0x0; /* Disable HOLES. */
  394. /* Zero HAE. */
  395. *(vulp)T2_HAE_1 = 0; mb(); /* Sparse MEM HAE */
  396. *(vulp)T2_HAE_2 = 0; mb(); /* Sparse I/O HAE */
  397. *(vulp)T2_HAE_3 = 0; mb(); /* Config Space HAE */
  398. /*
  399. * We also now zero out HAE_4, the dense memory HAE, so that
  400. * we need not account for its "offset" when accessing dense
  401. * memory resources which we allocated in our normal way. This
  402. * HAE would need to stay untouched were we to keep the SRM
  403. * resource settings.
  404. *
  405. * Thus we can now run standard X servers on SABLE/LYNX. :-)
  406. */
  407. *(vulp)T2_HAE_4 = 0; mb();
  408. }
  409. void
  410. t2_kill_arch(int mode)
  411. {
  412. /*
  413. * Restore the DMA Window registers.
  414. */
  415. *(vulp)T2_WBASE1 = t2_saved_config.window[0].wbase;
  416. *(vulp)T2_WMASK1 = t2_saved_config.window[0].wmask;
  417. *(vulp)T2_TBASE1 = t2_saved_config.window[0].tbase;
  418. *(vulp)T2_WBASE2 = t2_saved_config.window[1].wbase;
  419. *(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask;
  420. *(vulp)T2_TBASE2 = t2_saved_config.window[1].tbase;
  421. mb();
  422. *(vulp)T2_HAE_1 = srm_hae;
  423. *(vulp)T2_HAE_2 = t2_saved_config.hae_2;
  424. *(vulp)T2_HAE_3 = t2_saved_config.hae_3;
  425. *(vulp)T2_HAE_4 = t2_saved_config.hae_4;
  426. *(vulp)T2_HBASE = t2_saved_config.hbase;
  427. mb();
  428. *(vulp)T2_HBASE; /* READ it back to ensure WRITE occurred. */
  429. }
  430. void
  431. t2_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
  432. {
  433. unsigned long t2_iocsr;
  434. t2_iocsr = *(vulp)T2_IOCSR;
  435. /* set the TLB Clear bit */
  436. *(vulp)T2_IOCSR = t2_iocsr | (0x1UL << 28);
  437. mb();
  438. *(vulp)T2_IOCSR; /* read it back to make sure */
  439. /* clear the TLB Clear bit */
  440. *(vulp)T2_IOCSR = t2_iocsr & ~(0x1UL << 28);
  441. mb();
  442. *(vulp)T2_IOCSR; /* read it back to make sure */
  443. }
  444. #define SIC_SEIC (1UL << 33) /* System Event Clear */
  445. static void
  446. t2_clear_errors(int cpu)
  447. {
  448. struct sable_cpu_csr *cpu_regs;
  449. cpu_regs = (struct sable_cpu_csr *)T2_CPUn_BASE(cpu);
  450. cpu_regs->sic &= ~SIC_SEIC;
  451. /* Clear CPU errors. */
  452. cpu_regs->bcce |= cpu_regs->bcce;
  453. cpu_regs->cbe |= cpu_regs->cbe;
  454. cpu_regs->bcue |= cpu_regs->bcue;
  455. cpu_regs->dter |= cpu_regs->dter;
  456. *(vulp)T2_CERR1 |= *(vulp)T2_CERR1;
  457. *(vulp)T2_PERR1 |= *(vulp)T2_PERR1;
  458. mb();
  459. mb(); /* magic */
  460. }
  461. /*
  462. * SABLE seems to have a "broadcast" style machine check, in that all
  463. * CPUs receive it. And, the issuing CPU, in the case of PCI Config
  464. * space read/write faults, will also receive a second mcheck, upon
  465. * lowering IPL during completion processing in pci_read_config_byte()
  466. * et al.
  467. *
  468. * Hence all the taken/expected/any_expected/last_taken stuff...
  469. */
  470. void
  471. t2_machine_check(unsigned long vector, unsigned long la_ptr)
  472. {
  473. int cpu = smp_processor_id();
  474. #ifdef CONFIG_VERBOSE_MCHECK
  475. struct el_common *mchk_header = (struct el_common *)la_ptr;
  476. #endif
  477. /* Clear the error before any reporting. */
  478. mb();
  479. mb(); /* magic */
  480. draina();
  481. t2_clear_errors(cpu);
  482. /* This should not actually be done until the logout frame is
  483. examined, but, since we don't do that, go on and do this... */
  484. wrmces(0x7);
  485. mb();
  486. /* Now, do testing for the anomalous conditions. */
  487. if (!mcheck_expected(cpu) && t2_mcheck_any_expected) {
  488. /*
  489. * FUNKY: Received mcheck on a CPU and not
  490. * expecting it, but another CPU is expecting one.
  491. *
  492. * Just dismiss it for now on this CPU...
  493. */
  494. #ifdef CONFIG_VERBOSE_MCHECK
  495. if (alpha_verbose_mcheck > 1) {
  496. printk("t2_machine_check(cpu%d): any_expected 0x%x -"
  497. " (assumed) spurious -"
  498. " code 0x%x\n", cpu, t2_mcheck_any_expected,
  499. (unsigned int)mchk_header->code);
  500. }
  501. #endif
  502. return;
  503. }
  504. if (!mcheck_expected(cpu) && !t2_mcheck_any_expected) {
  505. if (t2_mcheck_last_taken & (1 << cpu)) {
  506. #ifdef CONFIG_VERBOSE_MCHECK
  507. if (alpha_verbose_mcheck > 1) {
  508. printk("t2_machine_check(cpu%d): last_taken 0x%x - "
  509. "unexpected mcheck - code 0x%x\n",
  510. cpu, t2_mcheck_last_taken,
  511. (unsigned int)mchk_header->code);
  512. }
  513. #endif
  514. t2_mcheck_last_taken = 0;
  515. mb();
  516. return;
  517. } else {
  518. t2_mcheck_last_taken = 0;
  519. mb();
  520. }
  521. }
  522. #ifdef CONFIG_VERBOSE_MCHECK
  523. if (alpha_verbose_mcheck > 1) {
  524. printk("%s t2_mcheck(cpu%d): last_taken 0x%x - "
  525. "any_expected 0x%x - code 0x%x\n",
  526. (mcheck_expected(cpu) ? "EX" : "UN"), cpu,
  527. t2_mcheck_last_taken, t2_mcheck_any_expected,
  528. (unsigned int)mchk_header->code);
  529. }
  530. #endif
  531. process_mcheck_info(vector, la_ptr, "T2", mcheck_expected(cpu));
  532. }