mach-imx51.c 2.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104
  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. #include <linux/io.h>
  13. #include <linux/irq.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/of_platform.h>
  17. #include <asm/mach/arch.h>
  18. #include <asm/mach/time.h>
  19. #include "common.h"
  20. #include "hardware.h"
  21. static void __init imx51_init_early(void)
  22. {
  23. mxc_set_cpu_type(MXC_CPU_MX51);
  24. }
  25. /*
  26. * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
  27. * the Freescale marketing division. However this did not remove the
  28. * hardware from the chip which still needs to be configured for proper
  29. * IPU support.
  30. */
  31. #define MX51_MIPI_HSC_BASE 0x83fdc000
  32. static void __init imx51_ipu_mipi_setup(void)
  33. {
  34. void __iomem *hsc_addr;
  35. hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K);
  36. WARN_ON(!hsc_addr);
  37. /* setup MIPI module to legacy mode */
  38. imx_writel(0xf00, hsc_addr);
  39. /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
  40. imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800);
  41. iounmap(hsc_addr);
  42. }
  43. static void __init imx51_m4if_setup(void)
  44. {
  45. void __iomem *m4if_base;
  46. struct device_node *np;
  47. np = of_find_compatible_node(NULL, NULL, "fsl,imx51-m4if");
  48. if (!np)
  49. return;
  50. m4if_base = of_iomap(np, 0);
  51. of_node_put(np);
  52. if (!m4if_base) {
  53. pr_err("Unable to map M4IF registers\n");
  54. return;
  55. }
  56. /*
  57. * Configure VPU and IPU with higher priorities
  58. * in order to avoid artifacts during video playback
  59. */
  60. writel_relaxed(0x00000203, m4if_base + 0x40);
  61. writel_relaxed(0x00000000, m4if_base + 0x44);
  62. writel_relaxed(0x00120125, m4if_base + 0x9c);
  63. writel_relaxed(0x001901A3, m4if_base + 0x48);
  64. iounmap(m4if_base);
  65. }
  66. static void __init imx51_dt_init(void)
  67. {
  68. imx51_ipu_mipi_setup();
  69. imx_src_init();
  70. imx51_m4if_setup();
  71. imx5_pmu_init();
  72. imx_aips_allow_unprivileged_access("fsl,imx51-aipstz");
  73. }
  74. static void __init imx51_init_late(void)
  75. {
  76. mx51_neon_fixup();
  77. imx51_pm_init();
  78. }
  79. static const char * const imx51_dt_board_compat[] __initconst = {
  80. "fsl,imx51",
  81. NULL
  82. };
  83. DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
  84. .init_early = imx51_init_early,
  85. .init_machine = imx51_dt_init,
  86. .init_late = imx51_init_late,
  87. .dt_compat = imx51_dt_board_compat,
  88. MACHINE_END