mca.c 61 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145
  1. /*
  2. * File: mca.c
  3. * Purpose: Generic MCA handling layer
  4. *
  5. * Copyright (C) 2003 Hewlett-Packard Co
  6. * David Mosberger-Tang <davidm@hpl.hp.com>
  7. *
  8. * Copyright (C) 2002 Dell Inc.
  9. * Copyright (C) Matt Domsch <Matt_Domsch@dell.com>
  10. *
  11. * Copyright (C) 2002 Intel
  12. * Copyright (C) Jenna Hall <jenna.s.hall@intel.com>
  13. *
  14. * Copyright (C) 2001 Intel
  15. * Copyright (C) Fred Lewis <frederick.v.lewis@intel.com>
  16. *
  17. * Copyright (C) 2000 Intel
  18. * Copyright (C) Chuck Fleckenstein <cfleck@co.intel.com>
  19. *
  20. * Copyright (C) 1999, 2004-2008 Silicon Graphics, Inc.
  21. * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
  22. *
  23. * Copyright (C) 2006 FUJITSU LIMITED
  24. * Copyright (C) Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
  25. *
  26. * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com>
  27. * Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
  28. * added min save state dump, added INIT handler.
  29. *
  30. * 2001-01-03 Fred Lewis <frederick.v.lewis@intel.com>
  31. * Added setup of CMCI and CPEI IRQs, logging of corrected platform
  32. * errors, completed code for logging of corrected & uncorrected
  33. * machine check errors, and updated for conformance with Nov. 2000
  34. * revision of the SAL 3.0 spec.
  35. *
  36. * 2002-01-04 Jenna Hall <jenna.s.hall@intel.com>
  37. * Aligned MCA stack to 16 bytes, added platform vs. CPU error flag,
  38. * set SAL default return values, changed error record structure to
  39. * linked list, added init call to sal_get_state_info_size().
  40. *
  41. * 2002-03-25 Matt Domsch <Matt_Domsch@dell.com>
  42. * GUID cleanups.
  43. *
  44. * 2003-04-15 David Mosberger-Tang <davidm@hpl.hp.com>
  45. * Added INIT backtrace support.
  46. *
  47. * 2003-12-08 Keith Owens <kaos@sgi.com>
  48. * smp_call_function() must not be called from interrupt context
  49. * (can deadlock on tasklist_lock).
  50. * Use keventd to call smp_call_function().
  51. *
  52. * 2004-02-01 Keith Owens <kaos@sgi.com>
  53. * Avoid deadlock when using printk() for MCA and INIT records.
  54. * Delete all record printing code, moved to salinfo_decode in user
  55. * space. Mark variables and functions static where possible.
  56. * Delete dead variables and functions. Reorder to remove the need
  57. * for forward declarations and to consolidate related code.
  58. *
  59. * 2005-08-12 Keith Owens <kaos@sgi.com>
  60. * Convert MCA/INIT handlers to use per event stacks and SAL/OS
  61. * state.
  62. *
  63. * 2005-10-07 Keith Owens <kaos@sgi.com>
  64. * Add notify_die() hooks.
  65. *
  66. * 2006-09-15 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
  67. * Add printing support for MCA/INIT.
  68. *
  69. * 2007-04-27 Russ Anderson <rja@sgi.com>
  70. * Support multiple cpus going through OS_MCA in the same event.
  71. */
  72. #include <linux/jiffies.h>
  73. #include <linux/types.h>
  74. #include <linux/init.h>
  75. #include <linux/sched/signal.h>
  76. #include <linux/sched/debug.h>
  77. #include <linux/sched/task.h>
  78. #include <linux/interrupt.h>
  79. #include <linux/irq.h>
  80. #include <linux/bootmem.h>
  81. #include <linux/acpi.h>
  82. #include <linux/timer.h>
  83. #include <linux/module.h>
  84. #include <linux/kernel.h>
  85. #include <linux/smp.h>
  86. #include <linux/workqueue.h>
  87. #include <linux/cpumask.h>
  88. #include <linux/kdebug.h>
  89. #include <linux/cpu.h>
  90. #include <linux/gfp.h>
  91. #include <asm/delay.h>
  92. #include <asm/machvec.h>
  93. #include <asm/meminit.h>
  94. #include <asm/page.h>
  95. #include <asm/ptrace.h>
  96. #include <asm/sal.h>
  97. #include <asm/mca.h>
  98. #include <asm/kexec.h>
  99. #include <asm/irq.h>
  100. #include <asm/hw_irq.h>
  101. #include <asm/tlb.h>
  102. #include "mca_drv.h"
  103. #include "entry.h"
  104. #if defined(IA64_MCA_DEBUG_INFO)
  105. # define IA64_MCA_DEBUG(fmt...) printk(fmt)
  106. #else
  107. # define IA64_MCA_DEBUG(fmt...)
  108. #endif
  109. #define NOTIFY_INIT(event, regs, arg, spin) \
  110. do { \
  111. if ((notify_die((event), "INIT", (regs), (arg), 0, 0) \
  112. == NOTIFY_STOP) && ((spin) == 1)) \
  113. ia64_mca_spin(__func__); \
  114. } while (0)
  115. #define NOTIFY_MCA(event, regs, arg, spin) \
  116. do { \
  117. if ((notify_die((event), "MCA", (regs), (arg), 0, 0) \
  118. == NOTIFY_STOP) && ((spin) == 1)) \
  119. ia64_mca_spin(__func__); \
  120. } while (0)
  121. /* Used by mca_asm.S */
  122. DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
  123. DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
  124. DEFINE_PER_CPU(u64, ia64_mca_pal_pte); /* PTE to map PAL code */
  125. DEFINE_PER_CPU(u64, ia64_mca_pal_base); /* vaddr PAL code granule */
  126. DEFINE_PER_CPU(u64, ia64_mca_tr_reload); /* Flag for TR reload */
  127. unsigned long __per_cpu_mca[NR_CPUS];
  128. /* In mca_asm.S */
  129. extern void ia64_os_init_dispatch_monarch (void);
  130. extern void ia64_os_init_dispatch_slave (void);
  131. static int monarch_cpu = -1;
  132. static ia64_mc_info_t ia64_mc_info;
  133. #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
  134. #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */
  135. #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */
  136. #define CPE_HISTORY_LENGTH 5
  137. #define CMC_HISTORY_LENGTH 5
  138. #ifdef CONFIG_ACPI
  139. static struct timer_list cpe_poll_timer;
  140. #endif
  141. static struct timer_list cmc_poll_timer;
  142. /*
  143. * This variable tells whether we are currently in polling mode.
  144. * Start with this in the wrong state so we won't play w/ timers
  145. * before the system is ready.
  146. */
  147. static int cmc_polling_enabled = 1;
  148. /*
  149. * Clearing this variable prevents CPE polling from getting activated
  150. * in mca_late_init. Use it if your system doesn't provide a CPEI,
  151. * but encounters problems retrieving CPE logs. This should only be
  152. * necessary for debugging.
  153. */
  154. static int cpe_poll_enabled = 1;
  155. extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
  156. static int mca_init __initdata;
  157. /*
  158. * limited & delayed printing support for MCA/INIT handler
  159. */
  160. #define mprintk(fmt...) ia64_mca_printk(fmt)
  161. #define MLOGBUF_SIZE (512+256*NR_CPUS)
  162. #define MLOGBUF_MSGMAX 256
  163. static char mlogbuf[MLOGBUF_SIZE];
  164. static DEFINE_SPINLOCK(mlogbuf_wlock); /* mca context only */
  165. static DEFINE_SPINLOCK(mlogbuf_rlock); /* normal context only */
  166. static unsigned long mlogbuf_start;
  167. static unsigned long mlogbuf_end;
  168. static unsigned int mlogbuf_finished = 0;
  169. static unsigned long mlogbuf_timestamp = 0;
  170. static int loglevel_save = -1;
  171. #define BREAK_LOGLEVEL(__console_loglevel) \
  172. oops_in_progress = 1; \
  173. if (loglevel_save < 0) \
  174. loglevel_save = __console_loglevel; \
  175. __console_loglevel = 15;
  176. #define RESTORE_LOGLEVEL(__console_loglevel) \
  177. if (loglevel_save >= 0) { \
  178. __console_loglevel = loglevel_save; \
  179. loglevel_save = -1; \
  180. } \
  181. mlogbuf_finished = 0; \
  182. oops_in_progress = 0;
  183. /*
  184. * Push messages into buffer, print them later if not urgent.
  185. */
  186. void ia64_mca_printk(const char *fmt, ...)
  187. {
  188. va_list args;
  189. int printed_len;
  190. char temp_buf[MLOGBUF_MSGMAX];
  191. char *p;
  192. va_start(args, fmt);
  193. printed_len = vscnprintf(temp_buf, sizeof(temp_buf), fmt, args);
  194. va_end(args);
  195. /* Copy the output into mlogbuf */
  196. if (oops_in_progress) {
  197. /* mlogbuf was abandoned, use printk directly instead. */
  198. printk("%s", temp_buf);
  199. } else {
  200. spin_lock(&mlogbuf_wlock);
  201. for (p = temp_buf; *p; p++) {
  202. unsigned long next = (mlogbuf_end + 1) % MLOGBUF_SIZE;
  203. if (next != mlogbuf_start) {
  204. mlogbuf[mlogbuf_end] = *p;
  205. mlogbuf_end = next;
  206. } else {
  207. /* buffer full */
  208. break;
  209. }
  210. }
  211. mlogbuf[mlogbuf_end] = '\0';
  212. spin_unlock(&mlogbuf_wlock);
  213. }
  214. }
  215. EXPORT_SYMBOL(ia64_mca_printk);
  216. /*
  217. * Print buffered messages.
  218. * NOTE: call this after returning normal context. (ex. from salinfod)
  219. */
  220. void ia64_mlogbuf_dump(void)
  221. {
  222. char temp_buf[MLOGBUF_MSGMAX];
  223. char *p;
  224. unsigned long index;
  225. unsigned long flags;
  226. unsigned int printed_len;
  227. /* Get output from mlogbuf */
  228. while (mlogbuf_start != mlogbuf_end) {
  229. temp_buf[0] = '\0';
  230. p = temp_buf;
  231. printed_len = 0;
  232. spin_lock_irqsave(&mlogbuf_rlock, flags);
  233. index = mlogbuf_start;
  234. while (index != mlogbuf_end) {
  235. *p = mlogbuf[index];
  236. index = (index + 1) % MLOGBUF_SIZE;
  237. if (!*p)
  238. break;
  239. p++;
  240. if (++printed_len >= MLOGBUF_MSGMAX - 1)
  241. break;
  242. }
  243. *p = '\0';
  244. if (temp_buf[0])
  245. printk("%s", temp_buf);
  246. mlogbuf_start = index;
  247. mlogbuf_timestamp = 0;
  248. spin_unlock_irqrestore(&mlogbuf_rlock, flags);
  249. }
  250. }
  251. EXPORT_SYMBOL(ia64_mlogbuf_dump);
  252. /*
  253. * Call this if system is going to down or if immediate flushing messages to
  254. * console is required. (ex. recovery was failed, crash dump is going to be
  255. * invoked, long-wait rendezvous etc.)
  256. * NOTE: this should be called from monarch.
  257. */
  258. static void ia64_mlogbuf_finish(int wait)
  259. {
  260. BREAK_LOGLEVEL(console_loglevel);
  261. spin_lock_init(&mlogbuf_rlock);
  262. ia64_mlogbuf_dump();
  263. printk(KERN_EMERG "mlogbuf_finish: printing switched to urgent mode, "
  264. "MCA/INIT might be dodgy or fail.\n");
  265. if (!wait)
  266. return;
  267. /* wait for console */
  268. printk("Delaying for 5 seconds...\n");
  269. udelay(5*1000000);
  270. mlogbuf_finished = 1;
  271. }
  272. /*
  273. * Print buffered messages from INIT context.
  274. */
  275. static void ia64_mlogbuf_dump_from_init(void)
  276. {
  277. if (mlogbuf_finished)
  278. return;
  279. if (mlogbuf_timestamp &&
  280. time_before(jiffies, mlogbuf_timestamp + 30 * HZ)) {
  281. printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT "
  282. " and the system seems to be messed up.\n");
  283. ia64_mlogbuf_finish(0);
  284. return;
  285. }
  286. if (!spin_trylock(&mlogbuf_rlock)) {
  287. printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT. "
  288. "Generated messages other than stack dump will be "
  289. "buffered to mlogbuf and will be printed later.\n");
  290. printk(KERN_ERR "INIT: If messages would not printed after "
  291. "this INIT, wait 30sec and assert INIT again.\n");
  292. if (!mlogbuf_timestamp)
  293. mlogbuf_timestamp = jiffies;
  294. return;
  295. }
  296. spin_unlock(&mlogbuf_rlock);
  297. ia64_mlogbuf_dump();
  298. }
  299. static inline void
  300. ia64_mca_spin(const char *func)
  301. {
  302. if (monarch_cpu == smp_processor_id())
  303. ia64_mlogbuf_finish(0);
  304. mprintk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
  305. while (1)
  306. cpu_relax();
  307. }
  308. /*
  309. * IA64_MCA log support
  310. */
  311. #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */
  312. #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */
  313. typedef struct ia64_state_log_s
  314. {
  315. spinlock_t isl_lock;
  316. int isl_index;
  317. unsigned long isl_count;
  318. ia64_err_rec_t *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
  319. } ia64_state_log_t;
  320. static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
  321. #define IA64_LOG_ALLOCATE(it, size) \
  322. {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
  323. (ia64_err_rec_t *)alloc_bootmem(size); \
  324. ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
  325. (ia64_err_rec_t *)alloc_bootmem(size);}
  326. #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
  327. #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
  328. #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
  329. #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index
  330. #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index
  331. #define IA64_LOG_INDEX_INC(it) \
  332. {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
  333. ia64_state_log[it].isl_count++;}
  334. #define IA64_LOG_INDEX_DEC(it) \
  335. ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
  336. #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
  337. #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
  338. #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count
  339. /*
  340. * ia64_log_init
  341. * Reset the OS ia64 log buffer
  342. * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
  343. * Outputs : None
  344. */
  345. static void __init
  346. ia64_log_init(int sal_info_type)
  347. {
  348. u64 max_size = 0;
  349. IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
  350. IA64_LOG_LOCK_INIT(sal_info_type);
  351. // SAL will tell us the maximum size of any error record of this type
  352. max_size = ia64_sal_get_state_info_size(sal_info_type);
  353. if (!max_size)
  354. /* alloc_bootmem() doesn't like zero-sized allocations! */
  355. return;
  356. // set up OS data structures to hold error info
  357. IA64_LOG_ALLOCATE(sal_info_type, max_size);
  358. memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
  359. memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
  360. }
  361. /*
  362. * ia64_log_get
  363. *
  364. * Get the current MCA log from SAL and copy it into the OS log buffer.
  365. *
  366. * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
  367. * irq_safe whether you can use printk at this point
  368. * Outputs : size (total record length)
  369. * *buffer (ptr to error record)
  370. *
  371. */
  372. static u64
  373. ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
  374. {
  375. sal_log_record_header_t *log_buffer;
  376. u64 total_len = 0;
  377. unsigned long s;
  378. IA64_LOG_LOCK(sal_info_type);
  379. /* Get the process state information */
  380. log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
  381. total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
  382. if (total_len) {
  383. IA64_LOG_INDEX_INC(sal_info_type);
  384. IA64_LOG_UNLOCK(sal_info_type);
  385. if (irq_safe) {
  386. IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. Record length = %ld\n",
  387. __func__, sal_info_type, total_len);
  388. }
  389. *buffer = (u8 *) log_buffer;
  390. return total_len;
  391. } else {
  392. IA64_LOG_UNLOCK(sal_info_type);
  393. return 0;
  394. }
  395. }
  396. /*
  397. * ia64_mca_log_sal_error_record
  398. *
  399. * This function retrieves a specified error record type from SAL
  400. * and wakes up any processes waiting for error records.
  401. *
  402. * Inputs : sal_info_type (Type of error record MCA/CMC/CPE)
  403. * FIXME: remove MCA and irq_safe.
  404. */
  405. static void
  406. ia64_mca_log_sal_error_record(int sal_info_type)
  407. {
  408. u8 *buffer;
  409. sal_log_record_header_t *rh;
  410. u64 size;
  411. int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
  412. #ifdef IA64_MCA_DEBUG_INFO
  413. static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
  414. #endif
  415. size = ia64_log_get(sal_info_type, &buffer, irq_safe);
  416. if (!size)
  417. return;
  418. salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
  419. if (irq_safe)
  420. IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
  421. smp_processor_id(),
  422. sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
  423. /* Clear logs from corrected errors in case there's no user-level logger */
  424. rh = (sal_log_record_header_t *)buffer;
  425. if (rh->severity == sal_log_severity_corrected)
  426. ia64_sal_clear_state_info(sal_info_type);
  427. }
  428. /*
  429. * search_mca_table
  430. * See if the MCA surfaced in an instruction range
  431. * that has been tagged as recoverable.
  432. *
  433. * Inputs
  434. * first First address range to check
  435. * last Last address range to check
  436. * ip Instruction pointer, address we are looking for
  437. *
  438. * Return value:
  439. * 1 on Success (in the table)/ 0 on Failure (not in the table)
  440. */
  441. int
  442. search_mca_table (const struct mca_table_entry *first,
  443. const struct mca_table_entry *last,
  444. unsigned long ip)
  445. {
  446. const struct mca_table_entry *curr;
  447. u64 curr_start, curr_end;
  448. curr = first;
  449. while (curr <= last) {
  450. curr_start = (u64) &curr->start_addr + curr->start_addr;
  451. curr_end = (u64) &curr->end_addr + curr->end_addr;
  452. if ((ip >= curr_start) && (ip <= curr_end)) {
  453. return 1;
  454. }
  455. curr++;
  456. }
  457. return 0;
  458. }
  459. /* Given an address, look for it in the mca tables. */
  460. int mca_recover_range(unsigned long addr)
  461. {
  462. extern struct mca_table_entry __start___mca_table[];
  463. extern struct mca_table_entry __stop___mca_table[];
  464. return search_mca_table(__start___mca_table, __stop___mca_table-1, addr);
  465. }
  466. EXPORT_SYMBOL_GPL(mca_recover_range);
  467. #ifdef CONFIG_ACPI
  468. int cpe_vector = -1;
  469. int ia64_cpe_irq = -1;
  470. static irqreturn_t
  471. ia64_mca_cpe_int_handler (int cpe_irq, void *arg)
  472. {
  473. static unsigned long cpe_history[CPE_HISTORY_LENGTH];
  474. static int index;
  475. static DEFINE_SPINLOCK(cpe_history_lock);
  476. IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
  477. __func__, cpe_irq, smp_processor_id());
  478. /* SAL spec states this should run w/ interrupts enabled */
  479. local_irq_enable();
  480. spin_lock(&cpe_history_lock);
  481. if (!cpe_poll_enabled && cpe_vector >= 0) {
  482. int i, count = 1; /* we know 1 happened now */
  483. unsigned long now = jiffies;
  484. for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
  485. if (now - cpe_history[i] <= HZ)
  486. count++;
  487. }
  488. IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
  489. if (count >= CPE_HISTORY_LENGTH) {
  490. cpe_poll_enabled = 1;
  491. spin_unlock(&cpe_history_lock);
  492. disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
  493. /*
  494. * Corrected errors will still be corrected, but
  495. * make sure there's a log somewhere that indicates
  496. * something is generating more than we can handle.
  497. */
  498. printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
  499. mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
  500. /* lock already released, get out now */
  501. goto out;
  502. } else {
  503. cpe_history[index++] = now;
  504. if (index == CPE_HISTORY_LENGTH)
  505. index = 0;
  506. }
  507. }
  508. spin_unlock(&cpe_history_lock);
  509. out:
  510. /* Get the CPE error record and log it */
  511. ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
  512. local_irq_disable();
  513. return IRQ_HANDLED;
  514. }
  515. #endif /* CONFIG_ACPI */
  516. #ifdef CONFIG_ACPI
  517. /*
  518. * ia64_mca_register_cpev
  519. *
  520. * Register the corrected platform error vector with SAL.
  521. *
  522. * Inputs
  523. * cpev Corrected Platform Error Vector number
  524. *
  525. * Outputs
  526. * None
  527. */
  528. void
  529. ia64_mca_register_cpev (int cpev)
  530. {
  531. /* Register the CPE interrupt vector with SAL */
  532. struct ia64_sal_retval isrv;
  533. isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
  534. if (isrv.status) {
  535. printk(KERN_ERR "Failed to register Corrected Platform "
  536. "Error interrupt vector with SAL (status %ld)\n", isrv.status);
  537. return;
  538. }
  539. IA64_MCA_DEBUG("%s: corrected platform error "
  540. "vector %#x registered\n", __func__, cpev);
  541. }
  542. #endif /* CONFIG_ACPI */
  543. /*
  544. * ia64_mca_cmc_vector_setup
  545. *
  546. * Setup the corrected machine check vector register in the processor.
  547. * (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
  548. * This function is invoked on a per-processor basis.
  549. *
  550. * Inputs
  551. * None
  552. *
  553. * Outputs
  554. * None
  555. */
  556. void
  557. ia64_mca_cmc_vector_setup (void)
  558. {
  559. cmcv_reg_t cmcv;
  560. cmcv.cmcv_regval = 0;
  561. cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */
  562. cmcv.cmcv_vector = IA64_CMC_VECTOR;
  563. ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
  564. IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x registered.\n",
  565. __func__, smp_processor_id(), IA64_CMC_VECTOR);
  566. IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
  567. __func__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
  568. }
  569. /*
  570. * ia64_mca_cmc_vector_disable
  571. *
  572. * Mask the corrected machine check vector register in the processor.
  573. * This function is invoked on a per-processor basis.
  574. *
  575. * Inputs
  576. * dummy(unused)
  577. *
  578. * Outputs
  579. * None
  580. */
  581. static void
  582. ia64_mca_cmc_vector_disable (void *dummy)
  583. {
  584. cmcv_reg_t cmcv;
  585. cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
  586. cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
  587. ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
  588. IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x disabled.\n",
  589. __func__, smp_processor_id(), cmcv.cmcv_vector);
  590. }
  591. /*
  592. * ia64_mca_cmc_vector_enable
  593. *
  594. * Unmask the corrected machine check vector register in the processor.
  595. * This function is invoked on a per-processor basis.
  596. *
  597. * Inputs
  598. * dummy(unused)
  599. *
  600. * Outputs
  601. * None
  602. */
  603. static void
  604. ia64_mca_cmc_vector_enable (void *dummy)
  605. {
  606. cmcv_reg_t cmcv;
  607. cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
  608. cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
  609. ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
  610. IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x enabled.\n",
  611. __func__, smp_processor_id(), cmcv.cmcv_vector);
  612. }
  613. /*
  614. * ia64_mca_cmc_vector_disable_keventd
  615. *
  616. * Called via keventd (smp_call_function() is not safe in interrupt context) to
  617. * disable the cmc interrupt vector.
  618. */
  619. static void
  620. ia64_mca_cmc_vector_disable_keventd(struct work_struct *unused)
  621. {
  622. on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 0);
  623. }
  624. /*
  625. * ia64_mca_cmc_vector_enable_keventd
  626. *
  627. * Called via keventd (smp_call_function() is not safe in interrupt context) to
  628. * enable the cmc interrupt vector.
  629. */
  630. static void
  631. ia64_mca_cmc_vector_enable_keventd(struct work_struct *unused)
  632. {
  633. on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 0);
  634. }
  635. /*
  636. * ia64_mca_wakeup
  637. *
  638. * Send an inter-cpu interrupt to wake-up a particular cpu.
  639. *
  640. * Inputs : cpuid
  641. * Outputs : None
  642. */
  643. static void
  644. ia64_mca_wakeup(int cpu)
  645. {
  646. platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
  647. }
  648. /*
  649. * ia64_mca_wakeup_all
  650. *
  651. * Wakeup all the slave cpus which have rendez'ed previously.
  652. *
  653. * Inputs : None
  654. * Outputs : None
  655. */
  656. static void
  657. ia64_mca_wakeup_all(void)
  658. {
  659. int cpu;
  660. /* Clear the Rendez checkin flag for all cpus */
  661. for_each_online_cpu(cpu) {
  662. if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
  663. ia64_mca_wakeup(cpu);
  664. }
  665. }
  666. /*
  667. * ia64_mca_rendez_interrupt_handler
  668. *
  669. * This is handler used to put slave processors into spinloop
  670. * while the monarch processor does the mca handling and later
  671. * wake each slave up once the monarch is done. The state
  672. * IA64_MCA_RENDEZ_CHECKIN_DONE indicates the cpu is rendez'ed
  673. * in SAL. The state IA64_MCA_RENDEZ_CHECKIN_NOTDONE indicates
  674. * the cpu has come out of OS rendezvous.
  675. *
  676. * Inputs : None
  677. * Outputs : None
  678. */
  679. static irqreturn_t
  680. ia64_mca_rendez_int_handler(int rendez_irq, void *arg)
  681. {
  682. unsigned long flags;
  683. int cpu = smp_processor_id();
  684. struct ia64_mca_notify_die nd =
  685. { .sos = NULL, .monarch_cpu = &monarch_cpu };
  686. /* Mask all interrupts */
  687. local_irq_save(flags);
  688. NOTIFY_MCA(DIE_MCA_RENDZVOUS_ENTER, get_irq_regs(), (long)&nd, 1);
  689. ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
  690. /* Register with the SAL monarch that the slave has
  691. * reached SAL
  692. */
  693. ia64_sal_mc_rendez();
  694. NOTIFY_MCA(DIE_MCA_RENDZVOUS_PROCESS, get_irq_regs(), (long)&nd, 1);
  695. /* Wait for the monarch cpu to exit. */
  696. while (monarch_cpu != -1)
  697. cpu_relax(); /* spin until monarch leaves */
  698. NOTIFY_MCA(DIE_MCA_RENDZVOUS_LEAVE, get_irq_regs(), (long)&nd, 1);
  699. ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
  700. /* Enable all interrupts */
  701. local_irq_restore(flags);
  702. return IRQ_HANDLED;
  703. }
  704. /*
  705. * ia64_mca_wakeup_int_handler
  706. *
  707. * The interrupt handler for processing the inter-cpu interrupt to the
  708. * slave cpu which was spinning in the rendez loop.
  709. * Since this spinning is done by turning off the interrupts and
  710. * polling on the wakeup-interrupt bit in the IRR, there is
  711. * nothing useful to be done in the handler.
  712. *
  713. * Inputs : wakeup_irq (Wakeup-interrupt bit)
  714. * arg (Interrupt handler specific argument)
  715. * Outputs : None
  716. *
  717. */
  718. static irqreturn_t
  719. ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg)
  720. {
  721. return IRQ_HANDLED;
  722. }
  723. /* Function pointer for extra MCA recovery */
  724. int (*ia64_mca_ucmc_extension)
  725. (void*,struct ia64_sal_os_state*)
  726. = NULL;
  727. int
  728. ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
  729. {
  730. if (ia64_mca_ucmc_extension)
  731. return 1;
  732. ia64_mca_ucmc_extension = fn;
  733. return 0;
  734. }
  735. void
  736. ia64_unreg_MCA_extension(void)
  737. {
  738. if (ia64_mca_ucmc_extension)
  739. ia64_mca_ucmc_extension = NULL;
  740. }
  741. EXPORT_SYMBOL(ia64_reg_MCA_extension);
  742. EXPORT_SYMBOL(ia64_unreg_MCA_extension);
  743. static inline void
  744. copy_reg(const u64 *fr, u64 fnat, unsigned long *tr, unsigned long *tnat)
  745. {
  746. u64 fslot, tslot, nat;
  747. *tr = *fr;
  748. fslot = ((unsigned long)fr >> 3) & 63;
  749. tslot = ((unsigned long)tr >> 3) & 63;
  750. *tnat &= ~(1UL << tslot);
  751. nat = (fnat >> fslot) & 1;
  752. *tnat |= (nat << tslot);
  753. }
  754. /* Change the comm field on the MCA/INT task to include the pid that
  755. * was interrupted, it makes for easier debugging. If that pid was 0
  756. * (swapper or nested MCA/INIT) then use the start of the previous comm
  757. * field suffixed with its cpu.
  758. */
  759. static void
  760. ia64_mca_modify_comm(const struct task_struct *previous_current)
  761. {
  762. char *p, comm[sizeof(current->comm)];
  763. if (previous_current->pid)
  764. snprintf(comm, sizeof(comm), "%s %d",
  765. current->comm, previous_current->pid);
  766. else {
  767. int l;
  768. if ((p = strchr(previous_current->comm, ' ')))
  769. l = p - previous_current->comm;
  770. else
  771. l = strlen(previous_current->comm);
  772. snprintf(comm, sizeof(comm), "%s %*s %d",
  773. current->comm, l, previous_current->comm,
  774. task_thread_info(previous_current)->cpu);
  775. }
  776. memcpy(current->comm, comm, sizeof(current->comm));
  777. }
  778. static void
  779. finish_pt_regs(struct pt_regs *regs, struct ia64_sal_os_state *sos,
  780. unsigned long *nat)
  781. {
  782. const pal_min_state_area_t *ms = sos->pal_min_state;
  783. const u64 *bank;
  784. /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
  785. * pmsa_{xip,xpsr,xfs}
  786. */
  787. if (ia64_psr(regs)->ic) {
  788. regs->cr_iip = ms->pmsa_iip;
  789. regs->cr_ipsr = ms->pmsa_ipsr;
  790. regs->cr_ifs = ms->pmsa_ifs;
  791. } else {
  792. regs->cr_iip = ms->pmsa_xip;
  793. regs->cr_ipsr = ms->pmsa_xpsr;
  794. regs->cr_ifs = ms->pmsa_xfs;
  795. sos->iip = ms->pmsa_iip;
  796. sos->ipsr = ms->pmsa_ipsr;
  797. sos->ifs = ms->pmsa_ifs;
  798. }
  799. regs->pr = ms->pmsa_pr;
  800. regs->b0 = ms->pmsa_br0;
  801. regs->ar_rsc = ms->pmsa_rsc;
  802. copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &regs->r1, nat);
  803. copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &regs->r2, nat);
  804. copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &regs->r3, nat);
  805. copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &regs->r8, nat);
  806. copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &regs->r9, nat);
  807. copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &regs->r10, nat);
  808. copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &regs->r11, nat);
  809. copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &regs->r12, nat);
  810. copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &regs->r13, nat);
  811. copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &regs->r14, nat);
  812. copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &regs->r15, nat);
  813. if (ia64_psr(regs)->bn)
  814. bank = ms->pmsa_bank1_gr;
  815. else
  816. bank = ms->pmsa_bank0_gr;
  817. copy_reg(&bank[16-16], ms->pmsa_nat_bits, &regs->r16, nat);
  818. copy_reg(&bank[17-16], ms->pmsa_nat_bits, &regs->r17, nat);
  819. copy_reg(&bank[18-16], ms->pmsa_nat_bits, &regs->r18, nat);
  820. copy_reg(&bank[19-16], ms->pmsa_nat_bits, &regs->r19, nat);
  821. copy_reg(&bank[20-16], ms->pmsa_nat_bits, &regs->r20, nat);
  822. copy_reg(&bank[21-16], ms->pmsa_nat_bits, &regs->r21, nat);
  823. copy_reg(&bank[22-16], ms->pmsa_nat_bits, &regs->r22, nat);
  824. copy_reg(&bank[23-16], ms->pmsa_nat_bits, &regs->r23, nat);
  825. copy_reg(&bank[24-16], ms->pmsa_nat_bits, &regs->r24, nat);
  826. copy_reg(&bank[25-16], ms->pmsa_nat_bits, &regs->r25, nat);
  827. copy_reg(&bank[26-16], ms->pmsa_nat_bits, &regs->r26, nat);
  828. copy_reg(&bank[27-16], ms->pmsa_nat_bits, &regs->r27, nat);
  829. copy_reg(&bank[28-16], ms->pmsa_nat_bits, &regs->r28, nat);
  830. copy_reg(&bank[29-16], ms->pmsa_nat_bits, &regs->r29, nat);
  831. copy_reg(&bank[30-16], ms->pmsa_nat_bits, &regs->r30, nat);
  832. copy_reg(&bank[31-16], ms->pmsa_nat_bits, &regs->r31, nat);
  833. }
  834. /* On entry to this routine, we are running on the per cpu stack, see
  835. * mca_asm.h. The original stack has not been touched by this event. Some of
  836. * the original stack's registers will be in the RBS on this stack. This stack
  837. * also contains a partial pt_regs and switch_stack, the rest of the data is in
  838. * PAL minstate.
  839. *
  840. * The first thing to do is modify the original stack to look like a blocked
  841. * task so we can run backtrace on the original task. Also mark the per cpu
  842. * stack as current to ensure that we use the correct task state, it also means
  843. * that we can do backtrace on the MCA/INIT handler code itself.
  844. */
  845. static struct task_struct *
  846. ia64_mca_modify_original_stack(struct pt_regs *regs,
  847. const struct switch_stack *sw,
  848. struct ia64_sal_os_state *sos,
  849. const char *type)
  850. {
  851. char *p;
  852. ia64_va va;
  853. extern char ia64_leave_kernel[]; /* Need asm address, not function descriptor */
  854. const pal_min_state_area_t *ms = sos->pal_min_state;
  855. struct task_struct *previous_current;
  856. struct pt_regs *old_regs;
  857. struct switch_stack *old_sw;
  858. unsigned size = sizeof(struct pt_regs) +
  859. sizeof(struct switch_stack) + 16;
  860. unsigned long *old_bspstore, *old_bsp;
  861. unsigned long *new_bspstore, *new_bsp;
  862. unsigned long old_unat, old_rnat, new_rnat, nat;
  863. u64 slots, loadrs = regs->loadrs;
  864. u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
  865. u64 ar_bspstore = regs->ar_bspstore;
  866. u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
  867. const char *msg;
  868. int cpu = smp_processor_id();
  869. previous_current = curr_task(cpu);
  870. ia64_set_curr_task(cpu, current);
  871. if ((p = strchr(current->comm, ' ')))
  872. *p = '\0';
  873. /* Best effort attempt to cope with MCA/INIT delivered while in
  874. * physical mode.
  875. */
  876. regs->cr_ipsr = ms->pmsa_ipsr;
  877. if (ia64_psr(regs)->dt == 0) {
  878. va.l = r12;
  879. if (va.f.reg == 0) {
  880. va.f.reg = 7;
  881. r12 = va.l;
  882. }
  883. va.l = r13;
  884. if (va.f.reg == 0) {
  885. va.f.reg = 7;
  886. r13 = va.l;
  887. }
  888. }
  889. if (ia64_psr(regs)->rt == 0) {
  890. va.l = ar_bspstore;
  891. if (va.f.reg == 0) {
  892. va.f.reg = 7;
  893. ar_bspstore = va.l;
  894. }
  895. va.l = ar_bsp;
  896. if (va.f.reg == 0) {
  897. va.f.reg = 7;
  898. ar_bsp = va.l;
  899. }
  900. }
  901. /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
  902. * have been copied to the old stack, the old stack may fail the
  903. * validation tests below. So ia64_old_stack() must restore the dirty
  904. * registers from the new stack. The old and new bspstore probably
  905. * have different alignments, so loadrs calculated on the old bsp
  906. * cannot be used to restore from the new bsp. Calculate a suitable
  907. * loadrs for the new stack and save it in the new pt_regs, where
  908. * ia64_old_stack() can get it.
  909. */
  910. old_bspstore = (unsigned long *)ar_bspstore;
  911. old_bsp = (unsigned long *)ar_bsp;
  912. slots = ia64_rse_num_regs(old_bspstore, old_bsp);
  913. new_bspstore = (unsigned long *)((u64)current + IA64_RBS_OFFSET);
  914. new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
  915. regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
  916. /* Verify the previous stack state before we change it */
  917. if (user_mode(regs)) {
  918. msg = "occurred in user space";
  919. /* previous_current is guaranteed to be valid when the task was
  920. * in user space, so ...
  921. */
  922. ia64_mca_modify_comm(previous_current);
  923. goto no_mod;
  924. }
  925. if (r13 != sos->prev_IA64_KR_CURRENT) {
  926. msg = "inconsistent previous current and r13";
  927. goto no_mod;
  928. }
  929. if (!mca_recover_range(ms->pmsa_iip)) {
  930. if ((r12 - r13) >= KERNEL_STACK_SIZE) {
  931. msg = "inconsistent r12 and r13";
  932. goto no_mod;
  933. }
  934. if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
  935. msg = "inconsistent ar.bspstore and r13";
  936. goto no_mod;
  937. }
  938. va.p = old_bspstore;
  939. if (va.f.reg < 5) {
  940. msg = "old_bspstore is in the wrong region";
  941. goto no_mod;
  942. }
  943. if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
  944. msg = "inconsistent ar.bsp and r13";
  945. goto no_mod;
  946. }
  947. size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
  948. if (ar_bspstore + size > r12) {
  949. msg = "no room for blocked state";
  950. goto no_mod;
  951. }
  952. }
  953. ia64_mca_modify_comm(previous_current);
  954. /* Make the original task look blocked. First stack a struct pt_regs,
  955. * describing the state at the time of interrupt. mca_asm.S built a
  956. * partial pt_regs, copy it and fill in the blanks using minstate.
  957. */
  958. p = (char *)r12 - sizeof(*regs);
  959. old_regs = (struct pt_regs *)p;
  960. memcpy(old_regs, regs, sizeof(*regs));
  961. old_regs->loadrs = loadrs;
  962. old_unat = old_regs->ar_unat;
  963. finish_pt_regs(old_regs, sos, &old_unat);
  964. /* Next stack a struct switch_stack. mca_asm.S built a partial
  965. * switch_stack, copy it and fill in the blanks using pt_regs and
  966. * minstate.
  967. *
  968. * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
  969. * ar.pfs is set to 0.
  970. *
  971. * unwind.c::unw_unwind() does special processing for interrupt frames.
  972. * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
  973. * is clear then unw_unwind() does _not_ adjust bsp over pt_regs. Not
  974. * that this is documented, of course. Set PRED_NON_SYSCALL in the
  975. * switch_stack on the original stack so it will unwind correctly when
  976. * unwind.c reads pt_regs.
  977. *
  978. * thread.ksp is updated to point to the synthesized switch_stack.
  979. */
  980. p -= sizeof(struct switch_stack);
  981. old_sw = (struct switch_stack *)p;
  982. memcpy(old_sw, sw, sizeof(*sw));
  983. old_sw->caller_unat = old_unat;
  984. old_sw->ar_fpsr = old_regs->ar_fpsr;
  985. copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
  986. copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
  987. copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
  988. copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
  989. old_sw->b0 = (u64)ia64_leave_kernel;
  990. old_sw->b1 = ms->pmsa_br1;
  991. old_sw->ar_pfs = 0;
  992. old_sw->ar_unat = old_unat;
  993. old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
  994. previous_current->thread.ksp = (u64)p - 16;
  995. /* Finally copy the original stack's registers back to its RBS.
  996. * Registers from ar.bspstore through ar.bsp at the time of the event
  997. * are in the current RBS, copy them back to the original stack. The
  998. * copy must be done register by register because the original bspstore
  999. * and the current one have different alignments, so the saved RNAT
  1000. * data occurs at different places.
  1001. *
  1002. * mca_asm does cover, so the old_bsp already includes all registers at
  1003. * the time of MCA/INIT. It also does flushrs, so all registers before
  1004. * this function have been written to backing store on the MCA/INIT
  1005. * stack.
  1006. */
  1007. new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
  1008. old_rnat = regs->ar_rnat;
  1009. while (slots--) {
  1010. if (ia64_rse_is_rnat_slot(new_bspstore)) {
  1011. new_rnat = ia64_get_rnat(new_bspstore++);
  1012. }
  1013. if (ia64_rse_is_rnat_slot(old_bspstore)) {
  1014. *old_bspstore++ = old_rnat;
  1015. old_rnat = 0;
  1016. }
  1017. nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
  1018. old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
  1019. old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
  1020. *old_bspstore++ = *new_bspstore++;
  1021. }
  1022. old_sw->ar_bspstore = (unsigned long)old_bspstore;
  1023. old_sw->ar_rnat = old_rnat;
  1024. sos->prev_task = previous_current;
  1025. return previous_current;
  1026. no_mod:
  1027. mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
  1028. smp_processor_id(), type, msg);
  1029. old_unat = regs->ar_unat;
  1030. finish_pt_regs(regs, sos, &old_unat);
  1031. return previous_current;
  1032. }
  1033. /* The monarch/slave interaction is based on monarch_cpu and requires that all
  1034. * slaves have entered rendezvous before the monarch leaves. If any cpu has
  1035. * not entered rendezvous yet then wait a bit. The assumption is that any
  1036. * slave that has not rendezvoused after a reasonable time is never going to do
  1037. * so. In this context, slave includes cpus that respond to the MCA rendezvous
  1038. * interrupt, as well as cpus that receive the INIT slave event.
  1039. */
  1040. static void
  1041. ia64_wait_for_slaves(int monarch, const char *type)
  1042. {
  1043. int c, i , wait;
  1044. /*
  1045. * wait 5 seconds total for slaves (arbitrary)
  1046. */
  1047. for (i = 0; i < 5000; i++) {
  1048. wait = 0;
  1049. for_each_online_cpu(c) {
  1050. if (c == monarch)
  1051. continue;
  1052. if (ia64_mc_info.imi_rendez_checkin[c]
  1053. == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
  1054. udelay(1000); /* short wait */
  1055. wait = 1;
  1056. break;
  1057. }
  1058. }
  1059. if (!wait)
  1060. goto all_in;
  1061. }
  1062. /*
  1063. * Maybe slave(s) dead. Print buffered messages immediately.
  1064. */
  1065. ia64_mlogbuf_finish(0);
  1066. mprintk(KERN_INFO "OS %s slave did not rendezvous on cpu", type);
  1067. for_each_online_cpu(c) {
  1068. if (c == monarch)
  1069. continue;
  1070. if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
  1071. mprintk(" %d", c);
  1072. }
  1073. mprintk("\n");
  1074. return;
  1075. all_in:
  1076. mprintk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type);
  1077. return;
  1078. }
  1079. /* mca_insert_tr
  1080. *
  1081. * Switch rid when TR reload and needed!
  1082. * iord: 1: itr, 2: itr;
  1083. *
  1084. */
  1085. static void mca_insert_tr(u64 iord)
  1086. {
  1087. int i;
  1088. u64 old_rr;
  1089. struct ia64_tr_entry *p;
  1090. unsigned long psr;
  1091. int cpu = smp_processor_id();
  1092. if (!ia64_idtrs[cpu])
  1093. return;
  1094. psr = ia64_clear_ic();
  1095. for (i = IA64_TR_ALLOC_BASE; i < IA64_TR_ALLOC_MAX; i++) {
  1096. p = ia64_idtrs[cpu] + (iord - 1) * IA64_TR_ALLOC_MAX;
  1097. if (p->pte & 0x1) {
  1098. old_rr = ia64_get_rr(p->ifa);
  1099. if (old_rr != p->rr) {
  1100. ia64_set_rr(p->ifa, p->rr);
  1101. ia64_srlz_d();
  1102. }
  1103. ia64_ptr(iord, p->ifa, p->itir >> 2);
  1104. ia64_srlz_i();
  1105. if (iord & 0x1) {
  1106. ia64_itr(0x1, i, p->ifa, p->pte, p->itir >> 2);
  1107. ia64_srlz_i();
  1108. }
  1109. if (iord & 0x2) {
  1110. ia64_itr(0x2, i, p->ifa, p->pte, p->itir >> 2);
  1111. ia64_srlz_i();
  1112. }
  1113. if (old_rr != p->rr) {
  1114. ia64_set_rr(p->ifa, old_rr);
  1115. ia64_srlz_d();
  1116. }
  1117. }
  1118. }
  1119. ia64_set_psr(psr);
  1120. }
  1121. /*
  1122. * ia64_mca_handler
  1123. *
  1124. * This is uncorrectable machine check handler called from OS_MCA
  1125. * dispatch code which is in turn called from SAL_CHECK().
  1126. * This is the place where the core of OS MCA handling is done.
  1127. * Right now the logs are extracted and displayed in a well-defined
  1128. * format. This handler code is supposed to be run only on the
  1129. * monarch processor. Once the monarch is done with MCA handling
  1130. * further MCA logging is enabled by clearing logs.
  1131. * Monarch also has the duty of sending wakeup-IPIs to pull the
  1132. * slave processors out of rendezvous spinloop.
  1133. *
  1134. * If multiple processors call into OS_MCA, the first will become
  1135. * the monarch. Subsequent cpus will be recorded in the mca_cpu
  1136. * bitmask. After the first monarch has processed its MCA, it
  1137. * will wake up the next cpu in the mca_cpu bitmask and then go
  1138. * into the rendezvous loop. When all processors have serviced
  1139. * their MCA, the last monarch frees up the rest of the processors.
  1140. */
  1141. void
  1142. ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
  1143. struct ia64_sal_os_state *sos)
  1144. {
  1145. int recover, cpu = smp_processor_id();
  1146. struct task_struct *previous_current;
  1147. struct ia64_mca_notify_die nd =
  1148. { .sos = sos, .monarch_cpu = &monarch_cpu, .data = &recover };
  1149. static atomic_t mca_count;
  1150. static cpumask_t mca_cpu;
  1151. if (atomic_add_return(1, &mca_count) == 1) {
  1152. monarch_cpu = cpu;
  1153. sos->monarch = 1;
  1154. } else {
  1155. cpumask_set_cpu(cpu, &mca_cpu);
  1156. sos->monarch = 0;
  1157. }
  1158. mprintk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d "
  1159. "monarch=%ld\n", sos->proc_state_param, cpu, sos->monarch);
  1160. previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
  1161. NOTIFY_MCA(DIE_MCA_MONARCH_ENTER, regs, (long)&nd, 1);
  1162. ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA;
  1163. if (sos->monarch) {
  1164. ia64_wait_for_slaves(cpu, "MCA");
  1165. /* Wakeup all the processors which are spinning in the
  1166. * rendezvous loop. They will leave SAL, then spin in the OS
  1167. * with interrupts disabled until this monarch cpu leaves the
  1168. * MCA handler. That gets control back to the OS so we can
  1169. * backtrace the other cpus, backtrace when spinning in SAL
  1170. * does not work.
  1171. */
  1172. ia64_mca_wakeup_all();
  1173. } else {
  1174. while (cpumask_test_cpu(cpu, &mca_cpu))
  1175. cpu_relax(); /* spin until monarch wakes us */
  1176. }
  1177. NOTIFY_MCA(DIE_MCA_MONARCH_PROCESS, regs, (long)&nd, 1);
  1178. /* Get the MCA error record and log it */
  1179. ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
  1180. /* MCA error recovery */
  1181. recover = (ia64_mca_ucmc_extension
  1182. && ia64_mca_ucmc_extension(
  1183. IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
  1184. sos));
  1185. if (recover) {
  1186. sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
  1187. rh->severity = sal_log_severity_corrected;
  1188. ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
  1189. sos->os_status = IA64_MCA_CORRECTED;
  1190. } else {
  1191. /* Dump buffered message to console */
  1192. ia64_mlogbuf_finish(1);
  1193. }
  1194. if (__this_cpu_read(ia64_mca_tr_reload)) {
  1195. mca_insert_tr(0x1); /*Reload dynamic itrs*/
  1196. mca_insert_tr(0x2); /*Reload dynamic itrs*/
  1197. }
  1198. NOTIFY_MCA(DIE_MCA_MONARCH_LEAVE, regs, (long)&nd, 1);
  1199. if (atomic_dec_return(&mca_count) > 0) {
  1200. int i;
  1201. /* wake up the next monarch cpu,
  1202. * and put this cpu in the rendez loop.
  1203. */
  1204. for_each_online_cpu(i) {
  1205. if (cpumask_test_cpu(i, &mca_cpu)) {
  1206. monarch_cpu = i;
  1207. cpumask_clear_cpu(i, &mca_cpu); /* wake next cpu */
  1208. while (monarch_cpu != -1)
  1209. cpu_relax(); /* spin until last cpu leaves */
  1210. ia64_set_curr_task(cpu, previous_current);
  1211. ia64_mc_info.imi_rendez_checkin[cpu]
  1212. = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
  1213. return;
  1214. }
  1215. }
  1216. }
  1217. ia64_set_curr_task(cpu, previous_current);
  1218. ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
  1219. monarch_cpu = -1; /* This frees the slaves and previous monarchs */
  1220. }
  1221. static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd);
  1222. static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd);
  1223. /*
  1224. * ia64_mca_cmc_int_handler
  1225. *
  1226. * This is corrected machine check interrupt handler.
  1227. * Right now the logs are extracted and displayed in a well-defined
  1228. * format.
  1229. *
  1230. * Inputs
  1231. * interrupt number
  1232. * client data arg ptr
  1233. *
  1234. * Outputs
  1235. * None
  1236. */
  1237. static irqreturn_t
  1238. ia64_mca_cmc_int_handler(int cmc_irq, void *arg)
  1239. {
  1240. static unsigned long cmc_history[CMC_HISTORY_LENGTH];
  1241. static int index;
  1242. static DEFINE_SPINLOCK(cmc_history_lock);
  1243. IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
  1244. __func__, cmc_irq, smp_processor_id());
  1245. /* SAL spec states this should run w/ interrupts enabled */
  1246. local_irq_enable();
  1247. spin_lock(&cmc_history_lock);
  1248. if (!cmc_polling_enabled) {
  1249. int i, count = 1; /* we know 1 happened now */
  1250. unsigned long now = jiffies;
  1251. for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
  1252. if (now - cmc_history[i] <= HZ)
  1253. count++;
  1254. }
  1255. IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
  1256. if (count >= CMC_HISTORY_LENGTH) {
  1257. cmc_polling_enabled = 1;
  1258. spin_unlock(&cmc_history_lock);
  1259. /* If we're being hit with CMC interrupts, we won't
  1260. * ever execute the schedule_work() below. Need to
  1261. * disable CMC interrupts on this processor now.
  1262. */
  1263. ia64_mca_cmc_vector_disable(NULL);
  1264. schedule_work(&cmc_disable_work);
  1265. /*
  1266. * Corrected errors will still be corrected, but
  1267. * make sure there's a log somewhere that indicates
  1268. * something is generating more than we can handle.
  1269. */
  1270. printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
  1271. mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
  1272. /* lock already released, get out now */
  1273. goto out;
  1274. } else {
  1275. cmc_history[index++] = now;
  1276. if (index == CMC_HISTORY_LENGTH)
  1277. index = 0;
  1278. }
  1279. }
  1280. spin_unlock(&cmc_history_lock);
  1281. out:
  1282. /* Get the CMC error record and log it */
  1283. ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
  1284. local_irq_disable();
  1285. return IRQ_HANDLED;
  1286. }
  1287. /*
  1288. * ia64_mca_cmc_int_caller
  1289. *
  1290. * Triggered by sw interrupt from CMC polling routine. Calls
  1291. * real interrupt handler and either triggers a sw interrupt
  1292. * on the next cpu or does cleanup at the end.
  1293. *
  1294. * Inputs
  1295. * interrupt number
  1296. * client data arg ptr
  1297. * Outputs
  1298. * handled
  1299. */
  1300. static irqreturn_t
  1301. ia64_mca_cmc_int_caller(int cmc_irq, void *arg)
  1302. {
  1303. static int start_count = -1;
  1304. unsigned int cpuid;
  1305. cpuid = smp_processor_id();
  1306. /* If first cpu, update count */
  1307. if (start_count == -1)
  1308. start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
  1309. ia64_mca_cmc_int_handler(cmc_irq, arg);
  1310. cpuid = cpumask_next(cpuid+1, cpu_online_mask);
  1311. if (cpuid < nr_cpu_ids) {
  1312. platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
  1313. } else {
  1314. /* If no log record, switch out of polling mode */
  1315. if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
  1316. printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
  1317. schedule_work(&cmc_enable_work);
  1318. cmc_polling_enabled = 0;
  1319. } else {
  1320. mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
  1321. }
  1322. start_count = -1;
  1323. }
  1324. return IRQ_HANDLED;
  1325. }
  1326. /*
  1327. * ia64_mca_cmc_poll
  1328. *
  1329. * Poll for Corrected Machine Checks (CMCs)
  1330. *
  1331. * Inputs : dummy(unused)
  1332. * Outputs : None
  1333. *
  1334. */
  1335. static void
  1336. ia64_mca_cmc_poll (struct timer_list *unused)
  1337. {
  1338. /* Trigger a CMC interrupt cascade */
  1339. platform_send_ipi(cpumask_first(cpu_online_mask), IA64_CMCP_VECTOR,
  1340. IA64_IPI_DM_INT, 0);
  1341. }
  1342. /*
  1343. * ia64_mca_cpe_int_caller
  1344. *
  1345. * Triggered by sw interrupt from CPE polling routine. Calls
  1346. * real interrupt handler and either triggers a sw interrupt
  1347. * on the next cpu or does cleanup at the end.
  1348. *
  1349. * Inputs
  1350. * interrupt number
  1351. * client data arg ptr
  1352. * Outputs
  1353. * handled
  1354. */
  1355. #ifdef CONFIG_ACPI
  1356. static irqreturn_t
  1357. ia64_mca_cpe_int_caller(int cpe_irq, void *arg)
  1358. {
  1359. static int start_count = -1;
  1360. static int poll_time = MIN_CPE_POLL_INTERVAL;
  1361. unsigned int cpuid;
  1362. cpuid = smp_processor_id();
  1363. /* If first cpu, update count */
  1364. if (start_count == -1)
  1365. start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
  1366. ia64_mca_cpe_int_handler(cpe_irq, arg);
  1367. cpuid = cpumask_next(cpuid+1, cpu_online_mask);
  1368. if (cpuid < NR_CPUS) {
  1369. platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
  1370. } else {
  1371. /*
  1372. * If a log was recorded, increase our polling frequency,
  1373. * otherwise, backoff or return to interrupt mode.
  1374. */
  1375. if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
  1376. poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
  1377. } else if (cpe_vector < 0) {
  1378. poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
  1379. } else {
  1380. poll_time = MIN_CPE_POLL_INTERVAL;
  1381. printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
  1382. enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
  1383. cpe_poll_enabled = 0;
  1384. }
  1385. if (cpe_poll_enabled)
  1386. mod_timer(&cpe_poll_timer, jiffies + poll_time);
  1387. start_count = -1;
  1388. }
  1389. return IRQ_HANDLED;
  1390. }
  1391. /*
  1392. * ia64_mca_cpe_poll
  1393. *
  1394. * Poll for Corrected Platform Errors (CPEs), trigger interrupt
  1395. * on first cpu, from there it will trickle through all the cpus.
  1396. *
  1397. * Inputs : dummy(unused)
  1398. * Outputs : None
  1399. *
  1400. */
  1401. static void
  1402. ia64_mca_cpe_poll (struct timer_list *unused)
  1403. {
  1404. /* Trigger a CPE interrupt cascade */
  1405. platform_send_ipi(cpumask_first(cpu_online_mask), IA64_CPEP_VECTOR,
  1406. IA64_IPI_DM_INT, 0);
  1407. }
  1408. #endif /* CONFIG_ACPI */
  1409. static int
  1410. default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
  1411. {
  1412. int c;
  1413. struct task_struct *g, *t;
  1414. if (val != DIE_INIT_MONARCH_PROCESS)
  1415. return NOTIFY_DONE;
  1416. #ifdef CONFIG_KEXEC
  1417. if (atomic_read(&kdump_in_progress))
  1418. return NOTIFY_DONE;
  1419. #endif
  1420. /*
  1421. * FIXME: mlogbuf will brim over with INIT stack dumps.
  1422. * To enable show_stack from INIT, we use oops_in_progress which should
  1423. * be used in real oops. This would cause something wrong after INIT.
  1424. */
  1425. BREAK_LOGLEVEL(console_loglevel);
  1426. ia64_mlogbuf_dump_from_init();
  1427. printk(KERN_ERR "Processes interrupted by INIT -");
  1428. for_each_online_cpu(c) {
  1429. struct ia64_sal_os_state *s;
  1430. t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
  1431. s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
  1432. g = s->prev_task;
  1433. if (g) {
  1434. if (g->pid)
  1435. printk(" %d", g->pid);
  1436. else
  1437. printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
  1438. }
  1439. }
  1440. printk("\n\n");
  1441. if (read_trylock(&tasklist_lock)) {
  1442. do_each_thread (g, t) {
  1443. printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
  1444. show_stack(t, NULL);
  1445. } while_each_thread (g, t);
  1446. read_unlock(&tasklist_lock);
  1447. }
  1448. /* FIXME: This will not restore zapped printk locks. */
  1449. RESTORE_LOGLEVEL(console_loglevel);
  1450. return NOTIFY_DONE;
  1451. }
  1452. /*
  1453. * C portion of the OS INIT handler
  1454. *
  1455. * Called from ia64_os_init_dispatch
  1456. *
  1457. * Inputs: pointer to pt_regs where processor info was saved. SAL/OS state for
  1458. * this event. This code is used for both monarch and slave INIT events, see
  1459. * sos->monarch.
  1460. *
  1461. * All INIT events switch to the INIT stack and change the previous process to
  1462. * blocked status. If one of the INIT events is the monarch then we are
  1463. * probably processing the nmi button/command. Use the monarch cpu to dump all
  1464. * the processes. The slave INIT events all spin until the monarch cpu
  1465. * returns. We can also get INIT slave events for MCA, in which case the MCA
  1466. * process is the monarch.
  1467. */
  1468. void
  1469. ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
  1470. struct ia64_sal_os_state *sos)
  1471. {
  1472. static atomic_t slaves;
  1473. static atomic_t monarchs;
  1474. struct task_struct *previous_current;
  1475. int cpu = smp_processor_id();
  1476. struct ia64_mca_notify_die nd =
  1477. { .sos = sos, .monarch_cpu = &monarch_cpu };
  1478. NOTIFY_INIT(DIE_INIT_ENTER, regs, (long)&nd, 0);
  1479. mprintk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
  1480. sos->proc_state_param, cpu, sos->monarch);
  1481. salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
  1482. previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
  1483. sos->os_status = IA64_INIT_RESUME;
  1484. /* FIXME: Workaround for broken proms that drive all INIT events as
  1485. * slaves. The last slave that enters is promoted to be a monarch.
  1486. * Remove this code in September 2006, that gives platforms a year to
  1487. * fix their proms and get their customers updated.
  1488. */
  1489. if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
  1490. mprintk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
  1491. __func__, cpu);
  1492. atomic_dec(&slaves);
  1493. sos->monarch = 1;
  1494. }
  1495. /* FIXME: Workaround for broken proms that drive all INIT events as
  1496. * monarchs. Second and subsequent monarchs are demoted to slaves.
  1497. * Remove this code in September 2006, that gives platforms a year to
  1498. * fix their proms and get their customers updated.
  1499. */
  1500. if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
  1501. mprintk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
  1502. __func__, cpu);
  1503. atomic_dec(&monarchs);
  1504. sos->monarch = 0;
  1505. }
  1506. if (!sos->monarch) {
  1507. ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
  1508. #ifdef CONFIG_KEXEC
  1509. while (monarch_cpu == -1 && !atomic_read(&kdump_in_progress))
  1510. udelay(1000);
  1511. #else
  1512. while (monarch_cpu == -1)
  1513. cpu_relax(); /* spin until monarch enters */
  1514. #endif
  1515. NOTIFY_INIT(DIE_INIT_SLAVE_ENTER, regs, (long)&nd, 1);
  1516. NOTIFY_INIT(DIE_INIT_SLAVE_PROCESS, regs, (long)&nd, 1);
  1517. #ifdef CONFIG_KEXEC
  1518. while (monarch_cpu != -1 && !atomic_read(&kdump_in_progress))
  1519. udelay(1000);
  1520. #else
  1521. while (monarch_cpu != -1)
  1522. cpu_relax(); /* spin until monarch leaves */
  1523. #endif
  1524. NOTIFY_INIT(DIE_INIT_SLAVE_LEAVE, regs, (long)&nd, 1);
  1525. mprintk("Slave on cpu %d returning to normal service.\n", cpu);
  1526. ia64_set_curr_task(cpu, previous_current);
  1527. ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
  1528. atomic_dec(&slaves);
  1529. return;
  1530. }
  1531. monarch_cpu = cpu;
  1532. NOTIFY_INIT(DIE_INIT_MONARCH_ENTER, regs, (long)&nd, 1);
  1533. /*
  1534. * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be
  1535. * generated via the BMC's command-line interface, but since the console is on the
  1536. * same serial line, the user will need some time to switch out of the BMC before
  1537. * the dump begins.
  1538. */
  1539. mprintk("Delaying for 5 seconds...\n");
  1540. udelay(5*1000000);
  1541. ia64_wait_for_slaves(cpu, "INIT");
  1542. /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
  1543. * to default_monarch_init_process() above and just print all the
  1544. * tasks.
  1545. */
  1546. NOTIFY_INIT(DIE_INIT_MONARCH_PROCESS, regs, (long)&nd, 1);
  1547. NOTIFY_INIT(DIE_INIT_MONARCH_LEAVE, regs, (long)&nd, 1);
  1548. mprintk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu);
  1549. atomic_dec(&monarchs);
  1550. ia64_set_curr_task(cpu, previous_current);
  1551. monarch_cpu = -1;
  1552. return;
  1553. }
  1554. static int __init
  1555. ia64_mca_disable_cpe_polling(char *str)
  1556. {
  1557. cpe_poll_enabled = 0;
  1558. return 1;
  1559. }
  1560. __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
  1561. static struct irqaction cmci_irqaction = {
  1562. .handler = ia64_mca_cmc_int_handler,
  1563. .name = "cmc_hndlr"
  1564. };
  1565. static struct irqaction cmcp_irqaction = {
  1566. .handler = ia64_mca_cmc_int_caller,
  1567. .name = "cmc_poll"
  1568. };
  1569. static struct irqaction mca_rdzv_irqaction = {
  1570. .handler = ia64_mca_rendez_int_handler,
  1571. .name = "mca_rdzv"
  1572. };
  1573. static struct irqaction mca_wkup_irqaction = {
  1574. .handler = ia64_mca_wakeup_int_handler,
  1575. .name = "mca_wkup"
  1576. };
  1577. #ifdef CONFIG_ACPI
  1578. static struct irqaction mca_cpe_irqaction = {
  1579. .handler = ia64_mca_cpe_int_handler,
  1580. .name = "cpe_hndlr"
  1581. };
  1582. static struct irqaction mca_cpep_irqaction = {
  1583. .handler = ia64_mca_cpe_int_caller,
  1584. .name = "cpe_poll"
  1585. };
  1586. #endif /* CONFIG_ACPI */
  1587. /* Minimal format of the MCA/INIT stacks. The pseudo processes that run on
  1588. * these stacks can never sleep, they cannot return from the kernel to user
  1589. * space, they do not appear in a normal ps listing. So there is no need to
  1590. * format most of the fields.
  1591. */
  1592. static void
  1593. format_mca_init_stack(void *mca_data, unsigned long offset,
  1594. const char *type, int cpu)
  1595. {
  1596. struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
  1597. struct thread_info *ti;
  1598. memset(p, 0, KERNEL_STACK_SIZE);
  1599. ti = task_thread_info(p);
  1600. ti->flags = _TIF_MCA_INIT;
  1601. ti->preempt_count = 1;
  1602. ti->task = p;
  1603. ti->cpu = cpu;
  1604. p->stack = ti;
  1605. p->state = TASK_UNINTERRUPTIBLE;
  1606. cpumask_set_cpu(cpu, &p->cpus_allowed);
  1607. INIT_LIST_HEAD(&p->tasks);
  1608. p->parent = p->real_parent = p->group_leader = p;
  1609. INIT_LIST_HEAD(&p->children);
  1610. INIT_LIST_HEAD(&p->sibling);
  1611. strncpy(p->comm, type, sizeof(p->comm)-1);
  1612. }
  1613. /* Caller prevents this from being called after init */
  1614. static void * __ref mca_bootmem(void)
  1615. {
  1616. return __alloc_bootmem(sizeof(struct ia64_mca_cpu),
  1617. KERNEL_STACK_SIZE, 0);
  1618. }
  1619. /* Do per-CPU MCA-related initialization. */
  1620. void
  1621. ia64_mca_cpu_init(void *cpu_data)
  1622. {
  1623. void *pal_vaddr;
  1624. void *data;
  1625. long sz = sizeof(struct ia64_mca_cpu);
  1626. int cpu = smp_processor_id();
  1627. static int first_time = 1;
  1628. /*
  1629. * Structure will already be allocated if cpu has been online,
  1630. * then offlined.
  1631. */
  1632. if (__per_cpu_mca[cpu]) {
  1633. data = __va(__per_cpu_mca[cpu]);
  1634. } else {
  1635. if (first_time) {
  1636. data = mca_bootmem();
  1637. first_time = 0;
  1638. } else
  1639. data = (void *)__get_free_pages(GFP_ATOMIC,
  1640. get_order(sz));
  1641. if (!data)
  1642. panic("Could not allocate MCA memory for cpu %d\n",
  1643. cpu);
  1644. }
  1645. format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, mca_stack),
  1646. "MCA", cpu);
  1647. format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, init_stack),
  1648. "INIT", cpu);
  1649. __this_cpu_write(ia64_mca_data, (__per_cpu_mca[cpu] = __pa(data)));
  1650. /*
  1651. * Stash away a copy of the PTE needed to map the per-CPU page.
  1652. * We may need it during MCA recovery.
  1653. */
  1654. __this_cpu_write(ia64_mca_per_cpu_pte,
  1655. pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL)));
  1656. /*
  1657. * Also, stash away a copy of the PAL address and the PTE
  1658. * needed to map it.
  1659. */
  1660. pal_vaddr = efi_get_pal_addr();
  1661. if (!pal_vaddr)
  1662. return;
  1663. __this_cpu_write(ia64_mca_pal_base,
  1664. GRANULEROUNDDOWN((unsigned long) pal_vaddr));
  1665. __this_cpu_write(ia64_mca_pal_pte, pte_val(mk_pte_phys(__pa(pal_vaddr),
  1666. PAGE_KERNEL)));
  1667. }
  1668. static int ia64_mca_cpu_online(unsigned int cpu)
  1669. {
  1670. unsigned long flags;
  1671. local_irq_save(flags);
  1672. if (!cmc_polling_enabled)
  1673. ia64_mca_cmc_vector_enable(NULL);
  1674. local_irq_restore(flags);
  1675. return 0;
  1676. }
  1677. /*
  1678. * ia64_mca_init
  1679. *
  1680. * Do all the system level mca specific initialization.
  1681. *
  1682. * 1. Register spinloop and wakeup request interrupt vectors
  1683. *
  1684. * 2. Register OS_MCA handler entry point
  1685. *
  1686. * 3. Register OS_INIT handler entry point
  1687. *
  1688. * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
  1689. *
  1690. * Note that this initialization is done very early before some kernel
  1691. * services are available.
  1692. *
  1693. * Inputs : None
  1694. *
  1695. * Outputs : None
  1696. */
  1697. void __init
  1698. ia64_mca_init(void)
  1699. {
  1700. ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
  1701. ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
  1702. ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
  1703. int i;
  1704. long rc;
  1705. struct ia64_sal_retval isrv;
  1706. unsigned long timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */
  1707. static struct notifier_block default_init_monarch_nb = {
  1708. .notifier_call = default_monarch_init_process,
  1709. .priority = 0/* we need to notified last */
  1710. };
  1711. IA64_MCA_DEBUG("%s: begin\n", __func__);
  1712. /* Clear the Rendez checkin flag for all cpus */
  1713. for(i = 0 ; i < NR_CPUS; i++)
  1714. ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
  1715. /*
  1716. * Register the rendezvous spinloop and wakeup mechanism with SAL
  1717. */
  1718. /* Register the rendezvous interrupt vector with SAL */
  1719. while (1) {
  1720. isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
  1721. SAL_MC_PARAM_MECHANISM_INT,
  1722. IA64_MCA_RENDEZ_VECTOR,
  1723. timeout,
  1724. SAL_MC_PARAM_RZ_ALWAYS);
  1725. rc = isrv.status;
  1726. if (rc == 0)
  1727. break;
  1728. if (rc == -2) {
  1729. printk(KERN_INFO "Increasing MCA rendezvous timeout from "
  1730. "%ld to %ld milliseconds\n", timeout, isrv.v0);
  1731. timeout = isrv.v0;
  1732. NOTIFY_MCA(DIE_MCA_NEW_TIMEOUT, NULL, timeout, 0);
  1733. continue;
  1734. }
  1735. printk(KERN_ERR "Failed to register rendezvous interrupt "
  1736. "with SAL (status %ld)\n", rc);
  1737. return;
  1738. }
  1739. /* Register the wakeup interrupt vector with SAL */
  1740. isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
  1741. SAL_MC_PARAM_MECHANISM_INT,
  1742. IA64_MCA_WAKEUP_VECTOR,
  1743. 0, 0);
  1744. rc = isrv.status;
  1745. if (rc) {
  1746. printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
  1747. "(status %ld)\n", rc);
  1748. return;
  1749. }
  1750. IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __func__);
  1751. ia64_mc_info.imi_mca_handler = ia64_tpa(mca_hldlr_ptr->fp);
  1752. /*
  1753. * XXX - disable SAL checksum by setting size to 0; should be
  1754. * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
  1755. */
  1756. ia64_mc_info.imi_mca_handler_size = 0;
  1757. /* Register the os mca handler with SAL */
  1758. if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
  1759. ia64_mc_info.imi_mca_handler,
  1760. ia64_tpa(mca_hldlr_ptr->gp),
  1761. ia64_mc_info.imi_mca_handler_size,
  1762. 0, 0, 0)))
  1763. {
  1764. printk(KERN_ERR "Failed to register OS MCA handler with SAL "
  1765. "(status %ld)\n", rc);
  1766. return;
  1767. }
  1768. IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __func__,
  1769. ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
  1770. /*
  1771. * XXX - disable SAL checksum by setting size to 0, should be
  1772. * size of the actual init handler in mca_asm.S.
  1773. */
  1774. ia64_mc_info.imi_monarch_init_handler = ia64_tpa(init_hldlr_ptr_monarch->fp);
  1775. ia64_mc_info.imi_monarch_init_handler_size = 0;
  1776. ia64_mc_info.imi_slave_init_handler = ia64_tpa(init_hldlr_ptr_slave->fp);
  1777. ia64_mc_info.imi_slave_init_handler_size = 0;
  1778. IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __func__,
  1779. ia64_mc_info.imi_monarch_init_handler);
  1780. /* Register the os init handler with SAL */
  1781. if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
  1782. ia64_mc_info.imi_monarch_init_handler,
  1783. ia64_tpa(ia64_getreg(_IA64_REG_GP)),
  1784. ia64_mc_info.imi_monarch_init_handler_size,
  1785. ia64_mc_info.imi_slave_init_handler,
  1786. ia64_tpa(ia64_getreg(_IA64_REG_GP)),
  1787. ia64_mc_info.imi_slave_init_handler_size)))
  1788. {
  1789. printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
  1790. "(status %ld)\n", rc);
  1791. return;
  1792. }
  1793. if (register_die_notifier(&default_init_monarch_nb)) {
  1794. printk(KERN_ERR "Failed to register default monarch INIT process\n");
  1795. return;
  1796. }
  1797. IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __func__);
  1798. /* Initialize the areas set aside by the OS to buffer the
  1799. * platform/processor error states for MCA/INIT/CMC
  1800. * handling.
  1801. */
  1802. ia64_log_init(SAL_INFO_TYPE_MCA);
  1803. ia64_log_init(SAL_INFO_TYPE_INIT);
  1804. ia64_log_init(SAL_INFO_TYPE_CMC);
  1805. ia64_log_init(SAL_INFO_TYPE_CPE);
  1806. mca_init = 1;
  1807. printk(KERN_INFO "MCA related initialization done\n");
  1808. }
  1809. /*
  1810. * These pieces cannot be done in ia64_mca_init() because it is called before
  1811. * early_irq_init() which would wipe out our percpu irq registrations. But we
  1812. * cannot leave them until ia64_mca_late_init() because by then all the other
  1813. * processors have been brought online and have set their own CMC vectors to
  1814. * point at a non-existant action. Called from arch_early_irq_init().
  1815. */
  1816. void __init ia64_mca_irq_init(void)
  1817. {
  1818. /*
  1819. * Configure the CMCI/P vector and handler. Interrupts for CMC are
  1820. * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
  1821. */
  1822. register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
  1823. register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
  1824. ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
  1825. /* Setup the MCA rendezvous interrupt vector */
  1826. register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
  1827. /* Setup the MCA wakeup interrupt vector */
  1828. register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
  1829. #ifdef CONFIG_ACPI
  1830. /* Setup the CPEI/P handler */
  1831. register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
  1832. #endif
  1833. }
  1834. /*
  1835. * ia64_mca_late_init
  1836. *
  1837. * Opportunity to setup things that require initialization later
  1838. * than ia64_mca_init. Setup a timer to poll for CPEs if the
  1839. * platform doesn't support an interrupt driven mechanism.
  1840. *
  1841. * Inputs : None
  1842. * Outputs : Status
  1843. */
  1844. static int __init
  1845. ia64_mca_late_init(void)
  1846. {
  1847. if (!mca_init)
  1848. return 0;
  1849. /* Setup the CMCI/P vector and handler */
  1850. timer_setup(&cmc_poll_timer, ia64_mca_cmc_poll, 0);
  1851. /* Unmask/enable the vector */
  1852. cmc_polling_enabled = 0;
  1853. cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "ia64/mca:online",
  1854. ia64_mca_cpu_online, NULL);
  1855. IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __func__);
  1856. #ifdef CONFIG_ACPI
  1857. /* Setup the CPEI/P vector and handler */
  1858. cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
  1859. timer_setup(&cpe_poll_timer, ia64_mca_cpe_poll, 0);
  1860. {
  1861. unsigned int irq;
  1862. if (cpe_vector >= 0) {
  1863. /* If platform supports CPEI, enable the irq. */
  1864. irq = local_vector_to_irq(cpe_vector);
  1865. if (irq > 0) {
  1866. cpe_poll_enabled = 0;
  1867. irq_set_status_flags(irq, IRQ_PER_CPU);
  1868. setup_irq(irq, &mca_cpe_irqaction);
  1869. ia64_cpe_irq = irq;
  1870. ia64_mca_register_cpev(cpe_vector);
  1871. IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n",
  1872. __func__);
  1873. return 0;
  1874. }
  1875. printk(KERN_ERR "%s: Failed to find irq for CPE "
  1876. "interrupt handler, vector %d\n",
  1877. __func__, cpe_vector);
  1878. }
  1879. /* If platform doesn't support CPEI, get the timer going. */
  1880. if (cpe_poll_enabled) {
  1881. ia64_mca_cpe_poll(0UL);
  1882. IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __func__);
  1883. }
  1884. }
  1885. #endif
  1886. return 0;
  1887. }
  1888. device_initcall(ia64_mca_late_init);