opal-irqchip.c 8.0 KB

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  1. /*
  2. * This file implements an irqchip for OPAL events. Whenever there is
  3. * an interrupt that is handled by OPAL we get passed a list of events
  4. * that Linux needs to do something about. These basically look like
  5. * interrupts to Linux so we implement an irqchip to handle them.
  6. *
  7. * Copyright Alistair Popple, IBM Corporation 2014.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/bitops.h>
  15. #include <linux/irq.h>
  16. #include <linux/irqchip.h>
  17. #include <linux/irqdomain.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/kthread.h>
  23. #include <linux/delay.h>
  24. #include <linux/slab.h>
  25. #include <linux/of_irq.h>
  26. #include <asm/machdep.h>
  27. #include <asm/opal.h>
  28. #include "powernv.h"
  29. /* Maximum number of events supported by OPAL firmware */
  30. #define MAX_NUM_EVENTS 64
  31. struct opal_event_irqchip {
  32. struct irq_chip irqchip;
  33. struct irq_domain *domain;
  34. unsigned long mask;
  35. };
  36. static struct opal_event_irqchip opal_event_irqchip;
  37. static u64 last_outstanding_events;
  38. static int opal_irq_count;
  39. static struct resource *opal_irqs;
  40. void opal_handle_events(void)
  41. {
  42. __be64 events = 0;
  43. u64 e;
  44. e = READ_ONCE(last_outstanding_events) & opal_event_irqchip.mask;
  45. again:
  46. while (e) {
  47. int virq, hwirq;
  48. hwirq = fls64(e) - 1;
  49. e &= ~BIT_ULL(hwirq);
  50. local_irq_disable();
  51. virq = irq_find_mapping(opal_event_irqchip.domain, hwirq);
  52. if (virq) {
  53. irq_enter();
  54. generic_handle_irq(virq);
  55. irq_exit();
  56. }
  57. local_irq_enable();
  58. cond_resched();
  59. }
  60. last_outstanding_events = 0;
  61. if (opal_poll_events(&events) != OPAL_SUCCESS)
  62. return;
  63. e = be64_to_cpu(events) & opal_event_irqchip.mask;
  64. if (e)
  65. goto again;
  66. }
  67. bool opal_have_pending_events(void)
  68. {
  69. if (last_outstanding_events & opal_event_irqchip.mask)
  70. return true;
  71. return false;
  72. }
  73. static void opal_event_mask(struct irq_data *d)
  74. {
  75. clear_bit(d->hwirq, &opal_event_irqchip.mask);
  76. }
  77. static void opal_event_unmask(struct irq_data *d)
  78. {
  79. set_bit(d->hwirq, &opal_event_irqchip.mask);
  80. if (opal_have_pending_events())
  81. opal_wake_poller();
  82. }
  83. static int opal_event_set_type(struct irq_data *d, unsigned int flow_type)
  84. {
  85. /*
  86. * For now we only support level triggered events. The irq
  87. * handler will be called continuously until the event has
  88. * been cleared in OPAL.
  89. */
  90. if (flow_type != IRQ_TYPE_LEVEL_HIGH)
  91. return -EINVAL;
  92. return 0;
  93. }
  94. static struct opal_event_irqchip opal_event_irqchip = {
  95. .irqchip = {
  96. .name = "OPAL EVT",
  97. .irq_mask = opal_event_mask,
  98. .irq_unmask = opal_event_unmask,
  99. .irq_set_type = opal_event_set_type,
  100. },
  101. .mask = 0,
  102. };
  103. static int opal_event_map(struct irq_domain *d, unsigned int irq,
  104. irq_hw_number_t hwirq)
  105. {
  106. irq_set_chip_data(irq, &opal_event_irqchip);
  107. irq_set_chip_and_handler(irq, &opal_event_irqchip.irqchip,
  108. handle_level_irq);
  109. return 0;
  110. }
  111. static irqreturn_t opal_interrupt(int irq, void *data)
  112. {
  113. __be64 events;
  114. opal_handle_interrupt(virq_to_hw(irq), &events);
  115. last_outstanding_events = be64_to_cpu(events);
  116. if (opal_have_pending_events())
  117. opal_wake_poller();
  118. return IRQ_HANDLED;
  119. }
  120. static int opal_event_match(struct irq_domain *h, struct device_node *node,
  121. enum irq_domain_bus_token bus_token)
  122. {
  123. return irq_domain_get_of_node(h) == node;
  124. }
  125. static int opal_event_xlate(struct irq_domain *h, struct device_node *np,
  126. const u32 *intspec, unsigned int intsize,
  127. irq_hw_number_t *out_hwirq, unsigned int *out_flags)
  128. {
  129. *out_hwirq = intspec[0];
  130. *out_flags = IRQ_TYPE_LEVEL_HIGH;
  131. return 0;
  132. }
  133. static const struct irq_domain_ops opal_event_domain_ops = {
  134. .match = opal_event_match,
  135. .map = opal_event_map,
  136. .xlate = opal_event_xlate,
  137. };
  138. void opal_event_shutdown(void)
  139. {
  140. unsigned int i;
  141. /* First free interrupts, which will also mask them */
  142. for (i = 0; i < opal_irq_count; i++) {
  143. if (!opal_irqs || !opal_irqs[i].start)
  144. continue;
  145. if (in_interrupt() || irqs_disabled())
  146. disable_irq_nosync(opal_irqs[i].start);
  147. else
  148. free_irq(opal_irqs[i].start, NULL);
  149. opal_irqs[i].start = 0;
  150. }
  151. }
  152. int __init opal_event_init(void)
  153. {
  154. struct device_node *dn, *opal_node;
  155. bool old_style = false;
  156. int i, rc = 0;
  157. opal_node = of_find_node_by_path("/ibm,opal");
  158. if (!opal_node) {
  159. pr_warn("opal: Node not found\n");
  160. return -ENODEV;
  161. }
  162. /* If dn is NULL it means the domain won't be linked to a DT
  163. * node so therefore irq_of_parse_and_map(...) wont work. But
  164. * that shouldn't be problem because if we're running a
  165. * version of skiboot that doesn't have the dn then the
  166. * devices won't have the correct properties and will have to
  167. * fall back to the legacy method (opal_event_request(...))
  168. * anyway. */
  169. dn = of_find_compatible_node(NULL, NULL, "ibm,opal-event");
  170. opal_event_irqchip.domain = irq_domain_add_linear(dn, MAX_NUM_EVENTS,
  171. &opal_event_domain_ops, &opal_event_irqchip);
  172. of_node_put(dn);
  173. if (!opal_event_irqchip.domain) {
  174. pr_warn("opal: Unable to create irq domain\n");
  175. rc = -ENOMEM;
  176. goto out;
  177. }
  178. /* Look for new-style (standard) "interrupts" property */
  179. opal_irq_count = of_irq_count(opal_node);
  180. /* Absent ? Look for the old one */
  181. if (opal_irq_count < 1) {
  182. /* Get opal-interrupts property and names if present */
  183. rc = of_property_count_u32_elems(opal_node, "opal-interrupts");
  184. if (rc > 0)
  185. opal_irq_count = rc;
  186. old_style = true;
  187. }
  188. /* No interrupts ? Bail out */
  189. if (!opal_irq_count)
  190. goto out;
  191. pr_debug("OPAL: Found %d interrupts reserved for OPAL using %s scheme\n",
  192. opal_irq_count, old_style ? "old" : "new");
  193. /* Allocate an IRQ resources array */
  194. opal_irqs = kcalloc(opal_irq_count, sizeof(struct resource), GFP_KERNEL);
  195. if (WARN_ON(!opal_irqs)) {
  196. rc = -ENOMEM;
  197. goto out;
  198. }
  199. /* Build the resources array */
  200. if (old_style) {
  201. /* Old style "opal-interrupts" property */
  202. for (i = 0; i < opal_irq_count; i++) {
  203. struct resource *r = &opal_irqs[i];
  204. const char *name = NULL;
  205. u32 hw_irq;
  206. int virq;
  207. rc = of_property_read_u32_index(opal_node, "opal-interrupts",
  208. i, &hw_irq);
  209. if (WARN_ON(rc < 0)) {
  210. opal_irq_count = i;
  211. break;
  212. }
  213. of_property_read_string_index(opal_node, "opal-interrupts-names",
  214. i, &name);
  215. virq = irq_create_mapping(NULL, hw_irq);
  216. if (!virq) {
  217. pr_warn("Failed to map OPAL irq 0x%x\n", hw_irq);
  218. continue;
  219. }
  220. r->start = r->end = virq;
  221. r->flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW;
  222. r->name = name;
  223. }
  224. } else {
  225. /* new style standard "interrupts" property */
  226. rc = of_irq_to_resource_table(opal_node, opal_irqs, opal_irq_count);
  227. if (WARN_ON(rc < 0)) {
  228. opal_irq_count = 0;
  229. kfree(opal_irqs);
  230. goto out;
  231. }
  232. if (WARN_ON(rc < opal_irq_count))
  233. opal_irq_count = rc;
  234. }
  235. /* Install interrupt handlers */
  236. for (i = 0; i < opal_irq_count; i++) {
  237. struct resource *r = &opal_irqs[i];
  238. const char *name;
  239. /* Prefix name */
  240. if (r->name && strlen(r->name))
  241. name = kasprintf(GFP_KERNEL, "opal-%s", r->name);
  242. else
  243. name = kasprintf(GFP_KERNEL, "opal");
  244. /* Install interrupt handler */
  245. rc = request_irq(r->start, opal_interrupt, r->flags & IRQD_TRIGGER_MASK,
  246. name, NULL);
  247. if (rc) {
  248. pr_warn("Error %d requesting OPAL irq %d\n", rc, (int)r->start);
  249. continue;
  250. }
  251. }
  252. rc = 0;
  253. out:
  254. of_node_put(opal_node);
  255. return rc;
  256. }
  257. machine_arch_initcall(powernv, opal_event_init);
  258. /**
  259. * opal_event_request(unsigned int opal_event_nr) - Request an event
  260. * @opal_event_nr: the opal event number to request
  261. *
  262. * This routine can be used to find the linux virq number which can
  263. * then be passed to request_irq to assign a handler for a particular
  264. * opal event. This should only be used by legacy devices which don't
  265. * have proper device tree bindings. Most devices should use
  266. * irq_of_parse_and_map() instead.
  267. */
  268. int opal_event_request(unsigned int opal_event_nr)
  269. {
  270. if (WARN_ON_ONCE(!opal_event_irqchip.domain))
  271. return 0;
  272. return irq_create_mapping(opal_event_irqchip.domain, opal_event_nr);
  273. }
  274. EXPORT_SYMBOL(opal_event_request);