pci.c 8.8 KB

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  1. /*
  2. * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
  3. * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
  4. *
  5. * pSeries specific routines for PCI.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/init.h>
  22. #include <linux/ioport.h>
  23. #include <linux/kernel.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <asm/eeh.h>
  27. #include <asm/pci-bridge.h>
  28. #include <asm/prom.h>
  29. #include <asm/ppc-pci.h>
  30. #include "pseries.h"
  31. #if 0
  32. void pcibios_name_device(struct pci_dev *dev)
  33. {
  34. struct device_node *dn;
  35. /*
  36. * Add IBM loc code (slot) as a prefix to the device names for service
  37. */
  38. dn = pci_device_to_OF_node(dev);
  39. if (dn) {
  40. const char *loc_code = of_get_property(dn, "ibm,loc-code",
  41. NULL);
  42. if (loc_code) {
  43. int loc_len = strlen(loc_code);
  44. if (loc_len < sizeof(dev->dev.name)) {
  45. memmove(dev->dev.name+loc_len+1, dev->dev.name,
  46. sizeof(dev->dev.name)-loc_len-1);
  47. memcpy(dev->dev.name, loc_code, loc_len);
  48. dev->dev.name[loc_len] = ' ';
  49. dev->dev.name[sizeof(dev->dev.name)-1] = '\0';
  50. }
  51. }
  52. }
  53. }
  54. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_name_device);
  55. #endif
  56. #ifdef CONFIG_PCI_IOV
  57. #define MAX_VFS_FOR_MAP_PE 256
  58. struct pe_map_bar_entry {
  59. __be64 bar; /* Input: Virtual Function BAR */
  60. __be16 rid; /* Input: Virtual Function Router ID */
  61. __be16 pe_num; /* Output: Virtual Function PE Number */
  62. __be32 reserved; /* Reserved Space */
  63. };
  64. int pseries_send_map_pe(struct pci_dev *pdev,
  65. u16 num_vfs,
  66. struct pe_map_bar_entry *vf_pe_array)
  67. {
  68. struct pci_dn *pdn;
  69. int rc;
  70. unsigned long buid, addr;
  71. int ibm_map_pes = rtas_token("ibm,open-sriov-map-pe-number");
  72. if (ibm_map_pes == RTAS_UNKNOWN_SERVICE)
  73. return -EINVAL;
  74. pdn = pci_get_pdn(pdev);
  75. addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
  76. buid = pdn->phb->buid;
  77. spin_lock(&rtas_data_buf_lock);
  78. memcpy(rtas_data_buf, vf_pe_array,
  79. RTAS_DATA_BUF_SIZE);
  80. rc = rtas_call(ibm_map_pes, 5, 1, NULL, addr,
  81. BUID_HI(buid), BUID_LO(buid),
  82. rtas_data_buf,
  83. num_vfs * sizeof(struct pe_map_bar_entry));
  84. memcpy(vf_pe_array, rtas_data_buf, RTAS_DATA_BUF_SIZE);
  85. spin_unlock(&rtas_data_buf_lock);
  86. if (rc)
  87. dev_err(&pdev->dev,
  88. "%s: Failed to associate pes PE#%lx, rc=%x\n",
  89. __func__, addr, rc);
  90. return rc;
  91. }
  92. void pseries_set_pe_num(struct pci_dev *pdev, u16 vf_index, __be16 pe_num)
  93. {
  94. struct pci_dn *pdn;
  95. pdn = pci_get_pdn(pdev);
  96. pdn->pe_num_map[vf_index] = be16_to_cpu(pe_num);
  97. dev_dbg(&pdev->dev, "VF %04x:%02x:%02x.%x associated with PE#%x\n",
  98. pci_domain_nr(pdev->bus),
  99. pdev->bus->number,
  100. PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
  101. PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)),
  102. pdn->pe_num_map[vf_index]);
  103. }
  104. int pseries_associate_pes(struct pci_dev *pdev, u16 num_vfs)
  105. {
  106. struct pci_dn *pdn;
  107. int i, rc, vf_index;
  108. struct pe_map_bar_entry *vf_pe_array;
  109. struct resource *res;
  110. u64 size;
  111. vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
  112. if (!vf_pe_array)
  113. return -ENOMEM;
  114. pdn = pci_get_pdn(pdev);
  115. /* create firmware structure to associate pes */
  116. for (vf_index = 0; vf_index < num_vfs; vf_index++) {
  117. pdn->pe_num_map[vf_index] = IODA_INVALID_PE;
  118. for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
  119. res = &pdev->resource[i + PCI_IOV_RESOURCES];
  120. if (!res->parent)
  121. continue;
  122. size = pcibios_iov_resource_alignment(pdev, i +
  123. PCI_IOV_RESOURCES);
  124. vf_pe_array[vf_index].bar =
  125. cpu_to_be64(res->start + size * vf_index);
  126. vf_pe_array[vf_index].rid =
  127. cpu_to_be16((pci_iov_virtfn_bus(pdev, vf_index)
  128. << 8) | pci_iov_virtfn_devfn(pdev,
  129. vf_index));
  130. vf_pe_array[vf_index].pe_num =
  131. cpu_to_be16(IODA_INVALID_PE);
  132. }
  133. }
  134. rc = pseries_send_map_pe(pdev, num_vfs, vf_pe_array);
  135. /* Only zero is success */
  136. if (!rc)
  137. for (vf_index = 0; vf_index < num_vfs; vf_index++)
  138. pseries_set_pe_num(pdev, vf_index,
  139. vf_pe_array[vf_index].pe_num);
  140. kfree(vf_pe_array);
  141. return rc;
  142. }
  143. int pseries_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
  144. {
  145. struct pci_dn *pdn;
  146. int rc;
  147. const int *max_vfs;
  148. int max_config_vfs;
  149. struct device_node *dn = pci_device_to_OF_node(pdev);
  150. max_vfs = of_get_property(dn, "ibm,number-of-configurable-vfs", NULL);
  151. if (!max_vfs)
  152. return -EINVAL;
  153. /* First integer stores max config */
  154. max_config_vfs = of_read_number(&max_vfs[0], 1);
  155. if (max_config_vfs < num_vfs && num_vfs > MAX_VFS_FOR_MAP_PE) {
  156. dev_err(&pdev->dev,
  157. "Num VFs %x > %x Configurable VFs\n",
  158. num_vfs, (num_vfs > MAX_VFS_FOR_MAP_PE) ?
  159. MAX_VFS_FOR_MAP_PE : max_config_vfs);
  160. return -EINVAL;
  161. }
  162. pdn = pci_get_pdn(pdev);
  163. pdn->pe_num_map = kmalloc_array(num_vfs,
  164. sizeof(*pdn->pe_num_map),
  165. GFP_KERNEL);
  166. if (!pdn->pe_num_map)
  167. return -ENOMEM;
  168. rc = pseries_associate_pes(pdev, num_vfs);
  169. /* Anything other than zero is failure */
  170. if (rc) {
  171. dev_err(&pdev->dev, "Failure to enable sriov: %x\n", rc);
  172. kfree(pdn->pe_num_map);
  173. } else {
  174. pci_vf_drivers_autoprobe(pdev, false);
  175. }
  176. return rc;
  177. }
  178. int pseries_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
  179. {
  180. /* Allocate PCI data */
  181. add_dev_pci_data(pdev);
  182. return pseries_pci_sriov_enable(pdev, num_vfs);
  183. }
  184. int pseries_pcibios_sriov_disable(struct pci_dev *pdev)
  185. {
  186. struct pci_dn *pdn;
  187. pdn = pci_get_pdn(pdev);
  188. /* Releasing pe_num_map */
  189. kfree(pdn->pe_num_map);
  190. /* Release PCI data */
  191. remove_dev_pci_data(pdev);
  192. pci_vf_drivers_autoprobe(pdev, true);
  193. return 0;
  194. }
  195. #endif
  196. static void __init pSeries_request_regions(void)
  197. {
  198. if (!isa_io_base)
  199. return;
  200. request_region(0x20,0x20,"pic1");
  201. request_region(0xa0,0x20,"pic2");
  202. request_region(0x00,0x20,"dma1");
  203. request_region(0x40,0x20,"timer");
  204. request_region(0x80,0x10,"dma page reg");
  205. request_region(0xc0,0x20,"dma2");
  206. }
  207. void __init pSeries_final_fixup(void)
  208. {
  209. pSeries_request_regions();
  210. eeh_addr_cache_build();
  211. #ifdef CONFIG_PCI_IOV
  212. ppc_md.pcibios_sriov_enable = pseries_pcibios_sriov_enable;
  213. ppc_md.pcibios_sriov_disable = pseries_pcibios_sriov_disable;
  214. #endif
  215. }
  216. /*
  217. * Assume the winbond 82c105 is the IDE controller on a
  218. * p610/p615/p630. We should probably be more careful in case
  219. * someone tries to plug in a similar adapter.
  220. */
  221. static void fixup_winbond_82c105(struct pci_dev* dev)
  222. {
  223. int i;
  224. unsigned int reg;
  225. if (!machine_is(pseries))
  226. return;
  227. printk("Using INTC for W82c105 IDE controller.\n");
  228. pci_read_config_dword(dev, 0x40, &reg);
  229. /* Enable LEGIRQ to use INTC instead of ISA interrupts */
  230. pci_write_config_dword(dev, 0x40, reg | (1<<11));
  231. for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
  232. /* zap the 2nd function of the winbond chip */
  233. if (dev->resource[i].flags & IORESOURCE_IO
  234. && dev->bus->number == 0 && dev->devfn == 0x81)
  235. dev->resource[i].flags &= ~IORESOURCE_IO;
  236. if (dev->resource[i].start == 0 && dev->resource[i].end) {
  237. dev->resource[i].flags = 0;
  238. dev->resource[i].end = 0;
  239. }
  240. }
  241. }
  242. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
  243. fixup_winbond_82c105);
  244. int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
  245. {
  246. struct device_node *dn, *pdn;
  247. struct pci_bus *bus;
  248. u32 pcie_link_speed_stats[2];
  249. int rc;
  250. bus = bridge->bus;
  251. /* Rely on the pcibios_free_controller_deferred() callback. */
  252. pci_set_host_bridge_release(bridge, pcibios_free_controller_deferred,
  253. (void *) pci_bus_to_host(bus));
  254. dn = pcibios_get_phb_of_node(bus);
  255. if (!dn)
  256. return 0;
  257. for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
  258. rc = of_property_read_u32_array(pdn,
  259. "ibm,pcie-link-speed-stats",
  260. &pcie_link_speed_stats[0], 2);
  261. if (!rc)
  262. break;
  263. }
  264. of_node_put(pdn);
  265. if (rc) {
  266. pr_debug("no ibm,pcie-link-speed-stats property\n");
  267. return 0;
  268. }
  269. switch (pcie_link_speed_stats[0]) {
  270. case 0x01:
  271. bus->max_bus_speed = PCIE_SPEED_2_5GT;
  272. break;
  273. case 0x02:
  274. bus->max_bus_speed = PCIE_SPEED_5_0GT;
  275. break;
  276. case 0x04:
  277. bus->max_bus_speed = PCIE_SPEED_8_0GT;
  278. break;
  279. default:
  280. bus->max_bus_speed = PCI_SPEED_UNKNOWN;
  281. break;
  282. }
  283. switch (pcie_link_speed_stats[1]) {
  284. case 0x01:
  285. bus->cur_bus_speed = PCIE_SPEED_2_5GT;
  286. break;
  287. case 0x02:
  288. bus->cur_bus_speed = PCIE_SPEED_5_0GT;
  289. break;
  290. case 0x04:
  291. bus->cur_bus_speed = PCIE_SPEED_8_0GT;
  292. break;
  293. default:
  294. bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
  295. break;
  296. }
  297. return 0;
  298. }