xilinx_intc.c 2.2 KB

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  1. /*
  2. * Interrupt controller driver for Xilinx Virtex FPGAs
  3. *
  4. * Copyright (C) 2007 Secret Lab Technologies Ltd.
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. *
  10. */
  11. /*
  12. * This is a driver for the interrupt controller typically found in
  13. * Xilinx Virtex FPGA designs.
  14. *
  15. * The interrupt sense levels are hard coded into the FPGA design with
  16. * typically a 1:1 relationship between irq lines and devices (no shared
  17. * irq lines). Therefore, this driver does not attempt to handle edge
  18. * and level interrupts differently.
  19. */
  20. #undef DEBUG
  21. #include <linux/kernel.h>
  22. #include <linux/irq.h>
  23. #include <linux/of.h>
  24. #include <linux/of_address.h>
  25. #include <linux/of_irq.h>
  26. #include <asm/io.h>
  27. #include <asm/processor.h>
  28. #include <asm/i8259.h>
  29. #include <asm/irq.h>
  30. #include <linux/irqchip.h>
  31. #if defined(CONFIG_PPC_I8259)
  32. /*
  33. * Support code for cascading to 8259 interrupt controllers
  34. */
  35. static void xilinx_i8259_cascade(struct irq_desc *desc)
  36. {
  37. struct irq_chip *chip = irq_desc_get_chip(desc);
  38. unsigned int cascade_irq = i8259_irq();
  39. if (cascade_irq)
  40. generic_handle_irq(cascade_irq);
  41. /* Let xilinx_intc end the interrupt */
  42. chip->irq_unmask(&desc->irq_data);
  43. }
  44. static void __init xilinx_i8259_setup_cascade(void)
  45. {
  46. struct device_node *cascade_node;
  47. int cascade_irq;
  48. /* Initialize i8259 controller */
  49. cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
  50. if (!cascade_node)
  51. return;
  52. cascade_irq = irq_of_parse_and_map(cascade_node, 0);
  53. if (!cascade_irq) {
  54. pr_err("virtex_ml510: Failed to map cascade interrupt\n");
  55. goto out;
  56. }
  57. i8259_init(cascade_node, 0);
  58. irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade);
  59. /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
  60. /* This looks like a dirty hack to me --gcl */
  61. outb(0xc0, 0x4d0);
  62. outb(0xc0, 0x4d1);
  63. out:
  64. of_node_put(cascade_node);
  65. }
  66. #else
  67. static inline void xilinx_i8259_setup_cascade(void) { return; }
  68. #endif /* defined(CONFIG_PPC_I8259) */
  69. /*
  70. * Initialize master Xilinx interrupt controller
  71. */
  72. void __init xilinx_intc_init_tree(void)
  73. {
  74. irqchip_init();
  75. xilinx_i8259_setup_cascade();
  76. }