intel-mid.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216
  1. /*
  2. * intel-mid.c: Intel MID platform setup code
  3. *
  4. * (C) Copyright 2008, 2012 Intel Corporation
  5. * Author: Jacob Pan (jacob.jun.pan@intel.com)
  6. * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; version 2
  11. * of the License.
  12. */
  13. #define pr_fmt(fmt) "intel_mid: " fmt
  14. #include <linux/init.h>
  15. #include <linux/kernel.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/regulator/machine.h>
  18. #include <linux/scatterlist.h>
  19. #include <linux/sfi.h>
  20. #include <linux/irq.h>
  21. #include <linux/export.h>
  22. #include <linux/notifier.h>
  23. #include <asm/setup.h>
  24. #include <asm/mpspec_def.h>
  25. #include <asm/hw_irq.h>
  26. #include <asm/apic.h>
  27. #include <asm/io_apic.h>
  28. #include <asm/intel-mid.h>
  29. #include <asm/intel_mid_vrtc.h>
  30. #include <asm/io.h>
  31. #include <asm/i8259.h>
  32. #include <asm/intel_scu_ipc.h>
  33. #include <asm/apb_timer.h>
  34. #include <asm/reboot.h>
  35. /*
  36. * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
  37. * cmdline option x86_intel_mid_timer can be used to override the configuration
  38. * to prefer one or the other.
  39. * at runtime, there are basically three timer configurations:
  40. * 1. per cpu apbt clock only
  41. * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
  42. * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
  43. *
  44. * by default (without cmdline option), platform code first detects cpu type
  45. * to see if we are on lincroft or penwell, then set up both lapic or apbt
  46. * clocks accordingly.
  47. * i.e. by default, medfield uses configuration #2, moorestown uses #1.
  48. * config #3 is supported but not recommended on medfield.
  49. *
  50. * rating and feature summary:
  51. * lapic (with C3STOP) --------- 100
  52. * apbt (always-on) ------------ 110
  53. * lapic (always-on,ARAT) ------ 150
  54. */
  55. enum intel_mid_timer_options intel_mid_timer_options;
  56. enum intel_mid_cpu_type __intel_mid_cpu_chip;
  57. EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
  58. static void intel_mid_power_off(void)
  59. {
  60. /* Shut down South Complex via PWRMU */
  61. intel_mid_pwr_power_off();
  62. /* Only for Tangier, the rest will ignore this command */
  63. intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1);
  64. };
  65. static void intel_mid_reboot(void)
  66. {
  67. intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
  68. }
  69. static void __init intel_mid_setup_bp_timer(void)
  70. {
  71. apbt_time_init();
  72. setup_boot_APIC_clock();
  73. }
  74. static void __init intel_mid_time_init(void)
  75. {
  76. sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
  77. switch (intel_mid_timer_options) {
  78. case INTEL_MID_TIMER_APBT_ONLY:
  79. break;
  80. case INTEL_MID_TIMER_LAPIC_APBT:
  81. /* Use apbt and local apic */
  82. x86_init.timers.setup_percpu_clockev = intel_mid_setup_bp_timer;
  83. x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
  84. return;
  85. default:
  86. if (!boot_cpu_has(X86_FEATURE_ARAT))
  87. break;
  88. /* Lapic only, no apbt */
  89. x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
  90. x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
  91. return;
  92. }
  93. x86_init.timers.setup_percpu_clockev = apbt_time_init;
  94. }
  95. static void intel_mid_arch_setup(void)
  96. {
  97. if (boot_cpu_data.x86 != 6) {
  98. pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
  99. boot_cpu_data.x86, boot_cpu_data.x86_model);
  100. __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
  101. goto out;
  102. }
  103. switch (boot_cpu_data.x86_model) {
  104. case 0x35:
  105. __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
  106. break;
  107. case 0x3C:
  108. case 0x4A:
  109. __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
  110. x86_platform.legacy.rtc = 1;
  111. break;
  112. case 0x27:
  113. default:
  114. __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
  115. break;
  116. }
  117. out:
  118. /*
  119. * Intel MID platforms are using explicitly defined regulators.
  120. *
  121. * Let the regulator core know that we do not have any additional
  122. * regulators left. This lets it substitute unprovided regulators with
  123. * dummy ones:
  124. */
  125. regulator_has_full_constraints();
  126. }
  127. /*
  128. * Moorestown does not have external NMI source nor port 0x61 to report
  129. * NMI status. The possible NMI sources are from pmu as a result of NMI
  130. * watchdog or lock debug. Reading io port 0x61 results in 0xff which
  131. * misled NMI handler.
  132. */
  133. static unsigned char intel_mid_get_nmi_reason(void)
  134. {
  135. return 0;
  136. }
  137. /*
  138. * Moorestown specific x86_init function overrides and early setup
  139. * calls.
  140. */
  141. void __init x86_intel_mid_early_setup(void)
  142. {
  143. x86_init.resources.probe_roms = x86_init_noop;
  144. x86_init.resources.reserve_resources = x86_init_noop;
  145. x86_init.timers.timer_init = intel_mid_time_init;
  146. x86_init.timers.setup_percpu_clockev = x86_init_noop;
  147. x86_init.timers.wallclock_init = intel_mid_rtc_init;
  148. x86_init.irqs.pre_vector_init = x86_init_noop;
  149. x86_init.oem.arch_setup = intel_mid_arch_setup;
  150. x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
  151. x86_platform.get_nmi_reason = intel_mid_get_nmi_reason;
  152. x86_init.pci.arch_init = intel_mid_pci_init;
  153. x86_init.pci.fixup_irqs = x86_init_noop;
  154. legacy_pic = &null_legacy_pic;
  155. /*
  156. * Do nothing for now as everything needed done in
  157. * x86_intel_mid_early_setup() below.
  158. */
  159. x86_init.acpi.reduced_hw_early_init = x86_init_noop;
  160. pm_power_off = intel_mid_power_off;
  161. machine_ops.emergency_restart = intel_mid_reboot;
  162. /* Avoid searching for BIOS MP tables */
  163. x86_init.mpparse.find_smp_config = x86_init_noop;
  164. x86_init.mpparse.get_smp_config = x86_init_uint_noop;
  165. set_bit(MP_BUS_ISA, mp_bus_not_pci);
  166. }
  167. /*
  168. * if user does not want to use per CPU apb timer, just give it a lower rating
  169. * than local apic timer and skip the late per cpu timer init.
  170. */
  171. static inline int __init setup_x86_intel_mid_timer(char *arg)
  172. {
  173. if (!arg)
  174. return -EINVAL;
  175. if (strcmp("apbt_only", arg) == 0)
  176. intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY;
  177. else if (strcmp("lapic_and_apbt", arg) == 0)
  178. intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT;
  179. else {
  180. pr_warn("X86 INTEL_MID timer option %s not recognised use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n",
  181. arg);
  182. return -EINVAL;
  183. }
  184. return 0;
  185. }
  186. __setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer);