sfi.c 14 KB

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  1. /*
  2. * intel_mid_sfi.c: Intel MID SFI initialization code
  3. *
  4. * (C) Copyright 2013 Intel Corporation
  5. * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; version 2
  10. * of the License.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/scatterlist.h>
  16. #include <linux/sfi.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/i2c.h>
  19. #include <linux/skbuff.h>
  20. #include <linux/gpio.h>
  21. #include <linux/gpio_keys.h>
  22. #include <linux/input.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/irq.h>
  25. #include <linux/export.h>
  26. #include <linux/notifier.h>
  27. #include <linux/mmc/core.h>
  28. #include <linux/mmc/card.h>
  29. #include <linux/blkdev.h>
  30. #include <asm/setup.h>
  31. #include <asm/mpspec_def.h>
  32. #include <asm/hw_irq.h>
  33. #include <asm/apic.h>
  34. #include <asm/io_apic.h>
  35. #include <asm/intel-mid.h>
  36. #include <asm/intel_mid_vrtc.h>
  37. #include <asm/io.h>
  38. #include <asm/i8259.h>
  39. #include <asm/intel_scu_ipc.h>
  40. #include <asm/apb_timer.h>
  41. #include <asm/reboot.h>
  42. #define SFI_SIG_OEM0 "OEM0"
  43. #define MAX_IPCDEVS 24
  44. #define MAX_SCU_SPI 24
  45. #define MAX_SCU_I2C 24
  46. static struct platform_device *ipc_devs[MAX_IPCDEVS];
  47. static struct spi_board_info *spi_devs[MAX_SCU_SPI];
  48. static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
  49. static struct sfi_gpio_table_entry *gpio_table;
  50. static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
  51. static int ipc_next_dev;
  52. static int spi_next_dev;
  53. static int i2c_next_dev;
  54. static int i2c_bus[MAX_SCU_I2C];
  55. static int gpio_num_entry;
  56. static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
  57. int sfi_mrtc_num;
  58. int sfi_mtimer_num;
  59. struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
  60. EXPORT_SYMBOL_GPL(sfi_mrtc_array);
  61. struct blocking_notifier_head intel_scu_notifier =
  62. BLOCKING_NOTIFIER_INIT(intel_scu_notifier);
  63. EXPORT_SYMBOL_GPL(intel_scu_notifier);
  64. #define intel_mid_sfi_get_pdata(dev, priv) \
  65. ((dev)->get_platform_data ? (dev)->get_platform_data(priv) : NULL)
  66. /* parse all the mtimer info to a static mtimer array */
  67. int __init sfi_parse_mtmr(struct sfi_table_header *table)
  68. {
  69. struct sfi_table_simple *sb;
  70. struct sfi_timer_table_entry *pentry;
  71. struct mpc_intsrc mp_irq;
  72. int totallen;
  73. sb = (struct sfi_table_simple *)table;
  74. if (!sfi_mtimer_num) {
  75. sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
  76. struct sfi_timer_table_entry);
  77. pentry = (struct sfi_timer_table_entry *) sb->pentry;
  78. totallen = sfi_mtimer_num * sizeof(*pentry);
  79. memcpy(sfi_mtimer_array, pentry, totallen);
  80. }
  81. pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
  82. pentry = sfi_mtimer_array;
  83. for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
  84. pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz, irq = %d\n",
  85. totallen, (u32)pentry->phys_addr,
  86. pentry->freq_hz, pentry->irq);
  87. mp_irq.type = MP_INTSRC;
  88. mp_irq.irqtype = mp_INT;
  89. mp_irq.irqflag = MP_IRQTRIG_EDGE | MP_IRQPOL_ACTIVE_HIGH;
  90. mp_irq.srcbus = MP_BUS_ISA;
  91. mp_irq.srcbusirq = pentry->irq; /* IRQ */
  92. mp_irq.dstapic = MP_APIC_ALL;
  93. mp_irq.dstirq = pentry->irq;
  94. mp_save_irq(&mp_irq);
  95. mp_map_gsi_to_irq(pentry->irq, IOAPIC_MAP_ALLOC, NULL);
  96. }
  97. return 0;
  98. }
  99. struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
  100. {
  101. int i;
  102. if (hint < sfi_mtimer_num) {
  103. if (!sfi_mtimer_usage[hint]) {
  104. pr_debug("hint taken for timer %d irq %d\n",
  105. hint, sfi_mtimer_array[hint].irq);
  106. sfi_mtimer_usage[hint] = 1;
  107. return &sfi_mtimer_array[hint];
  108. }
  109. }
  110. /* take the first timer available */
  111. for (i = 0; i < sfi_mtimer_num;) {
  112. if (!sfi_mtimer_usage[i]) {
  113. sfi_mtimer_usage[i] = 1;
  114. return &sfi_mtimer_array[i];
  115. }
  116. i++;
  117. }
  118. return NULL;
  119. }
  120. void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
  121. {
  122. int i;
  123. for (i = 0; i < sfi_mtimer_num;) {
  124. if (mtmr->irq == sfi_mtimer_array[i].irq) {
  125. sfi_mtimer_usage[i] = 0;
  126. return;
  127. }
  128. i++;
  129. }
  130. }
  131. /* parse all the mrtc info to a global mrtc array */
  132. int __init sfi_parse_mrtc(struct sfi_table_header *table)
  133. {
  134. struct sfi_table_simple *sb;
  135. struct sfi_rtc_table_entry *pentry;
  136. struct mpc_intsrc mp_irq;
  137. int totallen;
  138. sb = (struct sfi_table_simple *)table;
  139. if (!sfi_mrtc_num) {
  140. sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
  141. struct sfi_rtc_table_entry);
  142. pentry = (struct sfi_rtc_table_entry *)sb->pentry;
  143. totallen = sfi_mrtc_num * sizeof(*pentry);
  144. memcpy(sfi_mrtc_array, pentry, totallen);
  145. }
  146. pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
  147. pentry = sfi_mrtc_array;
  148. for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
  149. pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
  150. totallen, (u32)pentry->phys_addr, pentry->irq);
  151. mp_irq.type = MP_INTSRC;
  152. mp_irq.irqtype = mp_INT;
  153. mp_irq.irqflag = MP_IRQTRIG_LEVEL | MP_IRQPOL_ACTIVE_LOW;
  154. mp_irq.srcbus = MP_BUS_ISA;
  155. mp_irq.srcbusirq = pentry->irq; /* IRQ */
  156. mp_irq.dstapic = MP_APIC_ALL;
  157. mp_irq.dstirq = pentry->irq;
  158. mp_save_irq(&mp_irq);
  159. mp_map_gsi_to_irq(pentry->irq, IOAPIC_MAP_ALLOC, NULL);
  160. }
  161. return 0;
  162. }
  163. /*
  164. * Parsing GPIO table first, since the DEVS table will need this table
  165. * to map the pin name to the actual pin.
  166. */
  167. static int __init sfi_parse_gpio(struct sfi_table_header *table)
  168. {
  169. struct sfi_table_simple *sb;
  170. struct sfi_gpio_table_entry *pentry;
  171. int num, i;
  172. if (gpio_table)
  173. return 0;
  174. sb = (struct sfi_table_simple *)table;
  175. num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
  176. pentry = (struct sfi_gpio_table_entry *)sb->pentry;
  177. gpio_table = kmemdup(pentry, num * sizeof(*pentry), GFP_KERNEL);
  178. if (!gpio_table)
  179. return -1;
  180. gpio_num_entry = num;
  181. pr_debug("GPIO pin info:\n");
  182. for (i = 0; i < num; i++, pentry++)
  183. pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
  184. " pin = %d\n", i,
  185. pentry->controller_name,
  186. pentry->pin_name,
  187. pentry->pin_no);
  188. return 0;
  189. }
  190. int get_gpio_by_name(const char *name)
  191. {
  192. struct sfi_gpio_table_entry *pentry = gpio_table;
  193. int i;
  194. if (!pentry)
  195. return -1;
  196. for (i = 0; i < gpio_num_entry; i++, pentry++) {
  197. if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
  198. return pentry->pin_no;
  199. }
  200. return -EINVAL;
  201. }
  202. static void __init intel_scu_ipc_device_register(struct platform_device *pdev)
  203. {
  204. if (ipc_next_dev == MAX_IPCDEVS)
  205. pr_err("too many SCU IPC devices");
  206. else
  207. ipc_devs[ipc_next_dev++] = pdev;
  208. }
  209. static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
  210. {
  211. struct spi_board_info *new_dev;
  212. if (spi_next_dev == MAX_SCU_SPI) {
  213. pr_err("too many SCU SPI devices");
  214. return;
  215. }
  216. new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
  217. if (!new_dev) {
  218. pr_err("failed to alloc mem for delayed spi dev %s\n",
  219. sdev->modalias);
  220. return;
  221. }
  222. *new_dev = *sdev;
  223. spi_devs[spi_next_dev++] = new_dev;
  224. }
  225. static void __init intel_scu_i2c_device_register(int bus,
  226. struct i2c_board_info *idev)
  227. {
  228. struct i2c_board_info *new_dev;
  229. if (i2c_next_dev == MAX_SCU_I2C) {
  230. pr_err("too many SCU I2C devices");
  231. return;
  232. }
  233. new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
  234. if (!new_dev) {
  235. pr_err("failed to alloc mem for delayed i2c dev %s\n",
  236. idev->type);
  237. return;
  238. }
  239. *new_dev = *idev;
  240. i2c_bus[i2c_next_dev] = bus;
  241. i2c_devs[i2c_next_dev++] = new_dev;
  242. }
  243. /* Called by IPC driver */
  244. void intel_scu_devices_create(void)
  245. {
  246. int i;
  247. for (i = 0; i < ipc_next_dev; i++)
  248. platform_device_add(ipc_devs[i]);
  249. for (i = 0; i < spi_next_dev; i++)
  250. spi_register_board_info(spi_devs[i], 1);
  251. for (i = 0; i < i2c_next_dev; i++) {
  252. struct i2c_adapter *adapter;
  253. struct i2c_client *client;
  254. adapter = i2c_get_adapter(i2c_bus[i]);
  255. if (adapter) {
  256. client = i2c_new_device(adapter, i2c_devs[i]);
  257. if (!client)
  258. pr_err("can't create i2c device %s\n",
  259. i2c_devs[i]->type);
  260. } else
  261. i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
  262. }
  263. intel_scu_notifier_post(SCU_AVAILABLE, NULL);
  264. }
  265. EXPORT_SYMBOL_GPL(intel_scu_devices_create);
  266. /* Called by IPC driver */
  267. void intel_scu_devices_destroy(void)
  268. {
  269. int i;
  270. intel_scu_notifier_post(SCU_DOWN, NULL);
  271. for (i = 0; i < ipc_next_dev; i++)
  272. platform_device_del(ipc_devs[i]);
  273. }
  274. EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
  275. static void __init install_irq_resource(struct platform_device *pdev, int irq)
  276. {
  277. /* Single threaded */
  278. static struct resource res __initdata = {
  279. .name = "IRQ",
  280. .flags = IORESOURCE_IRQ,
  281. };
  282. res.start = irq;
  283. platform_device_add_resources(pdev, &res, 1);
  284. }
  285. static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *pentry,
  286. struct devs_id *dev)
  287. {
  288. struct platform_device *pdev;
  289. void *pdata = NULL;
  290. pr_debug("IPC bus, name = %16.16s, irq = 0x%2x\n",
  291. pentry->name, pentry->irq);
  292. /*
  293. * We need to call platform init of IPC devices to fill misc_pdata
  294. * structure. It will be used in msic_init for initialization.
  295. */
  296. pdata = intel_mid_sfi_get_pdata(dev, pentry);
  297. if (IS_ERR(pdata))
  298. return;
  299. /*
  300. * On Medfield the platform device creation is handled by the MSIC
  301. * MFD driver so we don't need to do it here.
  302. */
  303. if (dev->msic && intel_mid_has_msic())
  304. return;
  305. pdev = platform_device_alloc(pentry->name, 0);
  306. if (pdev == NULL) {
  307. pr_err("out of memory for SFI platform device '%s'.\n",
  308. pentry->name);
  309. return;
  310. }
  311. install_irq_resource(pdev, pentry->irq);
  312. pdev->dev.platform_data = pdata;
  313. if (dev->delay)
  314. intel_scu_ipc_device_register(pdev);
  315. else
  316. platform_device_add(pdev);
  317. }
  318. static void __init sfi_handle_spi_dev(struct sfi_device_table_entry *pentry,
  319. struct devs_id *dev)
  320. {
  321. struct spi_board_info spi_info;
  322. void *pdata = NULL;
  323. memset(&spi_info, 0, sizeof(spi_info));
  324. strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
  325. spi_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq);
  326. spi_info.bus_num = pentry->host_num;
  327. spi_info.chip_select = pentry->addr;
  328. spi_info.max_speed_hz = pentry->max_freq;
  329. pr_debug("SPI bus=%d, name=%16.16s, irq=0x%2x, max_freq=%d, cs=%d\n",
  330. spi_info.bus_num,
  331. spi_info.modalias,
  332. spi_info.irq,
  333. spi_info.max_speed_hz,
  334. spi_info.chip_select);
  335. pdata = intel_mid_sfi_get_pdata(dev, &spi_info);
  336. if (IS_ERR(pdata))
  337. return;
  338. spi_info.platform_data = pdata;
  339. if (dev->delay)
  340. intel_scu_spi_device_register(&spi_info);
  341. else
  342. spi_register_board_info(&spi_info, 1);
  343. }
  344. static void __init sfi_handle_i2c_dev(struct sfi_device_table_entry *pentry,
  345. struct devs_id *dev)
  346. {
  347. struct i2c_board_info i2c_info;
  348. void *pdata = NULL;
  349. memset(&i2c_info, 0, sizeof(i2c_info));
  350. strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
  351. i2c_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq);
  352. i2c_info.addr = pentry->addr;
  353. pr_debug("I2C bus = %d, name = %16.16s, irq = 0x%2x, addr = 0x%x\n",
  354. pentry->host_num,
  355. i2c_info.type,
  356. i2c_info.irq,
  357. i2c_info.addr);
  358. pdata = intel_mid_sfi_get_pdata(dev, &i2c_info);
  359. i2c_info.platform_data = pdata;
  360. if (IS_ERR(pdata))
  361. return;
  362. if (dev->delay)
  363. intel_scu_i2c_device_register(pentry->host_num, &i2c_info);
  364. else
  365. i2c_register_board_info(pentry->host_num, &i2c_info, 1);
  366. }
  367. static void __init sfi_handle_sd_dev(struct sfi_device_table_entry *pentry,
  368. struct devs_id *dev)
  369. {
  370. struct mid_sd_board_info sd_info;
  371. void *pdata;
  372. memset(&sd_info, 0, sizeof(sd_info));
  373. strncpy(sd_info.name, pentry->name, SFI_NAME_LEN);
  374. sd_info.bus_num = pentry->host_num;
  375. sd_info.max_clk = pentry->max_freq;
  376. sd_info.addr = pentry->addr;
  377. pr_debug("SD bus = %d, name = %16.16s, max_clk = %d, addr = 0x%x\n",
  378. sd_info.bus_num,
  379. sd_info.name,
  380. sd_info.max_clk,
  381. sd_info.addr);
  382. pdata = intel_mid_sfi_get_pdata(dev, &sd_info);
  383. if (IS_ERR(pdata))
  384. return;
  385. /* Nothing we can do with this for now */
  386. sd_info.platform_data = pdata;
  387. pr_debug("Successfully registered %16.16s", sd_info.name);
  388. }
  389. extern struct devs_id *const __x86_intel_mid_dev_start[],
  390. *const __x86_intel_mid_dev_end[];
  391. static struct devs_id __init *get_device_id(u8 type, char *name)
  392. {
  393. struct devs_id *const *dev_table;
  394. for (dev_table = __x86_intel_mid_dev_start;
  395. dev_table < __x86_intel_mid_dev_end; dev_table++) {
  396. struct devs_id *dev = *dev_table;
  397. if (dev->type == type &&
  398. !strncmp(dev->name, name, SFI_NAME_LEN)) {
  399. return dev;
  400. }
  401. }
  402. return NULL;
  403. }
  404. static int __init sfi_parse_devs(struct sfi_table_header *table)
  405. {
  406. struct sfi_table_simple *sb;
  407. struct sfi_device_table_entry *pentry;
  408. struct devs_id *dev = NULL;
  409. int num, i, ret;
  410. int polarity;
  411. struct irq_alloc_info info;
  412. sb = (struct sfi_table_simple *)table;
  413. num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
  414. pentry = (struct sfi_device_table_entry *)sb->pentry;
  415. for (i = 0; i < num; i++, pentry++) {
  416. int irq = pentry->irq;
  417. if (irq != (u8)0xff) { /* native RTE case */
  418. /* these SPI2 devices are not exposed to system as PCI
  419. * devices, but they have separate RTE entry in IOAPIC
  420. * so we have to enable them one by one here
  421. */
  422. if (intel_mid_identify_cpu() ==
  423. INTEL_MID_CPU_CHIP_TANGIER) {
  424. if (!strncmp(pentry->name, "r69001-ts-i2c", 13))
  425. /* active low */
  426. polarity = 1;
  427. else if (!strncmp(pentry->name,
  428. "synaptics_3202", 14))
  429. /* active low */
  430. polarity = 1;
  431. else if (irq == 41)
  432. /* fast_int_1 */
  433. polarity = 1;
  434. else
  435. /* active high */
  436. polarity = 0;
  437. } else {
  438. /* PNW and CLV go with active low */
  439. polarity = 1;
  440. }
  441. ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 1, polarity);
  442. ret = mp_map_gsi_to_irq(irq, IOAPIC_MAP_ALLOC, &info);
  443. WARN_ON(ret < 0);
  444. }
  445. dev = get_device_id(pentry->type, pentry->name);
  446. if (!dev)
  447. continue;
  448. switch (pentry->type) {
  449. case SFI_DEV_TYPE_IPC:
  450. sfi_handle_ipc_dev(pentry, dev);
  451. break;
  452. case SFI_DEV_TYPE_SPI:
  453. sfi_handle_spi_dev(pentry, dev);
  454. break;
  455. case SFI_DEV_TYPE_I2C:
  456. sfi_handle_i2c_dev(pentry, dev);
  457. break;
  458. case SFI_DEV_TYPE_SD:
  459. sfi_handle_sd_dev(pentry, dev);
  460. break;
  461. case SFI_DEV_TYPE_UART:
  462. case SFI_DEV_TYPE_HSI:
  463. default:
  464. break;
  465. }
  466. }
  467. return 0;
  468. }
  469. static int __init intel_mid_platform_init(void)
  470. {
  471. sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
  472. sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
  473. return 0;
  474. }
  475. arch_initcall(intel_mid_platform_init);