core.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * core.c - ChipIdea USB IP core family device controller
  4. *
  5. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  6. *
  7. * Author: David Lopo
  8. */
  9. /*
  10. * Description: ChipIdea USB IP core family device controller
  11. *
  12. * This driver is composed of several blocks:
  13. * - HW: hardware interface
  14. * - DBG: debug facilities (optional)
  15. * - UTIL: utilities
  16. * - ISR: interrupts handling
  17. * - ENDPT: endpoint operations (Gadget API)
  18. * - GADGET: gadget operations (Gadget API)
  19. * - BUS: bus glue code, bus abstraction layer
  20. *
  21. * Compile Options
  22. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  23. * if defined mass storage compliance succeeds but with warnings
  24. * => case 4: Hi > Dn
  25. * => case 5: Hi > Di
  26. * => case 8: Hi <> Do
  27. * if undefined usbtest 13 fails
  28. * - TRACE: enable function tracing (depends on DEBUG)
  29. *
  30. * Main Features
  31. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  32. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  33. * - Normal & LPM support
  34. *
  35. * USBTEST Report
  36. * - OK: 0-12, 13 (STALL_IN defined) & 14
  37. * - Not Supported: 15 & 16 (ISO)
  38. *
  39. * TODO List
  40. * - Suspend & Remote Wakeup
  41. */
  42. #include <linux/delay.h>
  43. #include <linux/device.h>
  44. #include <linux/dma-mapping.h>
  45. #include <linux/extcon.h>
  46. #include <linux/phy/phy.h>
  47. #include <linux/platform_device.h>
  48. #include <linux/module.h>
  49. #include <linux/idr.h>
  50. #include <linux/interrupt.h>
  51. #include <linux/io.h>
  52. #include <linux/kernel.h>
  53. #include <linux/slab.h>
  54. #include <linux/pm_runtime.h>
  55. #include <linux/usb/ch9.h>
  56. #include <linux/usb/gadget.h>
  57. #include <linux/usb/otg.h>
  58. #include <linux/usb/chipidea.h>
  59. #include <linux/usb/of.h>
  60. #include <linux/of.h>
  61. #include <linux/regulator/consumer.h>
  62. #include <linux/usb/ehci_def.h>
  63. #include "ci.h"
  64. #include "udc.h"
  65. #include "bits.h"
  66. #include "host.h"
  67. #include "otg.h"
  68. #include "otg_fsm.h"
  69. /* Controller register map */
  70. static const u8 ci_regs_nolpm[] = {
  71. [CAP_CAPLENGTH] = 0x00U,
  72. [CAP_HCCPARAMS] = 0x08U,
  73. [CAP_DCCPARAMS] = 0x24U,
  74. [CAP_TESTMODE] = 0x38U,
  75. [OP_USBCMD] = 0x00U,
  76. [OP_USBSTS] = 0x04U,
  77. [OP_USBINTR] = 0x08U,
  78. [OP_DEVICEADDR] = 0x14U,
  79. [OP_ENDPTLISTADDR] = 0x18U,
  80. [OP_TTCTRL] = 0x1CU,
  81. [OP_BURSTSIZE] = 0x20U,
  82. [OP_ULPI_VIEWPORT] = 0x30U,
  83. [OP_PORTSC] = 0x44U,
  84. [OP_DEVLC] = 0x84U,
  85. [OP_OTGSC] = 0x64U,
  86. [OP_USBMODE] = 0x68U,
  87. [OP_ENDPTSETUPSTAT] = 0x6CU,
  88. [OP_ENDPTPRIME] = 0x70U,
  89. [OP_ENDPTFLUSH] = 0x74U,
  90. [OP_ENDPTSTAT] = 0x78U,
  91. [OP_ENDPTCOMPLETE] = 0x7CU,
  92. [OP_ENDPTCTRL] = 0x80U,
  93. };
  94. static const u8 ci_regs_lpm[] = {
  95. [CAP_CAPLENGTH] = 0x00U,
  96. [CAP_HCCPARAMS] = 0x08U,
  97. [CAP_DCCPARAMS] = 0x24U,
  98. [CAP_TESTMODE] = 0xFCU,
  99. [OP_USBCMD] = 0x00U,
  100. [OP_USBSTS] = 0x04U,
  101. [OP_USBINTR] = 0x08U,
  102. [OP_DEVICEADDR] = 0x14U,
  103. [OP_ENDPTLISTADDR] = 0x18U,
  104. [OP_TTCTRL] = 0x1CU,
  105. [OP_BURSTSIZE] = 0x20U,
  106. [OP_ULPI_VIEWPORT] = 0x30U,
  107. [OP_PORTSC] = 0x44U,
  108. [OP_DEVLC] = 0x84U,
  109. [OP_OTGSC] = 0xC4U,
  110. [OP_USBMODE] = 0xC8U,
  111. [OP_ENDPTSETUPSTAT] = 0xD8U,
  112. [OP_ENDPTPRIME] = 0xDCU,
  113. [OP_ENDPTFLUSH] = 0xE0U,
  114. [OP_ENDPTSTAT] = 0xE4U,
  115. [OP_ENDPTCOMPLETE] = 0xE8U,
  116. [OP_ENDPTCTRL] = 0xECU,
  117. };
  118. static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
  119. {
  120. int i;
  121. for (i = 0; i < OP_ENDPTCTRL; i++)
  122. ci->hw_bank.regmap[i] =
  123. (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
  124. (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
  125. for (; i <= OP_LAST; i++)
  126. ci->hw_bank.regmap[i] = ci->hw_bank.op +
  127. 4 * (i - OP_ENDPTCTRL) +
  128. (is_lpm
  129. ? ci_regs_lpm[OP_ENDPTCTRL]
  130. : ci_regs_nolpm[OP_ENDPTCTRL]);
  131. }
  132. static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
  133. {
  134. int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
  135. enum ci_revision rev = CI_REVISION_UNKNOWN;
  136. if (ver == 0x2) {
  137. rev = hw_read_id_reg(ci, ID_ID, REVISION)
  138. >> __ffs(REVISION);
  139. rev += CI_REVISION_20;
  140. } else if (ver == 0x0) {
  141. rev = CI_REVISION_1X;
  142. }
  143. return rev;
  144. }
  145. /**
  146. * hw_read_intr_enable: returns interrupt enable register
  147. *
  148. * @ci: the controller
  149. *
  150. * This function returns register data
  151. */
  152. u32 hw_read_intr_enable(struct ci_hdrc *ci)
  153. {
  154. return hw_read(ci, OP_USBINTR, ~0);
  155. }
  156. /**
  157. * hw_read_intr_status: returns interrupt status register
  158. *
  159. * @ci: the controller
  160. *
  161. * This function returns register data
  162. */
  163. u32 hw_read_intr_status(struct ci_hdrc *ci)
  164. {
  165. return hw_read(ci, OP_USBSTS, ~0);
  166. }
  167. /**
  168. * hw_port_test_set: writes port test mode (execute without interruption)
  169. * @mode: new value
  170. *
  171. * This function returns an error code
  172. */
  173. int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
  174. {
  175. const u8 TEST_MODE_MAX = 7;
  176. if (mode > TEST_MODE_MAX)
  177. return -EINVAL;
  178. hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
  179. return 0;
  180. }
  181. /**
  182. * hw_port_test_get: reads port test mode value
  183. *
  184. * @ci: the controller
  185. *
  186. * This function returns port test mode value
  187. */
  188. u8 hw_port_test_get(struct ci_hdrc *ci)
  189. {
  190. return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
  191. }
  192. static void hw_wait_phy_stable(void)
  193. {
  194. /*
  195. * The phy needs some delay to output the stable status from low
  196. * power mode. And for OTGSC, the status inputs are debounced
  197. * using a 1 ms time constant, so, delay 2ms for controller to get
  198. * the stable status, like vbus and id when the phy leaves low power.
  199. */
  200. usleep_range(2000, 2500);
  201. }
  202. /* The PHY enters/leaves low power mode */
  203. static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
  204. {
  205. enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
  206. bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
  207. if (enable && !lpm)
  208. hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
  209. PORTSC_PHCD(ci->hw_bank.lpm));
  210. else if (!enable && lpm)
  211. hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
  212. 0);
  213. }
  214. static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
  215. {
  216. u32 reg;
  217. /* bank is a module variable */
  218. ci->hw_bank.abs = base;
  219. ci->hw_bank.cap = ci->hw_bank.abs;
  220. ci->hw_bank.cap += ci->platdata->capoffset;
  221. ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
  222. hw_alloc_regmap(ci, false);
  223. reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
  224. __ffs(HCCPARAMS_LEN);
  225. ci->hw_bank.lpm = reg;
  226. if (reg)
  227. hw_alloc_regmap(ci, !!reg);
  228. ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
  229. ci->hw_bank.size += OP_LAST;
  230. ci->hw_bank.size /= sizeof(u32);
  231. reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
  232. __ffs(DCCPARAMS_DEN);
  233. ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  234. if (ci->hw_ep_max > ENDPT_MAX)
  235. return -ENODEV;
  236. ci_hdrc_enter_lpm(ci, false);
  237. /* Disable all interrupts bits */
  238. hw_write(ci, OP_USBINTR, 0xffffffff, 0);
  239. /* Clear all interrupts status bits*/
  240. hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
  241. ci->rev = ci_get_revision(ci);
  242. dev_dbg(ci->dev,
  243. "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
  244. ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
  245. /* setup lock mode ? */
  246. /* ENDPTSETUPSTAT is '0' by default */
  247. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  248. return 0;
  249. }
  250. void hw_phymode_configure(struct ci_hdrc *ci)
  251. {
  252. u32 portsc, lpm, sts = 0;
  253. switch (ci->platdata->phy_mode) {
  254. case USBPHY_INTERFACE_MODE_UTMI:
  255. portsc = PORTSC_PTS(PTS_UTMI);
  256. lpm = DEVLC_PTS(PTS_UTMI);
  257. break;
  258. case USBPHY_INTERFACE_MODE_UTMIW:
  259. portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
  260. lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
  261. break;
  262. case USBPHY_INTERFACE_MODE_ULPI:
  263. portsc = PORTSC_PTS(PTS_ULPI);
  264. lpm = DEVLC_PTS(PTS_ULPI);
  265. break;
  266. case USBPHY_INTERFACE_MODE_SERIAL:
  267. portsc = PORTSC_PTS(PTS_SERIAL);
  268. lpm = DEVLC_PTS(PTS_SERIAL);
  269. sts = 1;
  270. break;
  271. case USBPHY_INTERFACE_MODE_HSIC:
  272. portsc = PORTSC_PTS(PTS_HSIC);
  273. lpm = DEVLC_PTS(PTS_HSIC);
  274. break;
  275. default:
  276. return;
  277. }
  278. if (ci->hw_bank.lpm) {
  279. hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
  280. if (sts)
  281. hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
  282. } else {
  283. hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
  284. if (sts)
  285. hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
  286. }
  287. }
  288. EXPORT_SYMBOL_GPL(hw_phymode_configure);
  289. /**
  290. * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
  291. * interfaces
  292. * @ci: the controller
  293. *
  294. * This function returns an error code if the phy failed to init
  295. */
  296. static int _ci_usb_phy_init(struct ci_hdrc *ci)
  297. {
  298. int ret;
  299. if (ci->phy) {
  300. ret = phy_init(ci->phy);
  301. if (ret)
  302. return ret;
  303. ret = phy_power_on(ci->phy);
  304. if (ret) {
  305. phy_exit(ci->phy);
  306. return ret;
  307. }
  308. } else {
  309. ret = usb_phy_init(ci->usb_phy);
  310. }
  311. return ret;
  312. }
  313. /**
  314. * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
  315. * interfaces
  316. * @ci: the controller
  317. */
  318. static void ci_usb_phy_exit(struct ci_hdrc *ci)
  319. {
  320. if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
  321. return;
  322. if (ci->phy) {
  323. phy_power_off(ci->phy);
  324. phy_exit(ci->phy);
  325. } else {
  326. usb_phy_shutdown(ci->usb_phy);
  327. }
  328. }
  329. /**
  330. * ci_usb_phy_init: initialize phy according to different phy type
  331. * @ci: the controller
  332. *
  333. * This function returns an error code if usb_phy_init has failed
  334. */
  335. static int ci_usb_phy_init(struct ci_hdrc *ci)
  336. {
  337. int ret;
  338. if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
  339. return 0;
  340. switch (ci->platdata->phy_mode) {
  341. case USBPHY_INTERFACE_MODE_UTMI:
  342. case USBPHY_INTERFACE_MODE_UTMIW:
  343. case USBPHY_INTERFACE_MODE_HSIC:
  344. ret = _ci_usb_phy_init(ci);
  345. if (!ret)
  346. hw_wait_phy_stable();
  347. else
  348. return ret;
  349. hw_phymode_configure(ci);
  350. break;
  351. case USBPHY_INTERFACE_MODE_ULPI:
  352. case USBPHY_INTERFACE_MODE_SERIAL:
  353. hw_phymode_configure(ci);
  354. ret = _ci_usb_phy_init(ci);
  355. if (ret)
  356. return ret;
  357. break;
  358. default:
  359. ret = _ci_usb_phy_init(ci);
  360. if (!ret)
  361. hw_wait_phy_stable();
  362. }
  363. return ret;
  364. }
  365. /**
  366. * ci_platform_configure: do controller configure
  367. * @ci: the controller
  368. *
  369. */
  370. void ci_platform_configure(struct ci_hdrc *ci)
  371. {
  372. bool is_device_mode, is_host_mode;
  373. is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
  374. is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
  375. if (is_device_mode) {
  376. phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
  377. if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
  378. hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
  379. USBMODE_CI_SDIS);
  380. }
  381. if (is_host_mode) {
  382. phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
  383. if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
  384. hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
  385. USBMODE_CI_SDIS);
  386. }
  387. if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
  388. if (ci->hw_bank.lpm)
  389. hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
  390. else
  391. hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
  392. }
  393. if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
  394. hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
  395. hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
  396. if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
  397. hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
  398. ci->platdata->ahb_burst_config);
  399. /* override burst size, take effect only when ahb_burst_config is 0 */
  400. if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
  401. if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
  402. hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
  403. ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
  404. if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
  405. hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
  406. ci->platdata->rx_burst_size);
  407. }
  408. }
  409. /**
  410. * hw_controller_reset: do controller reset
  411. * @ci: the controller
  412. *
  413. * This function returns an error code
  414. */
  415. static int hw_controller_reset(struct ci_hdrc *ci)
  416. {
  417. int count = 0;
  418. hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
  419. while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
  420. udelay(10);
  421. if (count++ > 1000)
  422. return -ETIMEDOUT;
  423. }
  424. return 0;
  425. }
  426. /**
  427. * hw_device_reset: resets chip (execute without interruption)
  428. * @ci: the controller
  429. *
  430. * This function returns an error code
  431. */
  432. int hw_device_reset(struct ci_hdrc *ci)
  433. {
  434. int ret;
  435. /* should flush & stop before reset */
  436. hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
  437. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  438. ret = hw_controller_reset(ci);
  439. if (ret) {
  440. dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
  441. return ret;
  442. }
  443. if (ci->platdata->notify_event) {
  444. ret = ci->platdata->notify_event(ci,
  445. CI_HDRC_CONTROLLER_RESET_EVENT);
  446. if (ret)
  447. return ret;
  448. }
  449. /* USBMODE should be configured step by step */
  450. hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  451. hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
  452. /* HW >= 2.3 */
  453. hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
  454. if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
  455. pr_err("cannot enter in %s device mode", ci_role(ci)->name);
  456. pr_err("lpm = %i", ci->hw_bank.lpm);
  457. return -ENODEV;
  458. }
  459. ci_platform_configure(ci);
  460. return 0;
  461. }
  462. static irqreturn_t ci_irq(int irq, void *data)
  463. {
  464. struct ci_hdrc *ci = data;
  465. irqreturn_t ret = IRQ_NONE;
  466. u32 otgsc = 0;
  467. if (ci->in_lpm) {
  468. disable_irq_nosync(irq);
  469. ci->wakeup_int = true;
  470. pm_runtime_get(ci->dev);
  471. return IRQ_HANDLED;
  472. }
  473. if (ci->is_otg) {
  474. otgsc = hw_read_otgsc(ci, ~0);
  475. if (ci_otg_is_fsm_mode(ci)) {
  476. ret = ci_otg_fsm_irq(ci);
  477. if (ret == IRQ_HANDLED)
  478. return ret;
  479. }
  480. }
  481. /*
  482. * Handle id change interrupt, it indicates device/host function
  483. * switch.
  484. */
  485. if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
  486. ci->id_event = true;
  487. /* Clear ID change irq status */
  488. hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
  489. ci_otg_queue_work(ci);
  490. return IRQ_HANDLED;
  491. }
  492. /*
  493. * Handle vbus change interrupt, it indicates device connection
  494. * and disconnection events.
  495. */
  496. if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
  497. ci->b_sess_valid_event = true;
  498. /* Clear BSV irq */
  499. hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
  500. ci_otg_queue_work(ci);
  501. return IRQ_HANDLED;
  502. }
  503. /* Handle device/host interrupt */
  504. if (ci->role != CI_ROLE_END)
  505. ret = ci_role(ci)->irq(ci);
  506. return ret;
  507. }
  508. static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
  509. void *ptr)
  510. {
  511. struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
  512. struct ci_hdrc *ci = cbl->ci;
  513. cbl->connected = event;
  514. cbl->changed = true;
  515. ci_irq(ci->irq, ci);
  516. return NOTIFY_DONE;
  517. }
  518. static int ci_get_platdata(struct device *dev,
  519. struct ci_hdrc_platform_data *platdata)
  520. {
  521. struct extcon_dev *ext_vbus, *ext_id;
  522. struct ci_hdrc_cable *cable;
  523. int ret;
  524. if (!platdata->phy_mode)
  525. platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
  526. if (!platdata->dr_mode)
  527. platdata->dr_mode = usb_get_dr_mode(dev);
  528. if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
  529. platdata->dr_mode = USB_DR_MODE_OTG;
  530. if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
  531. /* Get the vbus regulator */
  532. platdata->reg_vbus = devm_regulator_get(dev, "vbus");
  533. if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
  534. return -EPROBE_DEFER;
  535. } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
  536. /* no vbus regulator is needed */
  537. platdata->reg_vbus = NULL;
  538. } else if (IS_ERR(platdata->reg_vbus)) {
  539. dev_err(dev, "Getting regulator error: %ld\n",
  540. PTR_ERR(platdata->reg_vbus));
  541. return PTR_ERR(platdata->reg_vbus);
  542. }
  543. /* Get TPL support */
  544. if (!platdata->tpl_support)
  545. platdata->tpl_support =
  546. of_usb_host_tpl_support(dev->of_node);
  547. }
  548. if (platdata->dr_mode == USB_DR_MODE_OTG) {
  549. /* We can support HNP and SRP of OTG 2.0 */
  550. platdata->ci_otg_caps.otg_rev = 0x0200;
  551. platdata->ci_otg_caps.hnp_support = true;
  552. platdata->ci_otg_caps.srp_support = true;
  553. /* Update otg capabilities by DT properties */
  554. ret = of_usb_update_otg_caps(dev->of_node,
  555. &platdata->ci_otg_caps);
  556. if (ret)
  557. return ret;
  558. }
  559. if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
  560. platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
  561. of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
  562. &platdata->phy_clkgate_delay_us);
  563. platdata->itc_setting = 1;
  564. of_property_read_u32(dev->of_node, "itc-setting",
  565. &platdata->itc_setting);
  566. ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
  567. &platdata->ahb_burst_config);
  568. if (!ret) {
  569. platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
  570. } else if (ret != -EINVAL) {
  571. dev_err(dev, "failed to get ahb-burst-config\n");
  572. return ret;
  573. }
  574. ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
  575. &platdata->tx_burst_size);
  576. if (!ret) {
  577. platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
  578. } else if (ret != -EINVAL) {
  579. dev_err(dev, "failed to get tx-burst-size-dword\n");
  580. return ret;
  581. }
  582. ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
  583. &platdata->rx_burst_size);
  584. if (!ret) {
  585. platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
  586. } else if (ret != -EINVAL) {
  587. dev_err(dev, "failed to get rx-burst-size-dword\n");
  588. return ret;
  589. }
  590. if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
  591. platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
  592. ext_id = ERR_PTR(-ENODEV);
  593. ext_vbus = ERR_PTR(-ENODEV);
  594. if (of_property_read_bool(dev->of_node, "extcon")) {
  595. /* Each one of them is not mandatory */
  596. ext_vbus = extcon_get_edev_by_phandle(dev, 0);
  597. if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
  598. return PTR_ERR(ext_vbus);
  599. ext_id = extcon_get_edev_by_phandle(dev, 1);
  600. if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
  601. return PTR_ERR(ext_id);
  602. }
  603. cable = &platdata->vbus_extcon;
  604. cable->nb.notifier_call = ci_cable_notifier;
  605. cable->edev = ext_vbus;
  606. if (!IS_ERR(ext_vbus)) {
  607. ret = extcon_get_state(cable->edev, EXTCON_USB);
  608. if (ret)
  609. cable->connected = true;
  610. else
  611. cable->connected = false;
  612. }
  613. cable = &platdata->id_extcon;
  614. cable->nb.notifier_call = ci_cable_notifier;
  615. cable->edev = ext_id;
  616. if (!IS_ERR(ext_id)) {
  617. ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
  618. if (ret)
  619. cable->connected = true;
  620. else
  621. cable->connected = false;
  622. }
  623. return 0;
  624. }
  625. static int ci_extcon_register(struct ci_hdrc *ci)
  626. {
  627. struct ci_hdrc_cable *id, *vbus;
  628. int ret;
  629. id = &ci->platdata->id_extcon;
  630. id->ci = ci;
  631. if (!IS_ERR_OR_NULL(id->edev)) {
  632. ret = devm_extcon_register_notifier(ci->dev, id->edev,
  633. EXTCON_USB_HOST, &id->nb);
  634. if (ret < 0) {
  635. dev_err(ci->dev, "register ID failed\n");
  636. return ret;
  637. }
  638. }
  639. vbus = &ci->platdata->vbus_extcon;
  640. vbus->ci = ci;
  641. if (!IS_ERR_OR_NULL(vbus->edev)) {
  642. ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
  643. EXTCON_USB, &vbus->nb);
  644. if (ret < 0) {
  645. dev_err(ci->dev, "register VBUS failed\n");
  646. return ret;
  647. }
  648. }
  649. return 0;
  650. }
  651. static DEFINE_IDA(ci_ida);
  652. struct platform_device *ci_hdrc_add_device(struct device *dev,
  653. struct resource *res, int nres,
  654. struct ci_hdrc_platform_data *platdata)
  655. {
  656. struct platform_device *pdev;
  657. int id, ret;
  658. ret = ci_get_platdata(dev, platdata);
  659. if (ret)
  660. return ERR_PTR(ret);
  661. id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
  662. if (id < 0)
  663. return ERR_PTR(id);
  664. pdev = platform_device_alloc("ci_hdrc", id);
  665. if (!pdev) {
  666. ret = -ENOMEM;
  667. goto put_id;
  668. }
  669. pdev->dev.parent = dev;
  670. ret = platform_device_add_resources(pdev, res, nres);
  671. if (ret)
  672. goto err;
  673. ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
  674. if (ret)
  675. goto err;
  676. ret = platform_device_add(pdev);
  677. if (ret)
  678. goto err;
  679. return pdev;
  680. err:
  681. platform_device_put(pdev);
  682. put_id:
  683. ida_simple_remove(&ci_ida, id);
  684. return ERR_PTR(ret);
  685. }
  686. EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
  687. void ci_hdrc_remove_device(struct platform_device *pdev)
  688. {
  689. int id = pdev->id;
  690. platform_device_unregister(pdev);
  691. ida_simple_remove(&ci_ida, id);
  692. }
  693. EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
  694. static inline void ci_role_destroy(struct ci_hdrc *ci)
  695. {
  696. ci_hdrc_gadget_destroy(ci);
  697. ci_hdrc_host_destroy(ci);
  698. if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
  699. ci_hdrc_otg_destroy(ci);
  700. }
  701. static void ci_get_otg_capable(struct ci_hdrc *ci)
  702. {
  703. if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
  704. ci->is_otg = false;
  705. else
  706. ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
  707. DCCPARAMS_DC | DCCPARAMS_HC)
  708. == (DCCPARAMS_DC | DCCPARAMS_HC));
  709. if (ci->is_otg) {
  710. dev_dbg(ci->dev, "It is OTG capable controller\n");
  711. /* Disable and clear all OTG irq */
  712. hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
  713. OTGSC_INT_STATUS_BITS);
  714. }
  715. }
  716. static ssize_t role_show(struct device *dev, struct device_attribute *attr,
  717. char *buf)
  718. {
  719. struct ci_hdrc *ci = dev_get_drvdata(dev);
  720. if (ci->role != CI_ROLE_END)
  721. return sprintf(buf, "%s\n", ci_role(ci)->name);
  722. return 0;
  723. }
  724. static ssize_t role_store(struct device *dev,
  725. struct device_attribute *attr, const char *buf, size_t n)
  726. {
  727. struct ci_hdrc *ci = dev_get_drvdata(dev);
  728. enum ci_role role;
  729. int ret;
  730. if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
  731. dev_warn(dev, "Current configuration is not dual-role, quit\n");
  732. return -EPERM;
  733. }
  734. for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
  735. if (!strncmp(buf, ci->roles[role]->name,
  736. strlen(ci->roles[role]->name)))
  737. break;
  738. if (role == CI_ROLE_END || role == ci->role)
  739. return -EINVAL;
  740. pm_runtime_get_sync(dev);
  741. disable_irq(ci->irq);
  742. ci_role_stop(ci);
  743. ret = ci_role_start(ci, role);
  744. if (!ret && ci->role == CI_ROLE_GADGET)
  745. ci_handle_vbus_change(ci);
  746. enable_irq(ci->irq);
  747. pm_runtime_put_sync(dev);
  748. return (ret == 0) ? n : ret;
  749. }
  750. static DEVICE_ATTR_RW(role);
  751. static struct attribute *ci_attrs[] = {
  752. &dev_attr_role.attr,
  753. NULL,
  754. };
  755. static const struct attribute_group ci_attr_group = {
  756. .attrs = ci_attrs,
  757. };
  758. static int ci_hdrc_probe(struct platform_device *pdev)
  759. {
  760. struct device *dev = &pdev->dev;
  761. struct ci_hdrc *ci;
  762. struct resource *res;
  763. void __iomem *base;
  764. int ret;
  765. enum usb_dr_mode dr_mode;
  766. if (!dev_get_platdata(dev)) {
  767. dev_err(dev, "platform data missing\n");
  768. return -ENODEV;
  769. }
  770. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  771. base = devm_ioremap_resource(dev, res);
  772. if (IS_ERR(base))
  773. return PTR_ERR(base);
  774. ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
  775. if (!ci)
  776. return -ENOMEM;
  777. spin_lock_init(&ci->lock);
  778. ci->dev = dev;
  779. ci->platdata = dev_get_platdata(dev);
  780. ci->imx28_write_fix = !!(ci->platdata->flags &
  781. CI_HDRC_IMX28_WRITE_FIX);
  782. ci->supports_runtime_pm = !!(ci->platdata->flags &
  783. CI_HDRC_SUPPORTS_RUNTIME_PM);
  784. platform_set_drvdata(pdev, ci);
  785. ret = hw_device_init(ci, base);
  786. if (ret < 0) {
  787. dev_err(dev, "can't initialize hardware\n");
  788. return -ENODEV;
  789. }
  790. ret = ci_ulpi_init(ci);
  791. if (ret)
  792. return ret;
  793. if (ci->platdata->phy) {
  794. ci->phy = ci->platdata->phy;
  795. } else if (ci->platdata->usb_phy) {
  796. ci->usb_phy = ci->platdata->usb_phy;
  797. } else {
  798. ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent, "phys",
  799. 0);
  800. ci->phy = devm_phy_get(dev->parent, "usb-phy");
  801. /* Fallback to grabbing any registered USB2 PHY */
  802. if (IS_ERR(ci->usb_phy) &&
  803. PTR_ERR(ci->usb_phy) != -EPROBE_DEFER)
  804. ci->usb_phy = devm_usb_get_phy(dev->parent,
  805. USB_PHY_TYPE_USB2);
  806. /* if both generic PHY and USB PHY layers aren't enabled */
  807. if (PTR_ERR(ci->phy) == -ENOSYS &&
  808. PTR_ERR(ci->usb_phy) == -ENXIO) {
  809. ret = -ENXIO;
  810. goto ulpi_exit;
  811. }
  812. if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) {
  813. ret = -EPROBE_DEFER;
  814. goto ulpi_exit;
  815. }
  816. if (IS_ERR(ci->phy))
  817. ci->phy = NULL;
  818. else if (IS_ERR(ci->usb_phy))
  819. ci->usb_phy = NULL;
  820. }
  821. ret = ci_usb_phy_init(ci);
  822. if (ret) {
  823. dev_err(dev, "unable to init phy: %d\n", ret);
  824. return ret;
  825. }
  826. ci->hw_bank.phys = res->start;
  827. ci->irq = platform_get_irq(pdev, 0);
  828. if (ci->irq < 0) {
  829. dev_err(dev, "missing IRQ\n");
  830. ret = ci->irq;
  831. goto deinit_phy;
  832. }
  833. ci_get_otg_capable(ci);
  834. dr_mode = ci->platdata->dr_mode;
  835. /* initialize role(s) before the interrupt is requested */
  836. if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
  837. ret = ci_hdrc_host_init(ci);
  838. if (ret) {
  839. if (ret == -ENXIO)
  840. dev_info(dev, "doesn't support host\n");
  841. else
  842. goto deinit_phy;
  843. }
  844. }
  845. if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
  846. ret = ci_hdrc_gadget_init(ci);
  847. if (ret) {
  848. if (ret == -ENXIO)
  849. dev_info(dev, "doesn't support gadget\n");
  850. else
  851. goto deinit_host;
  852. }
  853. }
  854. if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
  855. dev_err(dev, "no supported roles\n");
  856. ret = -ENODEV;
  857. goto deinit_gadget;
  858. }
  859. if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
  860. ret = ci_hdrc_otg_init(ci);
  861. if (ret) {
  862. dev_err(dev, "init otg fails, ret = %d\n", ret);
  863. goto deinit_gadget;
  864. }
  865. }
  866. if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
  867. if (ci->is_otg) {
  868. ci->role = ci_otg_role(ci);
  869. /* Enable ID change irq */
  870. hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
  871. } else {
  872. /*
  873. * If the controller is not OTG capable, but support
  874. * role switch, the defalt role is gadget, and the
  875. * user can switch it through debugfs.
  876. */
  877. ci->role = CI_ROLE_GADGET;
  878. }
  879. } else {
  880. ci->role = ci->roles[CI_ROLE_HOST]
  881. ? CI_ROLE_HOST
  882. : CI_ROLE_GADGET;
  883. }
  884. if (!ci_otg_is_fsm_mode(ci)) {
  885. /* only update vbus status for peripheral */
  886. if (ci->role == CI_ROLE_GADGET)
  887. ci_handle_vbus_change(ci);
  888. ret = ci_role_start(ci, ci->role);
  889. if (ret) {
  890. dev_err(dev, "can't start %s role\n",
  891. ci_role(ci)->name);
  892. goto stop;
  893. }
  894. }
  895. ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
  896. ci->platdata->name, ci);
  897. if (ret)
  898. goto stop;
  899. ret = ci_extcon_register(ci);
  900. if (ret)
  901. goto stop;
  902. if (ci->supports_runtime_pm) {
  903. pm_runtime_set_active(&pdev->dev);
  904. pm_runtime_enable(&pdev->dev);
  905. pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
  906. pm_runtime_mark_last_busy(ci->dev);
  907. pm_runtime_use_autosuspend(&pdev->dev);
  908. }
  909. if (ci_otg_is_fsm_mode(ci))
  910. ci_hdrc_otg_fsm_start(ci);
  911. device_set_wakeup_capable(&pdev->dev, true);
  912. dbg_create_files(ci);
  913. ret = sysfs_create_group(&dev->kobj, &ci_attr_group);
  914. if (ret)
  915. goto remove_debug;
  916. return 0;
  917. remove_debug:
  918. dbg_remove_files(ci);
  919. stop:
  920. if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
  921. ci_hdrc_otg_destroy(ci);
  922. deinit_gadget:
  923. ci_hdrc_gadget_destroy(ci);
  924. deinit_host:
  925. ci_hdrc_host_destroy(ci);
  926. deinit_phy:
  927. ci_usb_phy_exit(ci);
  928. ulpi_exit:
  929. ci_ulpi_exit(ci);
  930. return ret;
  931. }
  932. static int ci_hdrc_remove(struct platform_device *pdev)
  933. {
  934. struct ci_hdrc *ci = platform_get_drvdata(pdev);
  935. if (ci->supports_runtime_pm) {
  936. pm_runtime_get_sync(&pdev->dev);
  937. pm_runtime_disable(&pdev->dev);
  938. pm_runtime_put_noidle(&pdev->dev);
  939. }
  940. dbg_remove_files(ci);
  941. sysfs_remove_group(&ci->dev->kobj, &ci_attr_group);
  942. ci_role_destroy(ci);
  943. ci_hdrc_enter_lpm(ci, true);
  944. ci_usb_phy_exit(ci);
  945. ci_ulpi_exit(ci);
  946. return 0;
  947. }
  948. #ifdef CONFIG_PM
  949. /* Prepare wakeup by SRP before suspend */
  950. static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
  951. {
  952. if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
  953. !hw_read_otgsc(ci, OTGSC_ID)) {
  954. hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
  955. PORTSC_PP);
  956. hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
  957. PORTSC_WKCN);
  958. }
  959. }
  960. /* Handle SRP when wakeup by data pulse */
  961. static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
  962. {
  963. if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
  964. (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
  965. if (!hw_read_otgsc(ci, OTGSC_ID)) {
  966. ci->fsm.a_srp_det = 1;
  967. ci->fsm.a_bus_drop = 0;
  968. } else {
  969. ci->fsm.id = 1;
  970. }
  971. ci_otg_queue_work(ci);
  972. }
  973. }
  974. static void ci_controller_suspend(struct ci_hdrc *ci)
  975. {
  976. disable_irq(ci->irq);
  977. ci_hdrc_enter_lpm(ci, true);
  978. if (ci->platdata->phy_clkgate_delay_us)
  979. usleep_range(ci->platdata->phy_clkgate_delay_us,
  980. ci->platdata->phy_clkgate_delay_us + 50);
  981. usb_phy_set_suspend(ci->usb_phy, 1);
  982. ci->in_lpm = true;
  983. enable_irq(ci->irq);
  984. }
  985. /*
  986. * Handle the wakeup interrupt triggered by extcon connector
  987. * We need to call ci_irq again for extcon since the first
  988. * interrupt (wakeup int) only let the controller be out of
  989. * low power mode, but not handle any interrupts.
  990. */
  991. static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
  992. {
  993. struct ci_hdrc_cable *cable_id, *cable_vbus;
  994. u32 otgsc = hw_read_otgsc(ci, ~0);
  995. cable_id = &ci->platdata->id_extcon;
  996. cable_vbus = &ci->platdata->vbus_extcon;
  997. if (!IS_ERR(cable_id->edev) && ci->is_otg &&
  998. (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
  999. ci_irq(ci->irq, ci);
  1000. if (!IS_ERR(cable_vbus->edev) && ci->is_otg &&
  1001. (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
  1002. ci_irq(ci->irq, ci);
  1003. }
  1004. static int ci_controller_resume(struct device *dev)
  1005. {
  1006. struct ci_hdrc *ci = dev_get_drvdata(dev);
  1007. int ret;
  1008. dev_dbg(dev, "at %s\n", __func__);
  1009. if (!ci->in_lpm) {
  1010. WARN_ON(1);
  1011. return 0;
  1012. }
  1013. ci_hdrc_enter_lpm(ci, false);
  1014. ret = ci_ulpi_resume(ci);
  1015. if (ret)
  1016. return ret;
  1017. if (ci->usb_phy) {
  1018. usb_phy_set_suspend(ci->usb_phy, 0);
  1019. usb_phy_set_wakeup(ci->usb_phy, false);
  1020. hw_wait_phy_stable();
  1021. }
  1022. ci->in_lpm = false;
  1023. if (ci->wakeup_int) {
  1024. ci->wakeup_int = false;
  1025. pm_runtime_mark_last_busy(ci->dev);
  1026. pm_runtime_put_autosuspend(ci->dev);
  1027. enable_irq(ci->irq);
  1028. if (ci_otg_is_fsm_mode(ci))
  1029. ci_otg_fsm_wakeup_by_srp(ci);
  1030. ci_extcon_wakeup_int(ci);
  1031. }
  1032. return 0;
  1033. }
  1034. #ifdef CONFIG_PM_SLEEP
  1035. static int ci_suspend(struct device *dev)
  1036. {
  1037. struct ci_hdrc *ci = dev_get_drvdata(dev);
  1038. if (ci->wq)
  1039. flush_workqueue(ci->wq);
  1040. /*
  1041. * Controller needs to be active during suspend, otherwise the core
  1042. * may run resume when the parent is at suspend if other driver's
  1043. * suspend fails, it occurs before parent's suspend has not started,
  1044. * but the core suspend has finished.
  1045. */
  1046. if (ci->in_lpm)
  1047. pm_runtime_resume(dev);
  1048. if (ci->in_lpm) {
  1049. WARN_ON(1);
  1050. return 0;
  1051. }
  1052. if (device_may_wakeup(dev)) {
  1053. if (ci_otg_is_fsm_mode(ci))
  1054. ci_otg_fsm_suspend_for_srp(ci);
  1055. usb_phy_set_wakeup(ci->usb_phy, true);
  1056. enable_irq_wake(ci->irq);
  1057. }
  1058. ci_controller_suspend(ci);
  1059. return 0;
  1060. }
  1061. static int ci_resume(struct device *dev)
  1062. {
  1063. struct ci_hdrc *ci = dev_get_drvdata(dev);
  1064. int ret;
  1065. if (device_may_wakeup(dev))
  1066. disable_irq_wake(ci->irq);
  1067. ret = ci_controller_resume(dev);
  1068. if (ret)
  1069. return ret;
  1070. if (ci->supports_runtime_pm) {
  1071. pm_runtime_disable(dev);
  1072. pm_runtime_set_active(dev);
  1073. pm_runtime_enable(dev);
  1074. }
  1075. return ret;
  1076. }
  1077. #endif /* CONFIG_PM_SLEEP */
  1078. static int ci_runtime_suspend(struct device *dev)
  1079. {
  1080. struct ci_hdrc *ci = dev_get_drvdata(dev);
  1081. dev_dbg(dev, "at %s\n", __func__);
  1082. if (ci->in_lpm) {
  1083. WARN_ON(1);
  1084. return 0;
  1085. }
  1086. if (ci_otg_is_fsm_mode(ci))
  1087. ci_otg_fsm_suspend_for_srp(ci);
  1088. usb_phy_set_wakeup(ci->usb_phy, true);
  1089. ci_controller_suspend(ci);
  1090. return 0;
  1091. }
  1092. static int ci_runtime_resume(struct device *dev)
  1093. {
  1094. return ci_controller_resume(dev);
  1095. }
  1096. #endif /* CONFIG_PM */
  1097. static const struct dev_pm_ops ci_pm_ops = {
  1098. SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
  1099. SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
  1100. };
  1101. static struct platform_driver ci_hdrc_driver = {
  1102. .probe = ci_hdrc_probe,
  1103. .remove = ci_hdrc_remove,
  1104. .driver = {
  1105. .name = "ci_hdrc",
  1106. .pm = &ci_pm_ops,
  1107. },
  1108. };
  1109. static int __init ci_hdrc_platform_register(void)
  1110. {
  1111. ci_hdrc_host_driver_init();
  1112. return platform_driver_register(&ci_hdrc_driver);
  1113. }
  1114. module_init(ci_hdrc_platform_register);
  1115. static void __exit ci_hdrc_platform_unregister(void)
  1116. {
  1117. platform_driver_unregister(&ci_hdrc_driver);
  1118. }
  1119. module_exit(ci_hdrc_platform_unregister);
  1120. MODULE_ALIAS("platform:ci_hdrc");
  1121. MODULE_LICENSE("GPL v2");
  1122. MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
  1123. MODULE_DESCRIPTION("ChipIdea HDRC Driver");