tascam-stream.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508
  1. /*
  2. * tascam-stream.c - a part of driver for TASCAM FireWire series
  3. *
  4. * Copyright (c) 2015 Takashi Sakamoto
  5. *
  6. * Licensed under the terms of the GNU General Public License, version 2.
  7. */
  8. #include <linux/delay.h>
  9. #include "tascam.h"
  10. #define CLOCK_STATUS_MASK 0xffff0000
  11. #define CLOCK_CONFIG_MASK 0x0000ffff
  12. #define CALLBACK_TIMEOUT 500
  13. static int get_clock(struct snd_tscm *tscm, u32 *data)
  14. {
  15. int trial = 0;
  16. __be32 reg;
  17. int err;
  18. while (trial++ < 5) {
  19. err = snd_fw_transaction(tscm->unit, TCODE_READ_QUADLET_REQUEST,
  20. TSCM_ADDR_BASE + TSCM_OFFSET_CLOCK_STATUS,
  21. &reg, sizeof(reg), 0);
  22. if (err < 0)
  23. return err;
  24. *data = be32_to_cpu(reg);
  25. if (*data & CLOCK_STATUS_MASK)
  26. break;
  27. // In intermediate state after changing clock status.
  28. msleep(50);
  29. }
  30. // Still in the intermediate state.
  31. if (trial >= 5)
  32. return -EAGAIN;
  33. return 0;
  34. }
  35. static int set_clock(struct snd_tscm *tscm, unsigned int rate,
  36. enum snd_tscm_clock clock)
  37. {
  38. u32 data;
  39. __be32 reg;
  40. int err;
  41. err = get_clock(tscm, &data);
  42. if (err < 0)
  43. return err;
  44. data &= CLOCK_CONFIG_MASK;
  45. if (rate > 0) {
  46. data &= 0x000000ff;
  47. /* Base rate. */
  48. if ((rate % 44100) == 0) {
  49. data |= 0x00000100;
  50. /* Multiplier. */
  51. if (rate / 44100 == 2)
  52. data |= 0x00008000;
  53. } else if ((rate % 48000) == 0) {
  54. data |= 0x00000200;
  55. /* Multiplier. */
  56. if (rate / 48000 == 2)
  57. data |= 0x00008000;
  58. } else {
  59. return -EAGAIN;
  60. }
  61. }
  62. if (clock != INT_MAX) {
  63. data &= 0x0000ff00;
  64. data |= clock + 1;
  65. }
  66. reg = cpu_to_be32(data);
  67. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  68. TSCM_ADDR_BASE + TSCM_OFFSET_CLOCK_STATUS,
  69. &reg, sizeof(reg), 0);
  70. if (err < 0)
  71. return err;
  72. if (data & 0x00008000)
  73. reg = cpu_to_be32(0x0000001a);
  74. else
  75. reg = cpu_to_be32(0x0000000d);
  76. return snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  77. TSCM_ADDR_BASE + TSCM_OFFSET_MULTIPLEX_MODE,
  78. &reg, sizeof(reg), 0);
  79. }
  80. int snd_tscm_stream_get_rate(struct snd_tscm *tscm, unsigned int *rate)
  81. {
  82. u32 data;
  83. int err;
  84. err = get_clock(tscm, &data);
  85. if (err < 0)
  86. return err;
  87. data = (data & 0xff000000) >> 24;
  88. /* Check base rate. */
  89. if ((data & 0x0f) == 0x01)
  90. *rate = 44100;
  91. else if ((data & 0x0f) == 0x02)
  92. *rate = 48000;
  93. else
  94. return -EAGAIN;
  95. /* Check multiplier. */
  96. if ((data & 0xf0) == 0x80)
  97. *rate *= 2;
  98. else if ((data & 0xf0) != 0x00)
  99. return -EAGAIN;
  100. return err;
  101. }
  102. int snd_tscm_stream_get_clock(struct snd_tscm *tscm, enum snd_tscm_clock *clock)
  103. {
  104. u32 data;
  105. int err;
  106. err = get_clock(tscm, &data);
  107. if (err < 0)
  108. return err;
  109. *clock = ((data & 0x00ff0000) >> 16) - 1;
  110. if (*clock < 0 || *clock > SND_TSCM_CLOCK_ADAT)
  111. return -EIO;
  112. return 0;
  113. }
  114. static int enable_data_channels(struct snd_tscm *tscm)
  115. {
  116. __be32 reg;
  117. u32 data;
  118. unsigned int i;
  119. int err;
  120. data = 0;
  121. for (i = 0; i < tscm->spec->pcm_capture_analog_channels; ++i)
  122. data |= BIT(i);
  123. if (tscm->spec->has_adat)
  124. data |= 0x0000ff00;
  125. if (tscm->spec->has_spdif)
  126. data |= 0x00030000;
  127. reg = cpu_to_be32(data);
  128. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  129. TSCM_ADDR_BASE + TSCM_OFFSET_TX_PCM_CHANNELS,
  130. &reg, sizeof(reg), 0);
  131. if (err < 0)
  132. return err;
  133. data = 0;
  134. for (i = 0; i < tscm->spec->pcm_playback_analog_channels; ++i)
  135. data |= BIT(i);
  136. if (tscm->spec->has_adat)
  137. data |= 0x0000ff00;
  138. if (tscm->spec->has_spdif)
  139. data |= 0x00030000;
  140. reg = cpu_to_be32(data);
  141. return snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  142. TSCM_ADDR_BASE + TSCM_OFFSET_RX_PCM_CHANNELS,
  143. &reg, sizeof(reg), 0);
  144. }
  145. static int set_stream_formats(struct snd_tscm *tscm, unsigned int rate)
  146. {
  147. __be32 reg;
  148. int err;
  149. /* Set an option for unknown purpose. */
  150. reg = cpu_to_be32(0x00200000);
  151. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  152. TSCM_ADDR_BASE + TSCM_OFFSET_SET_OPTION,
  153. &reg, sizeof(reg), 0);
  154. if (err < 0)
  155. return err;
  156. err = enable_data_channels(tscm);
  157. if (err < 0)
  158. return err;
  159. return set_clock(tscm, rate, INT_MAX);
  160. }
  161. static void finish_session(struct snd_tscm *tscm)
  162. {
  163. __be32 reg;
  164. reg = 0;
  165. snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  166. TSCM_ADDR_BASE + TSCM_OFFSET_START_STREAMING,
  167. &reg, sizeof(reg), 0);
  168. reg = 0;
  169. snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  170. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_ON,
  171. &reg, sizeof(reg), 0);
  172. }
  173. static int begin_session(struct snd_tscm *tscm)
  174. {
  175. __be32 reg;
  176. int err;
  177. reg = cpu_to_be32(0x00000001);
  178. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  179. TSCM_ADDR_BASE + TSCM_OFFSET_START_STREAMING,
  180. &reg, sizeof(reg), 0);
  181. if (err < 0)
  182. return err;
  183. reg = cpu_to_be32(0x00000001);
  184. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  185. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_ON,
  186. &reg, sizeof(reg), 0);
  187. if (err < 0)
  188. return err;
  189. /* Set an option for unknown purpose. */
  190. reg = cpu_to_be32(0x00002000);
  191. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  192. TSCM_ADDR_BASE + TSCM_OFFSET_SET_OPTION,
  193. &reg, sizeof(reg), 0);
  194. if (err < 0)
  195. return err;
  196. /* Start multiplexing PCM samples on packets. */
  197. reg = cpu_to_be32(0x00000001);
  198. return snd_fw_transaction(tscm->unit,
  199. TCODE_WRITE_QUADLET_REQUEST,
  200. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_ON,
  201. &reg, sizeof(reg), 0);
  202. }
  203. static void release_resources(struct snd_tscm *tscm)
  204. {
  205. __be32 reg;
  206. /* Unregister channels. */
  207. reg = cpu_to_be32(0x00000000);
  208. snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  209. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_CH,
  210. &reg, sizeof(reg), 0);
  211. reg = cpu_to_be32(0x00000000);
  212. snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  213. TSCM_ADDR_BASE + TSCM_OFFSET_UNKNOWN,
  214. &reg, sizeof(reg), 0);
  215. reg = cpu_to_be32(0x00000000);
  216. snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  217. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_CH,
  218. &reg, sizeof(reg), 0);
  219. /* Release isochronous resources. */
  220. fw_iso_resources_free(&tscm->tx_resources);
  221. fw_iso_resources_free(&tscm->rx_resources);
  222. }
  223. static int keep_resources(struct snd_tscm *tscm, unsigned int rate)
  224. {
  225. __be32 reg;
  226. int err;
  227. /* Keep resources for in-stream. */
  228. err = amdtp_tscm_set_parameters(&tscm->tx_stream, rate);
  229. if (err < 0)
  230. return err;
  231. err = fw_iso_resources_allocate(&tscm->tx_resources,
  232. amdtp_stream_get_max_payload(&tscm->tx_stream),
  233. fw_parent_device(tscm->unit)->max_speed);
  234. if (err < 0)
  235. goto error;
  236. /* Keep resources for out-stream. */
  237. err = amdtp_tscm_set_parameters(&tscm->rx_stream, rate);
  238. if (err < 0)
  239. return err;
  240. err = fw_iso_resources_allocate(&tscm->rx_resources,
  241. amdtp_stream_get_max_payload(&tscm->rx_stream),
  242. fw_parent_device(tscm->unit)->max_speed);
  243. if (err < 0)
  244. return err;
  245. /* Register the isochronous channel for transmitting stream. */
  246. reg = cpu_to_be32(tscm->tx_resources.channel);
  247. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  248. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_CH,
  249. &reg, sizeof(reg), 0);
  250. if (err < 0)
  251. goto error;
  252. /* Unknown */
  253. reg = cpu_to_be32(0x00000002);
  254. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  255. TSCM_ADDR_BASE + TSCM_OFFSET_UNKNOWN,
  256. &reg, sizeof(reg), 0);
  257. if (err < 0)
  258. goto error;
  259. /* Register the isochronous channel for receiving stream. */
  260. reg = cpu_to_be32(tscm->rx_resources.channel);
  261. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  262. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_CH,
  263. &reg, sizeof(reg), 0);
  264. if (err < 0)
  265. goto error;
  266. return 0;
  267. error:
  268. release_resources(tscm);
  269. return err;
  270. }
  271. int snd_tscm_stream_init_duplex(struct snd_tscm *tscm)
  272. {
  273. unsigned int pcm_channels;
  274. int err;
  275. /* For out-stream. */
  276. err = fw_iso_resources_init(&tscm->rx_resources, tscm->unit);
  277. if (err < 0)
  278. return err;
  279. pcm_channels = tscm->spec->pcm_playback_analog_channels;
  280. if (tscm->spec->has_adat)
  281. pcm_channels += 8;
  282. if (tscm->spec->has_spdif)
  283. pcm_channels += 2;
  284. err = amdtp_tscm_init(&tscm->rx_stream, tscm->unit, AMDTP_OUT_STREAM,
  285. pcm_channels);
  286. if (err < 0)
  287. return err;
  288. /* For in-stream. */
  289. err = fw_iso_resources_init(&tscm->tx_resources, tscm->unit);
  290. if (err < 0)
  291. return err;
  292. pcm_channels = tscm->spec->pcm_capture_analog_channels;
  293. if (tscm->spec->has_adat)
  294. pcm_channels += 8;
  295. if (tscm->spec->has_spdif)
  296. pcm_channels += 2;
  297. err = amdtp_tscm_init(&tscm->tx_stream, tscm->unit, AMDTP_IN_STREAM,
  298. pcm_channels);
  299. if (err < 0)
  300. amdtp_stream_destroy(&tscm->rx_stream);
  301. return err;
  302. }
  303. /* At bus reset, streaming is stopped and some registers are clear. */
  304. void snd_tscm_stream_update_duplex(struct snd_tscm *tscm)
  305. {
  306. amdtp_stream_pcm_abort(&tscm->tx_stream);
  307. amdtp_stream_stop(&tscm->tx_stream);
  308. amdtp_stream_pcm_abort(&tscm->rx_stream);
  309. amdtp_stream_stop(&tscm->rx_stream);
  310. }
  311. /*
  312. * This function should be called before starting streams or after stopping
  313. * streams.
  314. */
  315. void snd_tscm_stream_destroy_duplex(struct snd_tscm *tscm)
  316. {
  317. amdtp_stream_destroy(&tscm->rx_stream);
  318. amdtp_stream_destroy(&tscm->tx_stream);
  319. fw_iso_resources_destroy(&tscm->rx_resources);
  320. fw_iso_resources_destroy(&tscm->tx_resources);
  321. }
  322. int snd_tscm_stream_start_duplex(struct snd_tscm *tscm, unsigned int rate)
  323. {
  324. unsigned int curr_rate;
  325. int err;
  326. if (tscm->substreams_counter == 0)
  327. return 0;
  328. err = snd_tscm_stream_get_rate(tscm, &curr_rate);
  329. if (err < 0)
  330. return err;
  331. if (curr_rate != rate ||
  332. amdtp_streaming_error(&tscm->rx_stream) ||
  333. amdtp_streaming_error(&tscm->tx_stream)) {
  334. finish_session(tscm);
  335. amdtp_stream_stop(&tscm->rx_stream);
  336. amdtp_stream_stop(&tscm->tx_stream);
  337. release_resources(tscm);
  338. }
  339. if (!amdtp_stream_running(&tscm->rx_stream)) {
  340. err = keep_resources(tscm, rate);
  341. if (err < 0)
  342. goto error;
  343. err = set_stream_formats(tscm, rate);
  344. if (err < 0)
  345. goto error;
  346. err = begin_session(tscm);
  347. if (err < 0)
  348. goto error;
  349. err = amdtp_stream_start(&tscm->rx_stream,
  350. tscm->rx_resources.channel,
  351. fw_parent_device(tscm->unit)->max_speed);
  352. if (err < 0)
  353. goto error;
  354. if (!amdtp_stream_wait_callback(&tscm->rx_stream,
  355. CALLBACK_TIMEOUT)) {
  356. err = -ETIMEDOUT;
  357. goto error;
  358. }
  359. }
  360. if (!amdtp_stream_running(&tscm->tx_stream)) {
  361. err = amdtp_stream_start(&tscm->tx_stream,
  362. tscm->tx_resources.channel,
  363. fw_parent_device(tscm->unit)->max_speed);
  364. if (err < 0)
  365. goto error;
  366. if (!amdtp_stream_wait_callback(&tscm->tx_stream,
  367. CALLBACK_TIMEOUT)) {
  368. err = -ETIMEDOUT;
  369. goto error;
  370. }
  371. }
  372. return 0;
  373. error:
  374. amdtp_stream_stop(&tscm->rx_stream);
  375. amdtp_stream_stop(&tscm->tx_stream);
  376. finish_session(tscm);
  377. release_resources(tscm);
  378. return err;
  379. }
  380. void snd_tscm_stream_stop_duplex(struct snd_tscm *tscm)
  381. {
  382. if (tscm->substreams_counter > 0)
  383. return;
  384. amdtp_stream_stop(&tscm->tx_stream);
  385. amdtp_stream_stop(&tscm->rx_stream);
  386. finish_session(tscm);
  387. release_resources(tscm);
  388. }
  389. void snd_tscm_stream_lock_changed(struct snd_tscm *tscm)
  390. {
  391. tscm->dev_lock_changed = true;
  392. wake_up(&tscm->hwdep_wait);
  393. }
  394. int snd_tscm_stream_lock_try(struct snd_tscm *tscm)
  395. {
  396. int err;
  397. spin_lock_irq(&tscm->lock);
  398. /* user land lock this */
  399. if (tscm->dev_lock_count < 0) {
  400. err = -EBUSY;
  401. goto end;
  402. }
  403. /* this is the first time */
  404. if (tscm->dev_lock_count++ == 0)
  405. snd_tscm_stream_lock_changed(tscm);
  406. err = 0;
  407. end:
  408. spin_unlock_irq(&tscm->lock);
  409. return err;
  410. }
  411. void snd_tscm_stream_lock_release(struct snd_tscm *tscm)
  412. {
  413. spin_lock_irq(&tscm->lock);
  414. if (WARN_ON(tscm->dev_lock_count <= 0))
  415. goto end;
  416. if (--tscm->dev_lock_count == 0)
  417. snd_tscm_stream_lock_changed(tscm);
  418. end:
  419. spin_unlock_irq(&tscm->lock);
  420. }