ark1668e_i2s.c 10 KB

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  1. /*
  2. * ark1668e_i2s.c -- ALSA SoC Audio Layer
  3. */
  4. #include <linux/init.h>
  5. #include <linux/module.h>
  6. #include <linux/io.h>
  7. #include <linux/slab.h>
  8. #include <linux/delay.h>
  9. #include <sound/core.h>
  10. #include <sound/pcm.h>
  11. #include <sound/pcm_params.h>
  12. #include <sound/soc.h>
  13. #include <sound/dmaengine_pcm.h>
  14. #include <linux/clk.h>
  15. #include "ark1668e_i2s.h"
  16. #define DRV_NAME "ark1668e-i2s"
  17. //struct ark1668e_i2s1_data_in i2s_data;
  18. int master_status = SLAVE_ON;////only for junjie
  19. struct ark1668e_i2s_dev {
  20. struct device *dev;
  21. void __iomem *base; //i2s_base
  22. struct clk *clk;
  23. int irq;
  24. u32 nco_reg;
  25. struct snd_dmaengine_dai_dma_data capture_dma_data;
  26. struct snd_dmaengine_dai_dma_data playback_dma_data;
  27. int master;
  28. u32 fmt;
  29. int full_duplex_en;
  30. };
  31. static void i2s_poweron(struct ark1668e_i2s_dev *i2s)
  32. {
  33. return;
  34. }
  35. static int ark1668e_i2s_startup(
  36. struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
  37. {
  38. struct ark1668e_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
  39. unsigned int sacr0 = 0;
  40. /* reset */
  41. writel(SACR0_RST, i2s->base + I2S_SACR0);
  42. udelay(1);
  43. writel(0, i2s->base + I2S_SACR0);
  44. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  45. /*i2s_regs_init*/
  46. sacr0 = SACR0_TLFIRST | SACR0_CH_LOCK | SACR0_TFTH(15) | SACR0_TDMAEN;
  47. if(i2s->full_duplex_en)
  48. sacr0 |= SACR0_RLFIRST | SACR0_CH_LOCK | SACR0_RFTH(16) | SACR0_RDMAEN;
  49. if (i2s->master)
  50. sacr0 |= SACR0_BCKD | SACR0_SYNCD;//ark1668e-i2s:Master mode
  51. else
  52. sacr0 &= ~(SACR0_BCKD | SACR0_SYNCD);//ark1668e-i2s:slave mode
  53. writel(sacr0, i2s->base + I2S_SACR0);
  54. writel(SAIMR_TUR, i2s->base + I2S_SAIMR);
  55. if(i2s->full_duplex_en)
  56. writel(SAIMR_ROR, i2s->base + I2S_SAIMR);
  57. writel(0x7f, i2s->base + I2S_SAICR);
  58. writel(0, i2s->base + I2S_SAICR);
  59. } else if(substream->stream == SNDRV_PCM_STREAM_CAPTURE){
  60. /*i2s_regs_init*/
  61. if(i2s->full_duplex_en)
  62. sacr0 = SACR0_TLFIRST | SACR0_CH_LOCK | SACR0_TFTH(15) | SACR0_TDMAEN;
  63. sacr0 |= SACR0_RLFIRST | SACR0_CH_LOCK | SACR0_RFTH(16) | SACR0_RDMAEN;
  64. if (i2s->master)
  65. sacr0 |= SACR0_BCKD | SACR0_SYNCD;//ark1668e-i2s:Master mode
  66. else
  67. sacr0 &= ~(SACR0_BCKD | SACR0_SYNCD);//ark1668e-i2s:slave mode
  68. writel(sacr0, i2s->base + I2S_SACR0);
  69. if(i2s->full_duplex_en)
  70. writel(SAIMR_TUR, i2s->base + I2S_SAIMR);
  71. writel(SAIMR_ROR, i2s->base + I2S_SAIMR);
  72. writel(0x7f, i2s->base + I2S_SAICR);
  73. writel(0, i2s->base + I2S_SAICR);
  74. }
  75. udelay(1);
  76. sacr0 &= ~SACR0_CH_LOCK;
  77. writel(sacr0, i2s->base + I2S_SACR0);
  78. return 0;
  79. }
  80. static int ark1668e_i2s_hw_params(
  81. struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params,
  82. struct snd_soc_dai *dai)
  83. {
  84. struct ark1668e_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
  85. u32 val;
  86. #ifndef BOARD_ARK1668E_FPGA
  87. u32 rate = params_rate(params);
  88. u32 step = 256 * 2, modulo;
  89. u32 freq;
  90. void *sysreg;
  91. if (!i2s->nco_reg)
  92. return 0;
  93. /* mclk = rate * 256, mclk = freq * step / (2 * modulo) */
  94. freq = clk_get_rate(i2s->clk);
  95. modulo = freq / rate;
  96. val = (step << 16) | modulo;
  97. sysreg = ioremap(i2s->nco_reg, 0x10);
  98. if (sysreg) {
  99. writel(val, sysreg);
  100. iounmap(sysreg);
  101. }
  102. #endif
  103. val = readl(i2s->base + I2S_SACR0);
  104. switch (params_format(params)) {
  105. case SNDRV_PCM_FORMAT_S16_LE:
  106. val &= ~SACR0_32BIT_MODE;
  107. break;
  108. case SNDRV_PCM_FORMAT_S24_LE:
  109. case SNDRV_PCM_FORMAT_S32_LE:
  110. val |= SACR0_32BIT_MODE;
  111. val &= ~(SACR0_RFTH_MASK | SACR0_TFTH_MASK);
  112. val |= SACR0_TFTH(7) | SACR0_RFTH(8);
  113. break;
  114. default:
  115. return -EINVAL;
  116. }
  117. if (params_channels(params) == 1)
  118. val |= SACR0_MOLO_MODE;
  119. writel(val, i2s->base + I2S_SACR0);
  120. return 0;
  121. }
  122. static int ark1668e_i2s_trigger(
  123. struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
  124. {
  125. struct ark1668e_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
  126. int ret = 0;
  127. switch (cmd) {
  128. case SNDRV_PCM_TRIGGER_START:
  129. if(!i2s->full_duplex_en){
  130. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  131. writel(readl(i2s->base + I2S_SACR1) & ~SACR1_DRPL, i2s->base + I2S_SACR1);
  132. else
  133. writel(readl(i2s->base + I2S_SACR1) & ~SACR1_DREC, i2s->base + I2S_SACR1);
  134. }else{
  135. writel(readl(i2s->base + I2S_SACR1) & ~SACR1_DRPL, i2s->base + I2S_SACR1);
  136. writel(readl(i2s->base + I2S_SACR1) & ~SACR1_DREC, i2s->base + I2S_SACR1);
  137. }
  138. writel(readl(i2s->base + I2S_SACR0) | SACR0_ENB, i2s->base + I2S_SACR0);
  139. break;
  140. case SNDRV_PCM_TRIGGER_STOP:
  141. /* if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  142. writel(readl(i2s->base + I2S_SACR1) | SACR1_DRPL, i2s->base + I2S_SACR1);
  143. else
  144. writel(readl(i2s->base + I2S_SACR1) | SACR1_DREC, i2s->base + I2S_SACR1);
  145. writel(readl(i2s->base + I2S_SACR0) & ~SACR0_ENB, i2s->base + I2S_SACR0); */
  146. break;
  147. case SNDRV_PCM_TRIGGER_RESUME:
  148. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  149. case SNDRV_PCM_TRIGGER_SUSPEND:
  150. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  151. break;
  152. default:
  153. ret = -EINVAL;
  154. }
  155. return ret;
  156. }
  157. static int ark1668e_i2s_set_fmt(
  158. struct snd_soc_dai *dai, unsigned int fmt)
  159. {
  160. struct ark1668e_i2s_dev *i2s =snd_soc_dai_get_drvdata(dai);
  161. /* interface format */
  162. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  163. case SND_SOC_DAIFMT_I2S:
  164. i2s->fmt = 0;
  165. break;
  166. }
  167. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  168. case SND_SOC_DAIFMT_CBS_CFS:
  169. dev_dbg(i2s->dev, "i2s master.\n");
  170. i2s->master = 1;
  171. break;
  172. case SND_SOC_DAIFMT_CBM_CFM:
  173. dev_dbg(i2s->dev, "i2s slave.\n");
  174. i2s->master = 0;
  175. break;
  176. default:
  177. break;
  178. }
  179. return 0;
  180. }
  181. static int ark1668e_i2s_probe(struct snd_soc_dai *dai)
  182. {
  183. struct ark1668e_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
  184. dai->capture_dma_data = &i2s->capture_dma_data;
  185. dai->playback_dma_data = &i2s->playback_dma_data;
  186. return 0;
  187. }
  188. /* I2S supported rate and format */
  189. #define ARK1668E_I2S_RATES \
  190. (SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
  191. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
  192. SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
  193. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_8000)
  194. static const struct snd_soc_dai_ops ark1668e_i2s_dai_ops = {
  195. .startup = ark1668e_i2s_startup,
  196. .trigger = ark1668e_i2s_trigger,
  197. .hw_params = ark1668e_i2s_hw_params,
  198. .set_fmt = ark1668e_i2s_set_fmt,
  199. };
  200. static struct snd_soc_dai_driver ark1668e_i2s_dai = {
  201. .probe = ark1668e_i2s_probe,
  202. .playback = {
  203. .channels_min = 1,
  204. .channels_max = 2,
  205. .rates = ARK1668E_I2S_RATES,
  206. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
  207. SNDRV_PCM_FMTBIT_S32_LE,},
  208. .capture = {
  209. .channels_min = 2,
  210. .channels_max = 2,
  211. .rates = ARK1668E_I2S_RATES,
  212. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
  213. SNDRV_PCM_FMTBIT_S32_LE,},
  214. .ops = &ark1668e_i2s_dai_ops,
  215. .symmetric_rates = 1,
  216. };
  217. static struct snd_pcm_hardware ark1668e_pcm_hardware = {
  218. .info = (SNDRV_PCM_INFO_MMAP |
  219. SNDRV_PCM_INFO_MMAP_VALID |
  220. SNDRV_PCM_INFO_PAUSE |
  221. SNDRV_PCM_INFO_RESUME |
  222. SNDRV_PCM_INFO_INTERLEAVED |
  223. SNDRV_PCM_INFO_BLOCK_TRANSFER),
  224. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
  225. SNDRV_PCM_FMTBIT_S32_LE,
  226. .rates = (SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 |
  227. SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
  228. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
  229. SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 |
  230. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
  231. SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_8000),
  232. .rate_min = 8000,
  233. .rate_max = 192000,
  234. .channels_min = 1,
  235. .channels_max = 2,
  236. .buffer_bytes_max = 64 * 65536,
  237. .period_bytes_min = 64,
  238. .period_bytes_max = 65536,
  239. .periods_min = 1,
  240. .periods_max = 64,
  241. };
  242. static const struct snd_dmaengine_pcm_config
  243. ark1668e_i2s_dmaengine_pcm_config = {
  244. .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
  245. .pcm_hardware = &ark1668e_pcm_hardware,
  246. };
  247. static const struct snd_soc_component_driver ark1668e_i2s_component = {
  248. .name = DRV_NAME,
  249. };
  250. static irqreturn_t ark1668e_i2s_interrupt(int irq, void *dev_id)
  251. {
  252. struct ark1668e_i2s_dev *i2s = dev_id;
  253. u32 status;
  254. status = readl(i2s->base + I2S_SASR0);
  255. dev_dbg(i2s->dev, "ark1668e_i2s_interrupt status=0x%x.0x%x.\n", status, readl(i2s->base + I2S_SACR0));
  256. writel(status, i2s->base + I2S_SAICR);
  257. writel(0, i2s->base + I2S_SAICR);
  258. return IRQ_HANDLED;
  259. }
  260. static int ark1668e_i2s_drv_probe(struct platform_device *pdev)
  261. {
  262. struct ark1668e_i2s_dev *i2s;
  263. struct resource *res;
  264. u32 val;
  265. int ret = 0;
  266. i2s = devm_kzalloc(&pdev->dev, sizeof(struct ark1668e_i2s_dev), GFP_KERNEL);
  267. if (!i2s)
  268. return -ENOMEM;
  269. i2s->dev = &pdev->dev;
  270. //i2s resource
  271. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  272. i2s->base = devm_ioremap_resource(&pdev->dev, res);
  273. if (IS_ERR(i2s->base))
  274. return PTR_ERR(i2s->base);
  275. if (!of_property_read_u32(pdev->dev.of_node, "nco-reg", &val))
  276. i2s->nco_reg = val;
  277. if (of_property_read_bool(pdev->dev.of_node, "full-duplex-mode"))
  278. i2s->full_duplex_en = 1;
  279. //printk(">>>>>>>>>>>>>>>>>>i2s->full_duplex_en = %d \n",i2s->full_duplex_en);
  280. i2s->clk = of_clk_get(pdev->dev.of_node, 0);
  281. if (IS_ERR(i2s->clk))
  282. return PTR_ERR(i2s->clk);
  283. i2s->irq = platform_get_irq(pdev, 0);
  284. if (i2s->irq < 0)
  285. return i2s->irq;
  286. ret = devm_request_irq(i2s->dev, i2s->irq, ark1668e_i2s_interrupt,
  287. IRQF_SHARED, KBUILD_MODNAME, i2s);
  288. if (ret)
  289. return ret;
  290. /* DMA parameters */
  291. i2s->playback_dma_data.addr = res->start + I2S_SADR;
  292. i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  293. i2s->playback_dma_data.maxburst = 16;
  294. i2s->capture_dma_data.addr = res->start + I2S_SADR;
  295. i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  296. i2s->capture_dma_data.maxburst = 16;
  297. dev_set_drvdata(&pdev->dev, i2s);
  298. ret = devm_snd_soc_register_component(&pdev->dev,
  299. &ark1668e_i2s_component,
  300. &ark1668e_i2s_dai, 1);
  301. if (ret) {
  302. dev_err(&pdev->dev, "Could not register DAI\n");
  303. return ret;
  304. }
  305. i2s_poweron(i2s);
  306. ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
  307. &ark1668e_i2s_dmaengine_pcm_config,
  308. 0);
  309. if (ret) {
  310. dev_err(&pdev->dev, "Could not register PCM\n");
  311. return ret;
  312. }
  313. return 0;
  314. }
  315. static const struct of_device_id ark1668e_i2s_match[] = {
  316. { .compatible = "arkmicro,ark1668e-i2s", },
  317. {},
  318. };
  319. static struct platform_driver ark1668e_i2s_driver = {
  320. .probe = ark1668e_i2s_drv_probe,
  321. .driver = {
  322. .name = DRV_NAME,
  323. .of_match_table = of_match_ptr(ark1668e_i2s_match),
  324. },
  325. };
  326. module_platform_driver(ark1668e_i2s_driver);
  327. MODULE_DESCRIPTION("ARK I2S SoC Interface");
  328. MODULE_ALIAS("platform:" DRV_NAME);
  329. MODULE_AUTHOR("Sim");
  330. MODULE_LICENSE("GPL v2");