sst-haswell-dsp.c 19 KB

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  1. /*
  2. * Intel Haswell SST DSP driver
  3. *
  4. * Copyright (C) 2013, Intel Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License version
  8. * 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. */
  16. #include <linux/delay.h>
  17. #include <linux/fs.h>
  18. #include <linux/slab.h>
  19. #include <linux/device.h>
  20. #include <linux/sched.h>
  21. #include <linux/export.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/module.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/pci.h>
  27. #include <linux/firmware.h>
  28. #include <linux/pm_runtime.h>
  29. #include "../common/sst-dsp.h"
  30. #include "../common/sst-dsp-priv.h"
  31. #include "../haswell/sst-haswell-ipc.h"
  32. #include <trace/events/hswadsp.h>
  33. #define SST_HSW_FW_SIGNATURE_SIZE 4
  34. #define SST_HSW_FW_SIGN "$SST"
  35. #define SST_HSW_FW_LIB_SIGN "$LIB"
  36. #define SST_WPT_SHIM_OFFSET 0xFB000
  37. #define SST_LP_SHIM_OFFSET 0xE7000
  38. #define SST_WPT_IRAM_OFFSET 0xA0000
  39. #define SST_LP_IRAM_OFFSET 0x80000
  40. #define SST_WPT_DSP_DRAM_OFFSET 0x400000
  41. #define SST_WPT_DSP_IRAM_OFFSET 0x00000
  42. #define SST_LPT_DSP_DRAM_OFFSET 0x400000
  43. #define SST_LPT_DSP_IRAM_OFFSET 0x00000
  44. #define SST_SHIM_PM_REG 0x84
  45. #define SST_HSW_IRAM 1
  46. #define SST_HSW_DRAM 2
  47. #define SST_HSW_REGS 3
  48. struct dma_block_info {
  49. __le32 type; /* IRAM/DRAM */
  50. __le32 size; /* Bytes */
  51. __le32 ram_offset; /* Offset in I/DRAM */
  52. __le32 rsvd; /* Reserved field */
  53. } __attribute__((packed));
  54. struct fw_module_info {
  55. __le32 persistent_size;
  56. __le32 scratch_size;
  57. } __attribute__((packed));
  58. struct fw_header {
  59. unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* FW signature */
  60. __le32 file_size; /* size of fw minus this header */
  61. __le32 modules; /* # of modules */
  62. __le32 file_format; /* version of header format */
  63. __le32 reserved[4];
  64. } __attribute__((packed));
  65. struct fw_module_header {
  66. unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* module signature */
  67. __le32 mod_size; /* size of module */
  68. __le32 blocks; /* # of blocks */
  69. __le16 padding;
  70. __le16 type; /* codec type, pp lib */
  71. __le32 entry_point;
  72. struct fw_module_info info;
  73. } __attribute__((packed));
  74. static void hsw_free(struct sst_dsp *sst);
  75. static int hsw_parse_module(struct sst_dsp *dsp, struct sst_fw *fw,
  76. struct fw_module_header *module)
  77. {
  78. struct dma_block_info *block;
  79. struct sst_module *mod;
  80. struct sst_module_template template;
  81. int count, ret;
  82. void __iomem *ram;
  83. int type = le16_to_cpu(module->type);
  84. int entry_point = le32_to_cpu(module->entry_point);
  85. /* TODO: allowed module types need to be configurable */
  86. if (type != SST_HSW_MODULE_BASE_FW &&
  87. type != SST_HSW_MODULE_PCM_SYSTEM &&
  88. type != SST_HSW_MODULE_PCM &&
  89. type != SST_HSW_MODULE_PCM_REFERENCE &&
  90. type != SST_HSW_MODULE_PCM_CAPTURE &&
  91. type != SST_HSW_MODULE_WAVES &&
  92. type != SST_HSW_MODULE_LPAL)
  93. return 0;
  94. dev_dbg(dsp->dev, "new module sign 0x%s size 0x%x blocks 0x%x type 0x%x\n",
  95. module->signature, module->mod_size,
  96. module->blocks, type);
  97. dev_dbg(dsp->dev, " entrypoint 0x%x\n", entry_point);
  98. dev_dbg(dsp->dev, " persistent 0x%x scratch 0x%x\n",
  99. module->info.persistent_size, module->info.scratch_size);
  100. memset(&template, 0, sizeof(template));
  101. template.id = type;
  102. template.entry = entry_point - 4;
  103. template.persistent_size = le32_to_cpu(module->info.persistent_size);
  104. template.scratch_size = le32_to_cpu(module->info.scratch_size);
  105. mod = sst_module_new(fw, &template, NULL);
  106. if (mod == NULL)
  107. return -ENOMEM;
  108. block = (void *)module + sizeof(*module);
  109. for (count = 0; count < le32_to_cpu(module->blocks); count++) {
  110. if (le32_to_cpu(block->size) <= 0) {
  111. dev_err(dsp->dev,
  112. "error: block %d size invalid\n", count);
  113. sst_module_free(mod);
  114. return -EINVAL;
  115. }
  116. switch (le32_to_cpu(block->type)) {
  117. case SST_HSW_IRAM:
  118. ram = dsp->addr.lpe;
  119. mod->offset = le32_to_cpu(block->ram_offset) +
  120. dsp->addr.iram_offset;
  121. mod->type = SST_MEM_IRAM;
  122. break;
  123. case SST_HSW_DRAM:
  124. case SST_HSW_REGS:
  125. ram = dsp->addr.lpe;
  126. mod->offset = le32_to_cpu(block->ram_offset);
  127. mod->type = SST_MEM_DRAM;
  128. break;
  129. default:
  130. dev_err(dsp->dev, "error: bad type 0x%x for block 0x%x\n",
  131. block->type, count);
  132. sst_module_free(mod);
  133. return -EINVAL;
  134. }
  135. mod->size = le32_to_cpu(block->size);
  136. mod->data = (void *)block + sizeof(*block);
  137. mod->data_offset = mod->data - fw->dma_buf;
  138. dev_dbg(dsp->dev, "module block %d type 0x%x "
  139. "size 0x%x ==> ram %p offset 0x%x\n",
  140. count, mod->type, block->size, ram,
  141. block->ram_offset);
  142. ret = sst_module_alloc_blocks(mod);
  143. if (ret < 0) {
  144. dev_err(dsp->dev, "error: could not allocate blocks for module %d\n",
  145. count);
  146. sst_module_free(mod);
  147. return ret;
  148. }
  149. block = (void *)block + sizeof(*block) +
  150. le32_to_cpu(block->size);
  151. }
  152. mod->state = SST_MODULE_STATE_LOADED;
  153. return 0;
  154. }
  155. static int hsw_parse_fw_image(struct sst_fw *sst_fw)
  156. {
  157. struct fw_header *header;
  158. struct fw_module_header *module;
  159. struct sst_dsp *dsp = sst_fw->dsp;
  160. int ret, count;
  161. /* Read the header information from the data pointer */
  162. header = (struct fw_header *)sst_fw->dma_buf;
  163. /* verify FW */
  164. if ((strncmp(header->signature, SST_HSW_FW_SIGN, 4) != 0) ||
  165. (sst_fw->size !=
  166. le32_to_cpu(header->file_size) + sizeof(*header))) {
  167. dev_err(dsp->dev, "error: invalid fw sign/filesize mismatch\n");
  168. return -EINVAL;
  169. }
  170. dev_dbg(dsp->dev, "header size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
  171. header->file_size, header->modules,
  172. header->file_format, sizeof(*header));
  173. /* parse each module */
  174. module = (void *)sst_fw->dma_buf + sizeof(*header);
  175. for (count = 0; count < le32_to_cpu(header->modules); count++) {
  176. /* module */
  177. ret = hsw_parse_module(dsp, sst_fw, module);
  178. if (ret < 0) {
  179. dev_err(dsp->dev, "error: invalid module %d\n", count);
  180. return ret;
  181. }
  182. module = (void *)module + sizeof(*module) +
  183. le32_to_cpu(module->mod_size);
  184. }
  185. return 0;
  186. }
  187. static irqreturn_t hsw_irq(int irq, void *context)
  188. {
  189. struct sst_dsp *sst = (struct sst_dsp *) context;
  190. u32 isr;
  191. int ret = IRQ_NONE;
  192. spin_lock(&sst->spinlock);
  193. /* Interrupt arrived, check src */
  194. isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
  195. if (isr & SST_ISRX_DONE) {
  196. trace_sst_irq_done(isr,
  197. sst_dsp_shim_read_unlocked(sst, SST_IMRX));
  198. /* Mask Done interrupt before return */
  199. sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
  200. SST_IMRX_DONE, SST_IMRX_DONE);
  201. ret = IRQ_WAKE_THREAD;
  202. }
  203. if (isr & SST_ISRX_BUSY) {
  204. trace_sst_irq_busy(isr,
  205. sst_dsp_shim_read_unlocked(sst, SST_IMRX));
  206. /* Mask Busy interrupt before return */
  207. sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
  208. SST_IMRX_BUSY, SST_IMRX_BUSY);
  209. ret = IRQ_WAKE_THREAD;
  210. }
  211. spin_unlock(&sst->spinlock);
  212. return ret;
  213. }
  214. static void hsw_set_dsp_D3(struct sst_dsp *sst)
  215. {
  216. u32 val;
  217. u32 reg;
  218. /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
  219. reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
  220. reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
  221. writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
  222. /* enable power gating and switch off DRAM & IRAM blocks */
  223. val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
  224. val |= SST_VDRTCL0_DSRAMPGE_MASK |
  225. SST_VDRTCL0_ISRAMPGE_MASK;
  226. val &= ~(SST_VDRTCL0_D3PGD | SST_VDRTCL0_D3SRAMPGD);
  227. writel(val, sst->addr.pci_cfg + SST_VDRTCTL0);
  228. /* switch off audio PLL */
  229. val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
  230. val |= SST_VDRTCL2_APLLSE_MASK;
  231. writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
  232. /* disable MCLK(clkctl.smos = 0) */
  233. sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
  234. SST_CLKCTL_MASK, 0);
  235. /* Set D3 state, delay 50 us */
  236. val = readl(sst->addr.pci_cfg + SST_PMCS);
  237. val |= SST_PMCS_PS_MASK;
  238. writel(val, sst->addr.pci_cfg + SST_PMCS);
  239. udelay(50);
  240. /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
  241. reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
  242. reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
  243. writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
  244. udelay(50);
  245. }
  246. static void hsw_reset(struct sst_dsp *sst)
  247. {
  248. /* put DSP into reset and stall */
  249. sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
  250. SST_CSR_RST | SST_CSR_STALL,
  251. SST_CSR_RST | SST_CSR_STALL);
  252. /* keep in reset for 10ms */
  253. mdelay(10);
  254. /* take DSP out of reset and keep stalled for FW loading */
  255. sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
  256. SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL);
  257. }
  258. static int hsw_set_dsp_D0(struct sst_dsp *sst)
  259. {
  260. int tries = 10;
  261. u32 reg, fw_dump_bit;
  262. /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
  263. reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
  264. reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
  265. writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
  266. /* Disable D3PG (VDRTCTL0.D3PGD = 1) */
  267. reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
  268. reg |= SST_VDRTCL0_D3PGD;
  269. writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0);
  270. /* Set D0 state */
  271. reg = readl(sst->addr.pci_cfg + SST_PMCS);
  272. reg &= ~SST_PMCS_PS_MASK;
  273. writel(reg, sst->addr.pci_cfg + SST_PMCS);
  274. /* check that ADSP shim is enabled */
  275. while (tries--) {
  276. reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK;
  277. if (reg == 0)
  278. goto finish;
  279. msleep(1);
  280. }
  281. return -ENODEV;
  282. finish:
  283. /* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */
  284. sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
  285. SST_CSR_S1IOCS | SST_CSR_SBCS1 | SST_CSR_LPCS, 0x0);
  286. /* stall DSP core, set clk to 192/96Mhz */
  287. sst_dsp_shim_update_bits_unlocked(sst,
  288. SST_CSR, SST_CSR_STALL | SST_CSR_DCS_MASK,
  289. SST_CSR_STALL | SST_CSR_DCS(4));
  290. /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
  291. sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
  292. SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0,
  293. SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0);
  294. /* Stall and reset core, set CSR */
  295. hsw_reset(sst);
  296. /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
  297. reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
  298. reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
  299. writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
  300. udelay(50);
  301. /* switch on audio PLL */
  302. reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
  303. reg &= ~SST_VDRTCL2_APLLSE_MASK;
  304. writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
  305. /* set default power gating control, enable power gating control for all blocks. that is,
  306. can't be accessed, please enable each block before accessing. */
  307. reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
  308. reg |= SST_VDRTCL0_DSRAMPGE_MASK | SST_VDRTCL0_ISRAMPGE_MASK;
  309. /* for D0, always enable the block(DSRAM[0]) used for FW dump */
  310. fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT;
  311. writel(reg & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0);
  312. /* disable DMA finish function for SSP0 & SSP1 */
  313. sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,
  314. SST_CSR2_SDFD_SSP1);
  315. /* set on-demond mode on engine 0,1 for all channels */
  316. sst_dsp_shim_update_bits(sst, SST_HMDC,
  317. SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
  318. SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
  319. /* Enable Interrupt from both sides */
  320. sst_dsp_shim_update_bits(sst, SST_IMRX, (SST_IMRX_BUSY | SST_IMRX_DONE),
  321. 0x0);
  322. sst_dsp_shim_update_bits(sst, SST_IMRD, (SST_IMRD_DONE | SST_IMRD_BUSY |
  323. SST_IMRD_SSP0 | SST_IMRD_DMAC), 0x0);
  324. /* clear IPC registers */
  325. sst_dsp_shim_write(sst, SST_IPCX, 0x0);
  326. sst_dsp_shim_write(sst, SST_IPCD, 0x0);
  327. sst_dsp_shim_write(sst, 0x80, 0x6);
  328. sst_dsp_shim_write(sst, 0xe0, 0x300a);
  329. return 0;
  330. }
  331. static void hsw_boot(struct sst_dsp *sst)
  332. {
  333. /* set oportunistic mode on engine 0,1 for all channels */
  334. sst_dsp_shim_update_bits(sst, SST_HMDC,
  335. SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH, 0);
  336. /* set DSP to RUN */
  337. sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_STALL, 0x0);
  338. }
  339. static void hsw_stall(struct sst_dsp *sst)
  340. {
  341. /* stall DSP */
  342. sst_dsp_shim_update_bits(sst, SST_CSR,
  343. SST_CSR_24MHZ_LPCS | SST_CSR_STALL,
  344. SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
  345. }
  346. static void hsw_sleep(struct sst_dsp *sst)
  347. {
  348. dev_dbg(sst->dev, "HSW_PM dsp runtime suspend\n");
  349. /* put DSP into reset and stall */
  350. sst_dsp_shim_update_bits(sst, SST_CSR,
  351. SST_CSR_24MHZ_LPCS | SST_CSR_RST | SST_CSR_STALL,
  352. SST_CSR_RST | SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
  353. hsw_set_dsp_D3(sst);
  354. dev_dbg(sst->dev, "HSW_PM dsp runtime suspend exit\n");
  355. }
  356. static int hsw_wake(struct sst_dsp *sst)
  357. {
  358. int ret;
  359. dev_dbg(sst->dev, "HSW_PM dsp runtime resume\n");
  360. ret = hsw_set_dsp_D0(sst);
  361. if (ret < 0)
  362. return ret;
  363. dev_dbg(sst->dev, "HSW_PM dsp runtime resume exit\n");
  364. return 0;
  365. }
  366. struct sst_adsp_memregion {
  367. u32 start;
  368. u32 end;
  369. int blocks;
  370. enum sst_mem_type type;
  371. };
  372. /* lynx point ADSP mem regions */
  373. static const struct sst_adsp_memregion lp_region[] = {
  374. {0x00000, 0x40000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
  375. {0x40000, 0x80000, 8, SST_MEM_DRAM}, /* D-SRAM1 - 8 * 32kB */
  376. {0x80000, 0xE0000, 12, SST_MEM_IRAM}, /* I-SRAM - 12 * 32kB */
  377. };
  378. /* wild cat point ADSP mem regions */
  379. static const struct sst_adsp_memregion wpt_region[] = {
  380. {0x00000, 0xA0000, 20, SST_MEM_DRAM}, /* D-SRAM0,D-SRAM1,D-SRAM2 - 20 * 32kB */
  381. {0xA0000, 0xF0000, 10, SST_MEM_IRAM}, /* I-SRAM - 10 * 32kB */
  382. };
  383. static int hsw_acpi_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)
  384. {
  385. /* ADSP DRAM & IRAM */
  386. sst->addr.lpe_base = pdata->lpe_base;
  387. sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
  388. if (!sst->addr.lpe)
  389. return -ENODEV;
  390. /* ADSP PCI MMIO config space */
  391. sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
  392. if (!sst->addr.pci_cfg) {
  393. iounmap(sst->addr.lpe);
  394. return -ENODEV;
  395. }
  396. /* SST Shim */
  397. sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
  398. return 0;
  399. }
  400. struct sst_sram_shift {
  401. u32 dev_id; /* SST Device IDs */
  402. u32 iram_shift;
  403. u32 dram_shift;
  404. };
  405. static const struct sst_sram_shift sram_shift[] = {
  406. {SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */
  407. {SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */
  408. };
  409. static u32 hsw_block_get_bit(struct sst_mem_block *block)
  410. {
  411. u32 bit = 0, shift = 0, index;
  412. struct sst_dsp *sst = block->dsp;
  413. for (index = 0; index < ARRAY_SIZE(sram_shift); index++) {
  414. if (sram_shift[index].dev_id == sst->id)
  415. break;
  416. }
  417. if (index < ARRAY_SIZE(sram_shift)) {
  418. switch (block->type) {
  419. case SST_MEM_DRAM:
  420. shift = sram_shift[index].dram_shift;
  421. break;
  422. case SST_MEM_IRAM:
  423. shift = sram_shift[index].iram_shift;
  424. break;
  425. default:
  426. shift = 0;
  427. }
  428. } else
  429. shift = 0;
  430. bit = 1 << (block->index + shift);
  431. return bit;
  432. }
  433. /*dummy read a SRAM block.*/
  434. static void sst_mem_block_dummy_read(struct sst_mem_block *block)
  435. {
  436. u32 size;
  437. u8 tmp_buf[4];
  438. struct sst_dsp *sst = block->dsp;
  439. size = block->size > 4 ? 4 : block->size;
  440. memcpy_fromio(tmp_buf, sst->addr.lpe + block->offset, size);
  441. }
  442. /* enable 32kB memory block - locks held by caller */
  443. static int hsw_block_enable(struct sst_mem_block *block)
  444. {
  445. struct sst_dsp *sst = block->dsp;
  446. u32 bit, val;
  447. if (block->users++ > 0)
  448. return 0;
  449. dev_dbg(block->dsp->dev, " enabled block %d:%d at offset 0x%x\n",
  450. block->type, block->index, block->offset);
  451. /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
  452. val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
  453. val &= ~SST_VDRTCL2_DCLCGE;
  454. writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
  455. val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
  456. bit = hsw_block_get_bit(block);
  457. writel(val & ~bit, sst->addr.pci_cfg + SST_VDRTCTL0);
  458. /* wait 18 DSP clock ticks */
  459. udelay(10);
  460. /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
  461. val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
  462. val |= SST_VDRTCL2_DCLCGE;
  463. writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
  464. udelay(50);
  465. /*add a dummy read before the SRAM block is written, otherwise the writing may miss bytes sometimes.*/
  466. sst_mem_block_dummy_read(block);
  467. return 0;
  468. }
  469. /* disable 32kB memory block - locks held by caller */
  470. static int hsw_block_disable(struct sst_mem_block *block)
  471. {
  472. struct sst_dsp *sst = block->dsp;
  473. u32 bit, val;
  474. if (--block->users > 0)
  475. return 0;
  476. dev_dbg(block->dsp->dev, " disabled block %d:%d at offset 0x%x\n",
  477. block->type, block->index, block->offset);
  478. /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
  479. val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
  480. val &= ~SST_VDRTCL2_DCLCGE;
  481. writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
  482. val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
  483. bit = hsw_block_get_bit(block);
  484. /* don't disable DSRAM[0], keep it always enable for FW dump*/
  485. if (bit != (1 << SST_VDRTCL0_DSRAMPGE_SHIFT))
  486. writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0);
  487. /* wait 18 DSP clock ticks */
  488. udelay(10);
  489. /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
  490. val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
  491. val |= SST_VDRTCL2_DCLCGE;
  492. writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
  493. udelay(50);
  494. return 0;
  495. }
  496. static const struct sst_block_ops sst_hsw_ops = {
  497. .enable = hsw_block_enable,
  498. .disable = hsw_block_disable,
  499. };
  500. static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)
  501. {
  502. const struct sst_adsp_memregion *region;
  503. struct device *dev;
  504. int ret = -ENODEV, i, j, region_count;
  505. u32 offset, size, fw_dump_bit;
  506. dev = sst->dma_dev;
  507. switch (sst->id) {
  508. case SST_DEV_ID_LYNX_POINT:
  509. region = lp_region;
  510. region_count = ARRAY_SIZE(lp_region);
  511. sst->addr.iram_offset = SST_LP_IRAM_OFFSET;
  512. sst->addr.dsp_iram_offset = SST_LPT_DSP_IRAM_OFFSET;
  513. sst->addr.dsp_dram_offset = SST_LPT_DSP_DRAM_OFFSET;
  514. sst->addr.shim_offset = SST_LP_SHIM_OFFSET;
  515. break;
  516. case SST_DEV_ID_WILDCAT_POINT:
  517. region = wpt_region;
  518. region_count = ARRAY_SIZE(wpt_region);
  519. sst->addr.iram_offset = SST_WPT_IRAM_OFFSET;
  520. sst->addr.dsp_iram_offset = SST_WPT_DSP_IRAM_OFFSET;
  521. sst->addr.dsp_dram_offset = SST_WPT_DSP_DRAM_OFFSET;
  522. sst->addr.shim_offset = SST_WPT_SHIM_OFFSET;
  523. break;
  524. default:
  525. dev_err(dev, "error: failed to get mem resources\n");
  526. return ret;
  527. }
  528. ret = hsw_acpi_resource_map(sst, pdata);
  529. if (ret < 0) {
  530. dev_err(dev, "error: failed to map resources\n");
  531. return ret;
  532. }
  533. /* enable the DSP SHIM */
  534. ret = hsw_set_dsp_D0(sst);
  535. if (ret < 0) {
  536. dev_err(dev, "error: failed to set DSP D0 and reset SHIM\n");
  537. return ret;
  538. }
  539. ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(31));
  540. if (ret)
  541. return ret;
  542. /* register DSP memory blocks - ideally we should get this from ACPI */
  543. for (i = 0; i < region_count; i++) {
  544. offset = region[i].start;
  545. size = (region[i].end - region[i].start) / region[i].blocks;
  546. /* register individual memory blocks */
  547. for (j = 0; j < region[i].blocks; j++) {
  548. sst_mem_block_register(sst, offset, size,
  549. region[i].type, &sst_hsw_ops, j, sst);
  550. offset += size;
  551. }
  552. }
  553. /* always enable the block(DSRAM[0]) used for FW dump */
  554. fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT;
  555. /* set default power gating control, enable power gating control for all blocks. that is,
  556. can't be accessed, please enable each block before accessing. */
  557. writel(0xffffffff & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0);
  558. return 0;
  559. }
  560. static void hsw_free(struct sst_dsp *sst)
  561. {
  562. sst_mem_block_unregister_all(sst);
  563. iounmap(sst->addr.lpe);
  564. iounmap(sst->addr.pci_cfg);
  565. }
  566. struct sst_ops haswell_ops = {
  567. .reset = hsw_reset,
  568. .boot = hsw_boot,
  569. .stall = hsw_stall,
  570. .wake = hsw_wake,
  571. .sleep = hsw_sleep,
  572. .write = sst_shim32_write,
  573. .read = sst_shim32_read,
  574. .write64 = sst_shim32_write64,
  575. .read64 = sst_shim32_read64,
  576. .ram_read = sst_memcpy_fromio_32,
  577. .ram_write = sst_memcpy_toio_32,
  578. .irq_handler = hsw_irq,
  579. .init = hsw_init,
  580. .free = hsw_free,
  581. .parse_fw = hsw_parse_fw_image,
  582. };