sst-haswell-ipc.c 57 KB

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  1. /*
  2. * Intel SST Haswell/Broadwell IPC Support
  3. *
  4. * Copyright (C) 2013, Intel Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License version
  8. * 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. */
  16. #include <linux/types.h>
  17. #include <linux/kernel.h>
  18. #include <linux/list.h>
  19. #include <linux/device.h>
  20. #include <linux/wait.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/workqueue.h>
  23. #include <linux/export.h>
  24. #include <linux/slab.h>
  25. #include <linux/delay.h>
  26. #include <linux/sched.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/firmware.h>
  29. #include <linux/dma-mapping.h>
  30. #include <linux/debugfs.h>
  31. #include <linux/pm_runtime.h>
  32. #include <sound/asound.h>
  33. #include "sst-haswell-ipc.h"
  34. #include "../common/sst-dsp.h"
  35. #include "../common/sst-dsp-priv.h"
  36. #include "../common/sst-ipc.h"
  37. /* Global Message - Generic */
  38. #define IPC_GLB_TYPE_SHIFT 24
  39. #define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
  40. #define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
  41. /* Global Message - Reply */
  42. #define IPC_GLB_REPLY_SHIFT 0
  43. #define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
  44. #define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
  45. /* Stream Message - Generic */
  46. #define IPC_STR_TYPE_SHIFT 20
  47. #define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
  48. #define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
  49. #define IPC_STR_ID_SHIFT 16
  50. #define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
  51. #define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
  52. /* Stream Message - Reply */
  53. #define IPC_STR_REPLY_SHIFT 0
  54. #define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
  55. /* Stream Stage Message - Generic */
  56. #define IPC_STG_TYPE_SHIFT 12
  57. #define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
  58. #define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
  59. #define IPC_STG_ID_SHIFT 10
  60. #define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
  61. #define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
  62. /* Stream Stage Message - Reply */
  63. #define IPC_STG_REPLY_SHIFT 0
  64. #define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
  65. /* Debug Log Message - Generic */
  66. #define IPC_LOG_OP_SHIFT 20
  67. #define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
  68. #define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
  69. #define IPC_LOG_ID_SHIFT 16
  70. #define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
  71. #define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
  72. /* Module Message */
  73. #define IPC_MODULE_OPERATION_SHIFT 20
  74. #define IPC_MODULE_OPERATION_MASK (0xf << IPC_MODULE_OPERATION_SHIFT)
  75. #define IPC_MODULE_OPERATION(x) (x << IPC_MODULE_OPERATION_SHIFT)
  76. #define IPC_MODULE_ID_SHIFT 16
  77. #define IPC_MODULE_ID_MASK (0xf << IPC_MODULE_ID_SHIFT)
  78. #define IPC_MODULE_ID(x) (x << IPC_MODULE_ID_SHIFT)
  79. /* IPC message timeout (msecs) */
  80. #define IPC_TIMEOUT_MSECS 300
  81. #define IPC_BOOT_MSECS 200
  82. #define IPC_MSG_WAIT 0
  83. #define IPC_MSG_NOWAIT 1
  84. /* Firmware Ready Message */
  85. #define IPC_FW_READY (0x1 << 29)
  86. #define IPC_STATUS_MASK (0x3 << 30)
  87. #define IPC_EMPTY_LIST_SIZE 8
  88. #define IPC_MAX_STREAMS 4
  89. /* Mailbox */
  90. #define IPC_MAX_MAILBOX_BYTES 256
  91. #define INVALID_STREAM_HW_ID 0xffffffff
  92. /* Global Message - Types and Replies */
  93. enum ipc_glb_type {
  94. IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
  95. IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
  96. IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
  97. IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
  98. IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
  99. IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
  100. /* Request to store firmware context during D0->D3 transition */
  101. IPC_GLB_REQUEST_DUMP = 7,
  102. /* Request to restore firmware context during D3->D0 transition */
  103. IPC_GLB_RESTORE_CONTEXT = 8,
  104. IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
  105. IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
  106. IPC_GLB_SHORT_REPLY = 11,
  107. IPC_GLB_ENTER_DX_STATE = 12,
  108. IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
  109. IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
  110. IPC_GLB_MODULE_OPERATION = 15, /* Message to loadable fw module */
  111. IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
  112. IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
  113. };
  114. enum ipc_glb_reply {
  115. IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
  116. IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
  117. IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
  118. IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
  119. IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
  120. IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
  121. IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
  122. IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
  123. IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
  124. IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
  125. IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
  126. };
  127. enum ipc_module_operation {
  128. IPC_MODULE_NOTIFICATION = 0,
  129. IPC_MODULE_ENABLE = 1,
  130. IPC_MODULE_DISABLE = 2,
  131. IPC_MODULE_GET_PARAMETER = 3,
  132. IPC_MODULE_SET_PARAMETER = 4,
  133. IPC_MODULE_GET_INFO = 5,
  134. IPC_MODULE_MAX_MESSAGE
  135. };
  136. /* Stream Message - Types */
  137. enum ipc_str_operation {
  138. IPC_STR_RESET = 0,
  139. IPC_STR_PAUSE = 1,
  140. IPC_STR_RESUME = 2,
  141. IPC_STR_STAGE_MESSAGE = 3,
  142. IPC_STR_NOTIFICATION = 4,
  143. IPC_STR_MAX_MESSAGE
  144. };
  145. /* Stream Stage Message Types */
  146. enum ipc_stg_operation {
  147. IPC_STG_GET_VOLUME = 0,
  148. IPC_STG_SET_VOLUME,
  149. IPC_STG_SET_WRITE_POSITION,
  150. IPC_STG_SET_FX_ENABLE,
  151. IPC_STG_SET_FX_DISABLE,
  152. IPC_STG_SET_FX_GET_PARAM,
  153. IPC_STG_SET_FX_SET_PARAM,
  154. IPC_STG_SET_FX_GET_INFO,
  155. IPC_STG_MUTE_LOOPBACK,
  156. IPC_STG_MAX_MESSAGE
  157. };
  158. /* Stream Stage Message Types For Notification*/
  159. enum ipc_stg_operation_notify {
  160. IPC_POSITION_CHANGED = 0,
  161. IPC_STG_GLITCH,
  162. IPC_STG_MAX_NOTIFY
  163. };
  164. enum ipc_glitch_type {
  165. IPC_GLITCH_UNDERRUN = 1,
  166. IPC_GLITCH_DECODER_ERROR,
  167. IPC_GLITCH_DOUBLED_WRITE_POS,
  168. IPC_GLITCH_MAX
  169. };
  170. /* Debug Control */
  171. enum ipc_debug_operation {
  172. IPC_DEBUG_ENABLE_LOG = 0,
  173. IPC_DEBUG_DISABLE_LOG = 1,
  174. IPC_DEBUG_REQUEST_LOG_DUMP = 2,
  175. IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
  176. IPC_DEBUG_MAX_DEBUG_LOG
  177. };
  178. /* Firmware Ready */
  179. struct sst_hsw_ipc_fw_ready {
  180. u32 inbox_offset;
  181. u32 outbox_offset;
  182. u32 inbox_size;
  183. u32 outbox_size;
  184. u32 fw_info_size;
  185. u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
  186. } __attribute__((packed));
  187. struct sst_hsw_stream;
  188. struct sst_hsw;
  189. /* Stream infomation */
  190. struct sst_hsw_stream {
  191. /* configuration */
  192. struct sst_hsw_ipc_stream_alloc_req request;
  193. struct sst_hsw_ipc_stream_alloc_reply reply;
  194. struct sst_hsw_ipc_stream_free_req free_req;
  195. /* Mixer info */
  196. u32 mute_volume[SST_HSW_NO_CHANNELS];
  197. u32 mute[SST_HSW_NO_CHANNELS];
  198. /* runtime info */
  199. struct sst_hsw *hsw;
  200. int host_id;
  201. bool commited;
  202. bool running;
  203. /* Notification work */
  204. struct work_struct notify_work;
  205. u32 header;
  206. /* Position info from DSP */
  207. struct sst_hsw_ipc_stream_set_position wpos;
  208. struct sst_hsw_ipc_stream_get_position rpos;
  209. struct sst_hsw_ipc_stream_glitch_position glitch;
  210. /* Volume info */
  211. struct sst_hsw_ipc_volume_req vol_req;
  212. /* driver callback */
  213. u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
  214. void *pdata;
  215. /* record the fw read position when playback */
  216. snd_pcm_uframes_t old_position;
  217. bool play_silence;
  218. struct list_head node;
  219. };
  220. /* FW log ring information */
  221. struct sst_hsw_log_stream {
  222. dma_addr_t dma_addr;
  223. unsigned char *dma_area;
  224. unsigned char *ring_descr;
  225. int pages;
  226. int size;
  227. /* Notification work */
  228. struct work_struct notify_work;
  229. wait_queue_head_t readers_wait_q;
  230. struct mutex rw_mutex;
  231. u32 last_pos;
  232. u32 curr_pos;
  233. u32 reader_pos;
  234. /* fw log config */
  235. u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
  236. struct sst_hsw *hsw;
  237. };
  238. /* SST Haswell IPC data */
  239. struct sst_hsw {
  240. struct device *dev;
  241. struct sst_dsp *dsp;
  242. struct platform_device *pdev_pcm;
  243. /* FW config */
  244. struct sst_hsw_ipc_fw_ready fw_ready;
  245. struct sst_hsw_ipc_fw_version version;
  246. bool fw_done;
  247. struct sst_fw *sst_fw;
  248. /* stream */
  249. struct list_head stream_list;
  250. /* global mixer */
  251. struct sst_hsw_ipc_stream_info_reply mixer_info;
  252. enum sst_hsw_volume_curve curve_type;
  253. u32 curve_duration;
  254. u32 mute[SST_HSW_NO_CHANNELS];
  255. u32 mute_volume[SST_HSW_NO_CHANNELS];
  256. /* DX */
  257. struct sst_hsw_ipc_dx_reply dx;
  258. void *dx_context;
  259. dma_addr_t dx_context_paddr;
  260. enum sst_hsw_device_id dx_dev;
  261. enum sst_hsw_device_mclk dx_mclk;
  262. enum sst_hsw_device_mode dx_mode;
  263. u32 dx_clock_divider;
  264. /* boot */
  265. wait_queue_head_t boot_wait;
  266. bool boot_complete;
  267. bool shutdown;
  268. /* IPC messaging */
  269. struct sst_generic_ipc ipc;
  270. /* FW log stream */
  271. struct sst_hsw_log_stream log_stream;
  272. /* flags bit field to track module state when resume from RTD3,
  273. * each bit represent state (enabled/disabled) of single module */
  274. u32 enabled_modules_rtd3;
  275. /* buffer to store parameter lines */
  276. u32 param_idx_w; /* write index */
  277. u32 param_idx_r; /* read index */
  278. u8 param_buf[WAVES_PARAM_LINES][WAVES_PARAM_COUNT];
  279. };
  280. #define CREATE_TRACE_POINTS
  281. #include <trace/events/hswadsp.h>
  282. static inline u32 msg_get_global_type(u32 msg)
  283. {
  284. return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
  285. }
  286. static inline u32 msg_get_global_reply(u32 msg)
  287. {
  288. return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
  289. }
  290. static inline u32 msg_get_stream_type(u32 msg)
  291. {
  292. return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
  293. }
  294. static inline u32 msg_get_stage_type(u32 msg)
  295. {
  296. return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
  297. }
  298. static inline u32 msg_get_stream_id(u32 msg)
  299. {
  300. return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
  301. }
  302. static inline u32 msg_get_notify_reason(u32 msg)
  303. {
  304. return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
  305. }
  306. static inline u32 msg_get_module_operation(u32 msg)
  307. {
  308. return (msg & IPC_MODULE_OPERATION_MASK) >> IPC_MODULE_OPERATION_SHIFT;
  309. }
  310. static inline u32 msg_get_module_id(u32 msg)
  311. {
  312. return (msg & IPC_MODULE_ID_MASK) >> IPC_MODULE_ID_SHIFT;
  313. }
  314. u32 create_channel_map(enum sst_hsw_channel_config config)
  315. {
  316. switch (config) {
  317. case SST_HSW_CHANNEL_CONFIG_MONO:
  318. return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
  319. case SST_HSW_CHANNEL_CONFIG_STEREO:
  320. return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
  321. | (SST_HSW_CHANNEL_RIGHT << 4));
  322. case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
  323. return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
  324. | (SST_HSW_CHANNEL_RIGHT << 4)
  325. | (SST_HSW_CHANNEL_LFE << 8 ));
  326. case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
  327. return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
  328. | (SST_HSW_CHANNEL_CENTER << 4)
  329. | (SST_HSW_CHANNEL_RIGHT << 8));
  330. case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
  331. return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
  332. | (SST_HSW_CHANNEL_CENTER << 4)
  333. | (SST_HSW_CHANNEL_RIGHT << 8)
  334. | (SST_HSW_CHANNEL_LFE << 12));
  335. case SST_HSW_CHANNEL_CONFIG_QUATRO:
  336. return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
  337. | (SST_HSW_CHANNEL_RIGHT << 4)
  338. | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
  339. | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
  340. case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
  341. return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
  342. | (SST_HSW_CHANNEL_CENTER << 4)
  343. | (SST_HSW_CHANNEL_RIGHT << 8)
  344. | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
  345. case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
  346. return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
  347. | (SST_HSW_CHANNEL_CENTER << 4)
  348. | (SST_HSW_CHANNEL_RIGHT << 8)
  349. | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
  350. | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
  351. case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
  352. return (0xFF000000 | SST_HSW_CHANNEL_CENTER
  353. | (SST_HSW_CHANNEL_LEFT << 4)
  354. | (SST_HSW_CHANNEL_RIGHT << 8)
  355. | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
  356. | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
  357. | (SST_HSW_CHANNEL_LFE << 20));
  358. case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
  359. return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
  360. | (SST_HSW_CHANNEL_LEFT << 4));
  361. default:
  362. return 0xFFFFFFFF;
  363. }
  364. }
  365. static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
  366. int stream_id)
  367. {
  368. struct sst_hsw_stream *stream;
  369. list_for_each_entry(stream, &hsw->stream_list, node) {
  370. if (stream->reply.stream_hw_id == stream_id)
  371. return stream;
  372. }
  373. return NULL;
  374. }
  375. static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
  376. {
  377. struct sst_hsw_ipc_fw_ready fw_ready;
  378. u32 offset;
  379. u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
  380. char *tmp[5], *pinfo;
  381. int i = 0;
  382. offset = (header & 0x1FFFFFFF) << 3;
  383. dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
  384. header, offset);
  385. /* copy data from the DSP FW ready offset */
  386. sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
  387. sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
  388. fw_ready.inbox_size, fw_ready.outbox_offset,
  389. fw_ready.outbox_size);
  390. hsw->boot_complete = true;
  391. wake_up(&hsw->boot_wait);
  392. dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
  393. fw_ready.inbox_offset, fw_ready.inbox_size);
  394. dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
  395. fw_ready.outbox_offset, fw_ready.outbox_size);
  396. if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
  397. fw_ready.fw_info[fw_ready.fw_info_size] = 0;
  398. dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
  399. /* log the FW version info got from the mailbox here. */
  400. memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
  401. pinfo = &fw_info[0];
  402. for (i = 0; i < ARRAY_SIZE(tmp); i++)
  403. tmp[i] = strsep(&pinfo, " ");
  404. dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
  405. "version: %s.%s, build %s, source commit id: %s\n",
  406. tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
  407. }
  408. }
  409. static void hsw_notification_work(struct work_struct *work)
  410. {
  411. struct sst_hsw_stream *stream = container_of(work,
  412. struct sst_hsw_stream, notify_work);
  413. struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
  414. struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
  415. struct sst_hsw *hsw = stream->hsw;
  416. u32 reason;
  417. reason = msg_get_notify_reason(stream->header);
  418. switch (reason) {
  419. case IPC_STG_GLITCH:
  420. trace_ipc_notification("DSP stream under/overrun",
  421. stream->reply.stream_hw_id);
  422. sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
  423. dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
  424. glitch->glitch_type, glitch->present_pos,
  425. glitch->write_pos);
  426. break;
  427. case IPC_POSITION_CHANGED:
  428. trace_ipc_notification("DSP stream position changed for",
  429. stream->reply.stream_hw_id);
  430. sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
  431. if (stream->notify_position)
  432. stream->notify_position(stream, stream->pdata);
  433. break;
  434. default:
  435. dev_err(hsw->dev, "error: unknown notification 0x%x\n",
  436. stream->header);
  437. break;
  438. }
  439. /* tell DSP that notification has been handled */
  440. sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,
  441. SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
  442. /* unmask busy interrupt */
  443. sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
  444. }
  445. static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
  446. {
  447. struct sst_hsw_stream *stream;
  448. u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
  449. u32 stream_id = msg_get_stream_id(header);
  450. u32 stream_msg = msg_get_stream_type(header);
  451. stream = get_stream_by_id(hsw, stream_id);
  452. if (stream == NULL)
  453. return;
  454. switch (stream_msg) {
  455. case IPC_STR_STAGE_MESSAGE:
  456. case IPC_STR_NOTIFICATION:
  457. break;
  458. case IPC_STR_RESET:
  459. trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
  460. break;
  461. case IPC_STR_PAUSE:
  462. stream->running = false;
  463. trace_ipc_notification("stream paused",
  464. stream->reply.stream_hw_id);
  465. break;
  466. case IPC_STR_RESUME:
  467. stream->running = true;
  468. trace_ipc_notification("stream running",
  469. stream->reply.stream_hw_id);
  470. break;
  471. }
  472. }
  473. static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
  474. {
  475. struct ipc_message *msg;
  476. u32 reply = msg_get_global_reply(header);
  477. trace_ipc_reply("processing -->", header);
  478. msg = sst_ipc_reply_find_msg(&hsw->ipc, header);
  479. if (msg == NULL) {
  480. trace_ipc_error("error: can't find message header", header);
  481. return -EIO;
  482. }
  483. /* first process the header */
  484. switch (reply) {
  485. case IPC_GLB_REPLY_PENDING:
  486. trace_ipc_pending_reply("received", header);
  487. msg->pending = true;
  488. hsw->ipc.pending = true;
  489. return 1;
  490. case IPC_GLB_REPLY_SUCCESS:
  491. if (msg->pending) {
  492. trace_ipc_pending_reply("completed", header);
  493. sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
  494. msg->rx_size);
  495. hsw->ipc.pending = false;
  496. } else {
  497. /* copy data from the DSP */
  498. sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
  499. msg->rx_size);
  500. }
  501. break;
  502. /* these will be rare - but useful for debug */
  503. case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
  504. trace_ipc_error("error: unknown message type", header);
  505. msg->errno = -EBADMSG;
  506. break;
  507. case IPC_GLB_REPLY_OUT_OF_RESOURCES:
  508. trace_ipc_error("error: out of resources", header);
  509. msg->errno = -ENOMEM;
  510. break;
  511. case IPC_GLB_REPLY_BUSY:
  512. trace_ipc_error("error: reply busy", header);
  513. msg->errno = -EBUSY;
  514. break;
  515. case IPC_GLB_REPLY_FAILURE:
  516. trace_ipc_error("error: reply failure", header);
  517. msg->errno = -EINVAL;
  518. break;
  519. case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
  520. trace_ipc_error("error: stage uninitialized", header);
  521. msg->errno = -EINVAL;
  522. break;
  523. case IPC_GLB_REPLY_NOT_FOUND:
  524. trace_ipc_error("error: reply not found", header);
  525. msg->errno = -EINVAL;
  526. break;
  527. case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
  528. trace_ipc_error("error: source not started", header);
  529. msg->errno = -EINVAL;
  530. break;
  531. case IPC_GLB_REPLY_INVALID_REQUEST:
  532. trace_ipc_error("error: invalid request", header);
  533. msg->errno = -EINVAL;
  534. break;
  535. case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
  536. trace_ipc_error("error: invalid parameter", header);
  537. msg->errno = -EINVAL;
  538. break;
  539. default:
  540. trace_ipc_error("error: unknown reply", header);
  541. msg->errno = -EINVAL;
  542. break;
  543. }
  544. /* update any stream states */
  545. if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
  546. hsw_stream_update(hsw, msg);
  547. /* wake up and return the error if we have waiters on this message ? */
  548. list_del(&msg->list);
  549. sst_ipc_tx_msg_reply_complete(&hsw->ipc, msg);
  550. return 1;
  551. }
  552. static int hsw_module_message(struct sst_hsw *hsw, u32 header)
  553. {
  554. u32 operation, module_id;
  555. int handled = 0;
  556. operation = msg_get_module_operation(header);
  557. module_id = msg_get_module_id(header);
  558. dev_dbg(hsw->dev, "received module message header: 0x%8.8x\n",
  559. header);
  560. dev_dbg(hsw->dev, "operation: 0x%8.8x module_id: 0x%8.8x\n",
  561. operation, module_id);
  562. switch (operation) {
  563. case IPC_MODULE_NOTIFICATION:
  564. dev_dbg(hsw->dev, "module notification received");
  565. handled = 1;
  566. break;
  567. default:
  568. handled = hsw_process_reply(hsw, header);
  569. break;
  570. }
  571. return handled;
  572. }
  573. static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
  574. {
  575. u32 stream_msg, stream_id, stage_type;
  576. struct sst_hsw_stream *stream;
  577. int handled = 0;
  578. stream_msg = msg_get_stream_type(header);
  579. stream_id = msg_get_stream_id(header);
  580. stage_type = msg_get_stage_type(header);
  581. stream = get_stream_by_id(hsw, stream_id);
  582. if (stream == NULL)
  583. return handled;
  584. stream->header = header;
  585. switch (stream_msg) {
  586. case IPC_STR_STAGE_MESSAGE:
  587. dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
  588. header);
  589. break;
  590. case IPC_STR_NOTIFICATION:
  591. schedule_work(&stream->notify_work);
  592. break;
  593. default:
  594. /* handle pending message complete request */
  595. handled = hsw_process_reply(hsw, header);
  596. break;
  597. }
  598. return handled;
  599. }
  600. static int hsw_log_message(struct sst_hsw *hsw, u32 header)
  601. {
  602. u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
  603. struct sst_hsw_log_stream *stream = &hsw->log_stream;
  604. int ret = 1;
  605. if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
  606. dev_err(hsw->dev,
  607. "error: log msg not implemented 0x%8.8x\n", header);
  608. return 0;
  609. }
  610. mutex_lock(&stream->rw_mutex);
  611. stream->last_pos = stream->curr_pos;
  612. sst_dsp_inbox_read(
  613. hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
  614. mutex_unlock(&stream->rw_mutex);
  615. schedule_work(&stream->notify_work);
  616. return ret;
  617. }
  618. static int hsw_process_notification(struct sst_hsw *hsw)
  619. {
  620. struct sst_dsp *sst = hsw->dsp;
  621. u32 type, header;
  622. int handled = 1;
  623. header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
  624. type = msg_get_global_type(header);
  625. trace_ipc_request("processing -->", header);
  626. /* FW Ready is a special case */
  627. if (!hsw->boot_complete && header & IPC_FW_READY) {
  628. hsw_fw_ready(hsw, header);
  629. return handled;
  630. }
  631. switch (type) {
  632. case IPC_GLB_GET_FW_VERSION:
  633. case IPC_GLB_ALLOCATE_STREAM:
  634. case IPC_GLB_FREE_STREAM:
  635. case IPC_GLB_GET_FW_CAPABILITIES:
  636. case IPC_GLB_REQUEST_DUMP:
  637. case IPC_GLB_GET_DEVICE_FORMATS:
  638. case IPC_GLB_SET_DEVICE_FORMATS:
  639. case IPC_GLB_ENTER_DX_STATE:
  640. case IPC_GLB_GET_MIXER_STREAM_INFO:
  641. case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
  642. case IPC_GLB_RESTORE_CONTEXT:
  643. case IPC_GLB_SHORT_REPLY:
  644. dev_err(hsw->dev, "error: message type %d header 0x%x\n",
  645. type, header);
  646. break;
  647. case IPC_GLB_STREAM_MESSAGE:
  648. handled = hsw_stream_message(hsw, header);
  649. break;
  650. case IPC_GLB_DEBUG_LOG_MESSAGE:
  651. handled = hsw_log_message(hsw, header);
  652. break;
  653. case IPC_GLB_MODULE_OPERATION:
  654. handled = hsw_module_message(hsw, header);
  655. break;
  656. default:
  657. dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
  658. type, header);
  659. break;
  660. }
  661. return handled;
  662. }
  663. static irqreturn_t hsw_irq_thread(int irq, void *context)
  664. {
  665. struct sst_dsp *sst = (struct sst_dsp *) context;
  666. struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
  667. struct sst_generic_ipc *ipc = &hsw->ipc;
  668. u32 ipcx, ipcd;
  669. unsigned long flags;
  670. spin_lock_irqsave(&sst->spinlock, flags);
  671. ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
  672. ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
  673. /* reply message from DSP */
  674. if (ipcx & SST_IPCX_DONE) {
  675. /* Handle Immediate reply from DSP Core */
  676. hsw_process_reply(hsw, ipcx);
  677. /* clear DONE bit - tell DSP we have completed */
  678. sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
  679. SST_IPCX_DONE, 0);
  680. /* unmask Done interrupt */
  681. sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
  682. SST_IMRX_DONE, 0);
  683. }
  684. /* new message from DSP */
  685. if (ipcd & SST_IPCD_BUSY) {
  686. /* Handle Notification and Delayed reply from DSP Core */
  687. hsw_process_notification(hsw);
  688. /* clear BUSY bit and set DONE bit - accept new messages */
  689. sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
  690. SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
  691. /* unmask busy interrupt */
  692. sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
  693. SST_IMRX_BUSY, 0);
  694. }
  695. spin_unlock_irqrestore(&sst->spinlock, flags);
  696. /* continue to send any remaining messages... */
  697. schedule_work(&ipc->kwork);
  698. return IRQ_HANDLED;
  699. }
  700. int sst_hsw_fw_get_version(struct sst_hsw *hsw,
  701. struct sst_hsw_ipc_fw_version *version)
  702. {
  703. int ret;
  704. ret = sst_ipc_tx_message_wait(&hsw->ipc,
  705. IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
  706. NULL, 0, version, sizeof(*version));
  707. if (ret < 0)
  708. dev_err(hsw->dev, "error: get version failed\n");
  709. return ret;
  710. }
  711. /* Mixer Controls */
  712. int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  713. u32 stage_id, u32 channel, u32 *volume)
  714. {
  715. if (channel > 1)
  716. return -EINVAL;
  717. sst_dsp_read(hsw->dsp, volume,
  718. stream->reply.volume_register_address[channel],
  719. sizeof(*volume));
  720. return 0;
  721. }
  722. /* stream volume */
  723. int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
  724. struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
  725. {
  726. struct sst_hsw_ipc_volume_req *req;
  727. u32 header;
  728. int ret;
  729. trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
  730. if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
  731. return -EINVAL;
  732. header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
  733. IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
  734. header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
  735. header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
  736. header |= (stage_id << IPC_STG_ID_SHIFT);
  737. req = &stream->vol_req;
  738. req->target_volume = volume;
  739. /* set both at same time ? */
  740. if (channel == SST_HSW_CHANNELS_ALL) {
  741. if (hsw->mute[0] && hsw->mute[1]) {
  742. hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
  743. return 0;
  744. } else if (hsw->mute[0])
  745. req->channel = 1;
  746. else if (hsw->mute[1])
  747. req->channel = 0;
  748. else
  749. req->channel = SST_HSW_CHANNELS_ALL;
  750. } else {
  751. /* set only 1 channel */
  752. if (hsw->mute[channel]) {
  753. hsw->mute_volume[channel] = volume;
  754. return 0;
  755. }
  756. req->channel = channel;
  757. }
  758. ret = sst_ipc_tx_message_wait(&hsw->ipc, header, req,
  759. sizeof(*req), NULL, 0);
  760. if (ret < 0) {
  761. dev_err(hsw->dev, "error: set stream volume failed\n");
  762. return ret;
  763. }
  764. return 0;
  765. }
  766. int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
  767. u32 *volume)
  768. {
  769. if (channel > 1)
  770. return -EINVAL;
  771. sst_dsp_read(hsw->dsp, volume,
  772. hsw->mixer_info.volume_register_address[channel],
  773. sizeof(*volume));
  774. return 0;
  775. }
  776. /* global mixer volume */
  777. int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
  778. u32 volume)
  779. {
  780. struct sst_hsw_ipc_volume_req req;
  781. u32 header;
  782. int ret;
  783. trace_ipc_request("set mixer volume", volume);
  784. if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
  785. return -EINVAL;
  786. /* set both at same time ? */
  787. if (channel == SST_HSW_CHANNELS_ALL) {
  788. if (hsw->mute[0] && hsw->mute[1]) {
  789. hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
  790. return 0;
  791. } else if (hsw->mute[0])
  792. req.channel = 1;
  793. else if (hsw->mute[1])
  794. req.channel = 0;
  795. else
  796. req.channel = SST_HSW_CHANNELS_ALL;
  797. } else {
  798. /* set only 1 channel */
  799. if (hsw->mute[channel]) {
  800. hsw->mute_volume[channel] = volume;
  801. return 0;
  802. }
  803. req.channel = channel;
  804. }
  805. header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
  806. IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
  807. header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
  808. header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
  809. header |= (stage_id << IPC_STG_ID_SHIFT);
  810. req.curve_duration = hsw->curve_duration;
  811. req.curve_type = hsw->curve_type;
  812. req.target_volume = volume;
  813. ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &req,
  814. sizeof(req), NULL, 0);
  815. if (ret < 0) {
  816. dev_err(hsw->dev, "error: set mixer volume failed\n");
  817. return ret;
  818. }
  819. return 0;
  820. }
  821. /* Stream API */
  822. struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
  823. u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
  824. void *data)
  825. {
  826. struct sst_hsw_stream *stream;
  827. struct sst_dsp *sst = hsw->dsp;
  828. unsigned long flags;
  829. stream = kzalloc(sizeof(*stream), GFP_KERNEL);
  830. if (stream == NULL)
  831. return NULL;
  832. spin_lock_irqsave(&sst->spinlock, flags);
  833. stream->reply.stream_hw_id = INVALID_STREAM_HW_ID;
  834. list_add(&stream->node, &hsw->stream_list);
  835. stream->notify_position = notify_position;
  836. stream->pdata = data;
  837. stream->hsw = hsw;
  838. stream->host_id = id;
  839. /* work to process notification messages */
  840. INIT_WORK(&stream->notify_work, hsw_notification_work);
  841. spin_unlock_irqrestore(&sst->spinlock, flags);
  842. return stream;
  843. }
  844. int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
  845. {
  846. u32 header;
  847. int ret = 0;
  848. struct sst_dsp *sst = hsw->dsp;
  849. unsigned long flags;
  850. if (!stream) {
  851. dev_warn(hsw->dev, "warning: stream is NULL, no stream to free, ignore it.\n");
  852. return 0;
  853. }
  854. /* dont free DSP streams that are not commited */
  855. if (!stream->commited)
  856. goto out;
  857. trace_ipc_request("stream free", stream->host_id);
  858. stream->free_req.stream_id = stream->reply.stream_hw_id;
  859. header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
  860. ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &stream->free_req,
  861. sizeof(stream->free_req), NULL, 0);
  862. if (ret < 0) {
  863. dev_err(hsw->dev, "error: free stream %d failed\n",
  864. stream->free_req.stream_id);
  865. return -EAGAIN;
  866. }
  867. trace_hsw_stream_free_req(stream, &stream->free_req);
  868. out:
  869. cancel_work_sync(&stream->notify_work);
  870. spin_lock_irqsave(&sst->spinlock, flags);
  871. list_del(&stream->node);
  872. kfree(stream);
  873. spin_unlock_irqrestore(&sst->spinlock, flags);
  874. return ret;
  875. }
  876. int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
  877. struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
  878. {
  879. if (stream->commited) {
  880. dev_err(hsw->dev, "error: stream committed for set bits\n");
  881. return -EINVAL;
  882. }
  883. stream->request.format.bitdepth = bits;
  884. return 0;
  885. }
  886. int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
  887. struct sst_hsw_stream *stream, int channels)
  888. {
  889. if (stream->commited) {
  890. dev_err(hsw->dev, "error: stream committed for set channels\n");
  891. return -EINVAL;
  892. }
  893. stream->request.format.ch_num = channels;
  894. return 0;
  895. }
  896. int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
  897. struct sst_hsw_stream *stream, int rate)
  898. {
  899. if (stream->commited) {
  900. dev_err(hsw->dev, "error: stream committed for set rate\n");
  901. return -EINVAL;
  902. }
  903. stream->request.format.frequency = rate;
  904. return 0;
  905. }
  906. int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
  907. struct sst_hsw_stream *stream, u32 map,
  908. enum sst_hsw_channel_config config)
  909. {
  910. if (stream->commited) {
  911. dev_err(hsw->dev, "error: stream committed for set map\n");
  912. return -EINVAL;
  913. }
  914. stream->request.format.map = map;
  915. stream->request.format.config = config;
  916. return 0;
  917. }
  918. int sst_hsw_stream_set_style(struct sst_hsw *hsw,
  919. struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
  920. {
  921. if (stream->commited) {
  922. dev_err(hsw->dev, "error: stream committed for set style\n");
  923. return -EINVAL;
  924. }
  925. stream->request.format.style = style;
  926. return 0;
  927. }
  928. int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
  929. struct sst_hsw_stream *stream, u32 bits)
  930. {
  931. if (stream->commited) {
  932. dev_err(hsw->dev, "error: stream committed for set valid bits\n");
  933. return -EINVAL;
  934. }
  935. stream->request.format.valid_bit = bits;
  936. return 0;
  937. }
  938. /* Stream Configuration */
  939. int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  940. enum sst_hsw_stream_path_id path_id,
  941. enum sst_hsw_stream_type stream_type,
  942. enum sst_hsw_stream_format format_id)
  943. {
  944. if (stream->commited) {
  945. dev_err(hsw->dev, "error: stream committed for set format\n");
  946. return -EINVAL;
  947. }
  948. stream->request.path_id = path_id;
  949. stream->request.stream_type = stream_type;
  950. stream->request.format_id = format_id;
  951. trace_hsw_stream_alloc_request(stream, &stream->request);
  952. return 0;
  953. }
  954. int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  955. u32 ring_pt_address, u32 num_pages,
  956. u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
  957. {
  958. if (stream->commited) {
  959. dev_err(hsw->dev, "error: stream committed for buffer\n");
  960. return -EINVAL;
  961. }
  962. stream->request.ringinfo.ring_pt_address = ring_pt_address;
  963. stream->request.ringinfo.num_pages = num_pages;
  964. stream->request.ringinfo.ring_size = ring_size;
  965. stream->request.ringinfo.ring_offset = ring_offset;
  966. stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
  967. trace_hsw_stream_buffer(stream);
  968. return 0;
  969. }
  970. int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
  971. struct sst_hsw_stream *stream, struct sst_module_runtime *runtime)
  972. {
  973. struct sst_hsw_module_map *map = &stream->request.map;
  974. struct sst_dsp *dsp = sst_hsw_get_dsp(hsw);
  975. struct sst_module *module = runtime->module;
  976. if (stream->commited) {
  977. dev_err(hsw->dev, "error: stream committed for set module\n");
  978. return -EINVAL;
  979. }
  980. /* only support initial module atm */
  981. map->module_entries_count = 1;
  982. map->module_entries[0].module_id = module->id;
  983. map->module_entries[0].entry_point = module->entry;
  984. stream->request.persistent_mem.offset =
  985. sst_dsp_get_offset(dsp, runtime->persistent_offset, SST_MEM_DRAM);
  986. stream->request.persistent_mem.size = module->persistent_size;
  987. stream->request.scratch_mem.offset =
  988. sst_dsp_get_offset(dsp, dsp->scratch_offset, SST_MEM_DRAM);
  989. stream->request.scratch_mem.size = dsp->scratch_size;
  990. dev_dbg(hsw->dev, "module %d runtime %d using:\n", module->id,
  991. runtime->id);
  992. dev_dbg(hsw->dev, " persistent offset 0x%x bytes 0x%x\n",
  993. stream->request.persistent_mem.offset,
  994. stream->request.persistent_mem.size);
  995. dev_dbg(hsw->dev, " scratch offset 0x%x bytes 0x%x\n",
  996. stream->request.scratch_mem.offset,
  997. stream->request.scratch_mem.size);
  998. return 0;
  999. }
  1000. int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
  1001. {
  1002. struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
  1003. struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
  1004. u32 header;
  1005. int ret;
  1006. if (!stream) {
  1007. dev_warn(hsw->dev, "warning: stream is NULL, no stream to commit, ignore it.\n");
  1008. return 0;
  1009. }
  1010. if (stream->commited) {
  1011. dev_warn(hsw->dev, "warning: stream is already committed, ignore it.\n");
  1012. return 0;
  1013. }
  1014. trace_ipc_request("stream alloc", stream->host_id);
  1015. header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
  1016. ret = sst_ipc_tx_message_wait(&hsw->ipc, header, str_req,
  1017. sizeof(*str_req), reply, sizeof(*reply));
  1018. if (ret < 0) {
  1019. dev_err(hsw->dev, "error: stream commit failed\n");
  1020. return ret;
  1021. }
  1022. stream->commited = 1;
  1023. trace_hsw_stream_alloc_reply(stream);
  1024. return 0;
  1025. }
  1026. snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
  1027. struct sst_hsw_stream *stream)
  1028. {
  1029. return stream->old_position;
  1030. }
  1031. void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
  1032. struct sst_hsw_stream *stream, snd_pcm_uframes_t val)
  1033. {
  1034. stream->old_position = val;
  1035. }
  1036. bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
  1037. struct sst_hsw_stream *stream)
  1038. {
  1039. return stream->play_silence;
  1040. }
  1041. void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
  1042. struct sst_hsw_stream *stream, bool val)
  1043. {
  1044. stream->play_silence = val;
  1045. }
  1046. /* Stream Information - these calls could be inline but we want the IPC
  1047. ABI to be opaque to client PCM drivers to cope with any future ABI changes */
  1048. int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
  1049. {
  1050. struct sst_hsw_ipc_stream_info_reply *reply;
  1051. u32 header;
  1052. int ret;
  1053. reply = &hsw->mixer_info;
  1054. header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
  1055. trace_ipc_request("get global mixer info", 0);
  1056. ret = sst_ipc_tx_message_wait(&hsw->ipc, header, NULL, 0,
  1057. reply, sizeof(*reply));
  1058. if (ret < 0) {
  1059. dev_err(hsw->dev, "error: get stream info failed\n");
  1060. return ret;
  1061. }
  1062. trace_hsw_mixer_info_reply(reply);
  1063. return 0;
  1064. }
  1065. /* Send stream command */
  1066. static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
  1067. int stream_id, int wait)
  1068. {
  1069. u32 header;
  1070. header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
  1071. header |= (stream_id << IPC_STR_ID_SHIFT);
  1072. if (wait)
  1073. return sst_ipc_tx_message_wait(&hsw->ipc, header,
  1074. NULL, 0, NULL, 0);
  1075. else
  1076. return sst_ipc_tx_message_nowait(&hsw->ipc, header, NULL, 0);
  1077. }
  1078. /* Stream ALSA trigger operations */
  1079. int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  1080. int wait)
  1081. {
  1082. int ret;
  1083. if (!stream) {
  1084. dev_warn(hsw->dev, "warning: stream is NULL, no stream to pause, ignore it.\n");
  1085. return 0;
  1086. }
  1087. trace_ipc_request("stream pause", stream->reply.stream_hw_id);
  1088. ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
  1089. stream->reply.stream_hw_id, wait);
  1090. if (ret < 0)
  1091. dev_err(hsw->dev, "error: failed to pause stream %d\n",
  1092. stream->reply.stream_hw_id);
  1093. return ret;
  1094. }
  1095. int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  1096. int wait)
  1097. {
  1098. int ret;
  1099. if (!stream) {
  1100. dev_warn(hsw->dev, "warning: stream is NULL, no stream to resume, ignore it.\n");
  1101. return 0;
  1102. }
  1103. trace_ipc_request("stream resume", stream->reply.stream_hw_id);
  1104. ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
  1105. stream->reply.stream_hw_id, wait);
  1106. if (ret < 0)
  1107. dev_err(hsw->dev, "error: failed to resume stream %d\n",
  1108. stream->reply.stream_hw_id);
  1109. return ret;
  1110. }
  1111. int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
  1112. {
  1113. int ret, tries = 10;
  1114. if (!stream) {
  1115. dev_warn(hsw->dev, "warning: stream is NULL, no stream to reset, ignore it.\n");
  1116. return 0;
  1117. }
  1118. /* dont reset streams that are not commited */
  1119. if (!stream->commited)
  1120. return 0;
  1121. /* wait for pause to complete before we reset the stream */
  1122. while (stream->running && --tries)
  1123. msleep(1);
  1124. if (!tries) {
  1125. dev_err(hsw->dev, "error: reset stream %d still running\n",
  1126. stream->reply.stream_hw_id);
  1127. return -EINVAL;
  1128. }
  1129. trace_ipc_request("stream reset", stream->reply.stream_hw_id);
  1130. ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
  1131. stream->reply.stream_hw_id, 1);
  1132. if (ret < 0)
  1133. dev_err(hsw->dev, "error: failed to reset stream %d\n",
  1134. stream->reply.stream_hw_id);
  1135. return ret;
  1136. }
  1137. /* Stream pointer positions */
  1138. u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
  1139. struct sst_hsw_stream *stream)
  1140. {
  1141. u32 rpos;
  1142. sst_dsp_read(hsw->dsp, &rpos,
  1143. stream->reply.read_position_register_address, sizeof(rpos));
  1144. return rpos;
  1145. }
  1146. /* Stream presentation (monotonic) positions */
  1147. u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
  1148. struct sst_hsw_stream *stream)
  1149. {
  1150. u64 ppos;
  1151. sst_dsp_read(hsw->dsp, &ppos,
  1152. stream->reply.presentation_position_register_address,
  1153. sizeof(ppos));
  1154. return ppos;
  1155. }
  1156. /* physical BE config */
  1157. int sst_hsw_device_set_config(struct sst_hsw *hsw,
  1158. enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
  1159. enum sst_hsw_device_mode mode, u32 clock_divider)
  1160. {
  1161. struct sst_hsw_ipc_device_config_req config;
  1162. u32 header;
  1163. int ret;
  1164. trace_ipc_request("set device config", dev);
  1165. hsw->dx_dev = config.ssp_interface = dev;
  1166. hsw->dx_mclk = config.clock_frequency = mclk;
  1167. hsw->dx_mode = config.mode = mode;
  1168. hsw->dx_clock_divider = config.clock_divider = clock_divider;
  1169. if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER)
  1170. config.channels = 4;
  1171. else
  1172. config.channels = 2;
  1173. trace_hsw_device_config_req(&config);
  1174. header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
  1175. ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &config,
  1176. sizeof(config), NULL, 0);
  1177. if (ret < 0)
  1178. dev_err(hsw->dev, "error: set device formats failed\n");
  1179. return ret;
  1180. }
  1181. EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
  1182. /* DX Config */
  1183. int sst_hsw_dx_set_state(struct sst_hsw *hsw,
  1184. enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
  1185. {
  1186. u32 header, state_;
  1187. int ret, item;
  1188. header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
  1189. state_ = state;
  1190. trace_ipc_request("PM enter Dx state", state);
  1191. ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &state_,
  1192. sizeof(state_), dx, sizeof(*dx));
  1193. if (ret < 0) {
  1194. dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
  1195. return ret;
  1196. }
  1197. for (item = 0; item < dx->entries_no; item++) {
  1198. dev_dbg(hsw->dev,
  1199. "Item[%d] offset[%x] - size[%x] - source[%x]\n",
  1200. item, dx->mem_info[item].offset,
  1201. dx->mem_info[item].size,
  1202. dx->mem_info[item].source);
  1203. }
  1204. dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
  1205. dx->entries_no, state);
  1206. return ret;
  1207. }
  1208. struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
  1209. int mod_id, int offset)
  1210. {
  1211. struct sst_dsp *dsp = hsw->dsp;
  1212. struct sst_module *module;
  1213. struct sst_module_runtime *runtime;
  1214. int err;
  1215. module = sst_module_get_from_id(dsp, mod_id);
  1216. if (module == NULL) {
  1217. dev_err(dsp->dev, "error: failed to get module %d for pcm\n",
  1218. mod_id);
  1219. return NULL;
  1220. }
  1221. runtime = sst_module_runtime_new(module, mod_id, NULL);
  1222. if (runtime == NULL) {
  1223. dev_err(dsp->dev, "error: failed to create module %d runtime\n",
  1224. mod_id);
  1225. return NULL;
  1226. }
  1227. err = sst_module_runtime_alloc_blocks(runtime, offset);
  1228. if (err < 0) {
  1229. dev_err(dsp->dev, "error: failed to alloc blocks for module %d runtime\n",
  1230. mod_id);
  1231. sst_module_runtime_free(runtime);
  1232. return NULL;
  1233. }
  1234. dev_dbg(dsp->dev, "runtime id %d created for module %d\n", runtime->id,
  1235. mod_id);
  1236. return runtime;
  1237. }
  1238. void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime)
  1239. {
  1240. sst_module_runtime_free_blocks(runtime);
  1241. sst_module_runtime_free(runtime);
  1242. }
  1243. #ifdef CONFIG_PM
  1244. static int sst_hsw_dx_state_dump(struct sst_hsw *hsw)
  1245. {
  1246. struct sst_dsp *sst = hsw->dsp;
  1247. u32 item, offset, size;
  1248. int ret = 0;
  1249. trace_ipc_request("PM state dump. Items #", SST_HSW_MAX_DX_REGIONS);
  1250. if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) {
  1251. dev_err(hsw->dev,
  1252. "error: number of FW context regions greater than %d\n",
  1253. SST_HSW_MAX_DX_REGIONS);
  1254. memset(&hsw->dx, 0, sizeof(hsw->dx));
  1255. return -EINVAL;
  1256. }
  1257. ret = sst_dsp_dma_get_channel(sst, 0);
  1258. if (ret < 0) {
  1259. dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
  1260. return ret;
  1261. }
  1262. /* set on-demond mode on engine 0 channel 3 */
  1263. sst_dsp_shim_update_bits(sst, SST_HMDC,
  1264. SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
  1265. SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
  1266. for (item = 0; item < hsw->dx.entries_no; item++) {
  1267. if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
  1268. && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
  1269. && hsw->dx.mem_info[item].offset <
  1270. DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
  1271. offset = hsw->dx.mem_info[item].offset
  1272. - DSP_DRAM_ADDR_OFFSET;
  1273. size = (hsw->dx.mem_info[item].size + 3) & (~3);
  1274. ret = sst_dsp_dma_copyfrom(sst, hsw->dx_context_paddr + offset,
  1275. sst->addr.lpe_base + offset, size);
  1276. if (ret < 0) {
  1277. dev_err(hsw->dev,
  1278. "error: FW context dump failed\n");
  1279. memset(&hsw->dx, 0, sizeof(hsw->dx));
  1280. goto out;
  1281. }
  1282. }
  1283. }
  1284. out:
  1285. sst_dsp_dma_put_channel(sst);
  1286. return ret;
  1287. }
  1288. static int sst_hsw_dx_state_restore(struct sst_hsw *hsw)
  1289. {
  1290. struct sst_dsp *sst = hsw->dsp;
  1291. u32 item, offset, size;
  1292. int ret;
  1293. for (item = 0; item < hsw->dx.entries_no; item++) {
  1294. if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
  1295. && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
  1296. && hsw->dx.mem_info[item].offset <
  1297. DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
  1298. offset = hsw->dx.mem_info[item].offset
  1299. - DSP_DRAM_ADDR_OFFSET;
  1300. size = (hsw->dx.mem_info[item].size + 3) & (~3);
  1301. ret = sst_dsp_dma_copyto(sst, sst->addr.lpe_base + offset,
  1302. hsw->dx_context_paddr + offset, size);
  1303. if (ret < 0) {
  1304. dev_err(hsw->dev,
  1305. "error: FW context restore failed\n");
  1306. return ret;
  1307. }
  1308. }
  1309. }
  1310. return 0;
  1311. }
  1312. int sst_hsw_dsp_load(struct sst_hsw *hsw)
  1313. {
  1314. struct sst_dsp *dsp = hsw->dsp;
  1315. struct sst_fw *sst_fw, *t;
  1316. int ret;
  1317. dev_dbg(hsw->dev, "loading audio DSP....");
  1318. ret = sst_dsp_wake(dsp);
  1319. if (ret < 0) {
  1320. dev_err(hsw->dev, "error: failed to wake audio DSP\n");
  1321. return -ENODEV;
  1322. }
  1323. ret = sst_dsp_dma_get_channel(dsp, 0);
  1324. if (ret < 0) {
  1325. dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
  1326. return ret;
  1327. }
  1328. list_for_each_entry_safe_reverse(sst_fw, t, &dsp->fw_list, list) {
  1329. ret = sst_fw_reload(sst_fw);
  1330. if (ret < 0) {
  1331. dev_err(hsw->dev, "error: SST FW reload failed\n");
  1332. sst_dsp_dma_put_channel(dsp);
  1333. return -ENOMEM;
  1334. }
  1335. }
  1336. ret = sst_block_alloc_scratch(hsw->dsp);
  1337. if (ret < 0)
  1338. return -EINVAL;
  1339. sst_dsp_dma_put_channel(dsp);
  1340. return 0;
  1341. }
  1342. static int sst_hsw_dsp_restore(struct sst_hsw *hsw)
  1343. {
  1344. struct sst_dsp *dsp = hsw->dsp;
  1345. int ret;
  1346. dev_dbg(hsw->dev, "restoring audio DSP....");
  1347. ret = sst_dsp_dma_get_channel(dsp, 0);
  1348. if (ret < 0) {
  1349. dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
  1350. return ret;
  1351. }
  1352. ret = sst_hsw_dx_state_restore(hsw);
  1353. if (ret < 0) {
  1354. dev_err(hsw->dev, "error: SST FW context restore failed\n");
  1355. sst_dsp_dma_put_channel(dsp);
  1356. return -ENOMEM;
  1357. }
  1358. sst_dsp_dma_put_channel(dsp);
  1359. /* wait for DSP boot completion */
  1360. sst_dsp_boot(dsp);
  1361. return ret;
  1362. }
  1363. int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw)
  1364. {
  1365. int ret;
  1366. dev_dbg(hsw->dev, "audio dsp runtime suspend\n");
  1367. ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx);
  1368. if (ret < 0)
  1369. return ret;
  1370. sst_dsp_stall(hsw->dsp);
  1371. ret = sst_hsw_dx_state_dump(hsw);
  1372. if (ret < 0)
  1373. return ret;
  1374. sst_ipc_drop_all(&hsw->ipc);
  1375. return 0;
  1376. }
  1377. int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw)
  1378. {
  1379. struct sst_fw *sst_fw, *t;
  1380. struct sst_dsp *dsp = hsw->dsp;
  1381. list_for_each_entry_safe(sst_fw, t, &dsp->fw_list, list) {
  1382. sst_fw_unload(sst_fw);
  1383. }
  1384. sst_block_free_scratch(dsp);
  1385. hsw->boot_complete = false;
  1386. sst_dsp_sleep(dsp);
  1387. return 0;
  1388. }
  1389. int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw)
  1390. {
  1391. struct device *dev = hsw->dev;
  1392. int ret;
  1393. dev_dbg(dev, "audio dsp runtime resume\n");
  1394. if (hsw->boot_complete)
  1395. return 1; /* tell caller no action is required */
  1396. ret = sst_hsw_dsp_restore(hsw);
  1397. if (ret < 0)
  1398. dev_err(dev, "error: audio DSP boot failure\n");
  1399. sst_hsw_init_module_state(hsw);
  1400. ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
  1401. msecs_to_jiffies(IPC_BOOT_MSECS));
  1402. if (ret == 0) {
  1403. dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
  1404. sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
  1405. sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
  1406. return -EIO;
  1407. }
  1408. /* Set ADSP SSP port settings - sadly the FW does not store SSP port
  1409. settings as part of the PM context. */
  1410. ret = sst_hsw_device_set_config(hsw, hsw->dx_dev, hsw->dx_mclk,
  1411. hsw->dx_mode, hsw->dx_clock_divider);
  1412. if (ret < 0)
  1413. dev_err(dev, "error: SSP re-initialization failed\n");
  1414. return ret;
  1415. }
  1416. #endif
  1417. struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
  1418. {
  1419. return hsw->dsp;
  1420. }
  1421. void sst_hsw_init_module_state(struct sst_hsw *hsw)
  1422. {
  1423. struct sst_module *module;
  1424. enum sst_hsw_module_id id;
  1425. /* the base fw contains several modules */
  1426. for (id = SST_HSW_MODULE_BASE_FW; id < SST_HSW_MAX_MODULE_ID; id++) {
  1427. module = sst_module_get_from_id(hsw->dsp, id);
  1428. if (module) {
  1429. /* module waves is active only after being enabled */
  1430. if (id == SST_HSW_MODULE_WAVES)
  1431. module->state = SST_MODULE_STATE_INITIALIZED;
  1432. else
  1433. module->state = SST_MODULE_STATE_ACTIVE;
  1434. }
  1435. }
  1436. }
  1437. bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id)
  1438. {
  1439. struct sst_module *module;
  1440. module = sst_module_get_from_id(hsw->dsp, module_id);
  1441. if (module == NULL || module->state == SST_MODULE_STATE_UNLOADED)
  1442. return false;
  1443. else
  1444. return true;
  1445. }
  1446. bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id)
  1447. {
  1448. struct sst_module *module;
  1449. module = sst_module_get_from_id(hsw->dsp, module_id);
  1450. if (module != NULL && module->state == SST_MODULE_STATE_ACTIVE)
  1451. return true;
  1452. else
  1453. return false;
  1454. }
  1455. void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
  1456. {
  1457. hsw->enabled_modules_rtd3 |= (1 << module_id);
  1458. }
  1459. void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id)
  1460. {
  1461. hsw->enabled_modules_rtd3 &= ~(1 << module_id);
  1462. }
  1463. bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
  1464. {
  1465. return hsw->enabled_modules_rtd3 & (1 << module_id);
  1466. }
  1467. void sst_hsw_reset_param_buf(struct sst_hsw *hsw)
  1468. {
  1469. hsw->param_idx_w = 0;
  1470. hsw->param_idx_r = 0;
  1471. memset((void *)hsw->param_buf, 0, sizeof(hsw->param_buf));
  1472. }
  1473. int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf)
  1474. {
  1475. /* save line to the first available position of param buffer */
  1476. if (hsw->param_idx_w > WAVES_PARAM_LINES - 1) {
  1477. dev_warn(hsw->dev, "warning: param buffer overflow!\n");
  1478. return -EPERM;
  1479. }
  1480. memcpy(hsw->param_buf[hsw->param_idx_w], buf, WAVES_PARAM_COUNT);
  1481. hsw->param_idx_w++;
  1482. return 0;
  1483. }
  1484. int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf)
  1485. {
  1486. u8 id = 0;
  1487. /* read the first matching line from param buffer */
  1488. while (hsw->param_idx_r < WAVES_PARAM_LINES) {
  1489. id = hsw->param_buf[hsw->param_idx_r][0];
  1490. hsw->param_idx_r++;
  1491. if (buf[0] == id) {
  1492. memcpy(buf, hsw->param_buf[hsw->param_idx_r],
  1493. WAVES_PARAM_COUNT);
  1494. break;
  1495. }
  1496. }
  1497. if (hsw->param_idx_r > WAVES_PARAM_LINES - 1) {
  1498. dev_dbg(hsw->dev, "end of buffer, roll to the beginning\n");
  1499. hsw->param_idx_r = 0;
  1500. return 0;
  1501. }
  1502. return 0;
  1503. }
  1504. int sst_hsw_launch_param_buf(struct sst_hsw *hsw)
  1505. {
  1506. int ret, idx;
  1507. if (!sst_hsw_is_module_active(hsw, SST_HSW_MODULE_WAVES)) {
  1508. dev_dbg(hsw->dev, "module waves is not active\n");
  1509. return 0;
  1510. }
  1511. /* put all param lines to DSP through ipc */
  1512. for (idx = 0; idx < hsw->param_idx_w; idx++) {
  1513. ret = sst_hsw_module_set_param(hsw,
  1514. SST_HSW_MODULE_WAVES, 0, hsw->param_buf[idx][0],
  1515. WAVES_PARAM_COUNT, hsw->param_buf[idx]);
  1516. if (ret < 0)
  1517. return ret;
  1518. }
  1519. return 0;
  1520. }
  1521. int sst_hsw_module_load(struct sst_hsw *hsw,
  1522. u32 module_id, u32 instance_id, char *name)
  1523. {
  1524. int ret = 0;
  1525. const struct firmware *fw = NULL;
  1526. struct sst_fw *hsw_sst_fw;
  1527. struct sst_module *module;
  1528. struct device *dev = hsw->dev;
  1529. struct sst_dsp *dsp = hsw->dsp;
  1530. dev_dbg(dev, "sst_hsw_module_load id=%d, name='%s'", module_id, name);
  1531. module = sst_module_get_from_id(dsp, module_id);
  1532. if (module == NULL) {
  1533. /* loading for the first time */
  1534. if (module_id == SST_HSW_MODULE_BASE_FW) {
  1535. /* for base module: use fw requested in acpi probe */
  1536. fw = dsp->pdata->fw;
  1537. if (!fw) {
  1538. dev_err(dev, "request Base fw failed\n");
  1539. return -ENODEV;
  1540. }
  1541. } else {
  1542. /* try and load any other optional modules if they are
  1543. * available. Use dev_info instead of dev_err in case
  1544. * request firmware failed */
  1545. ret = request_firmware(&fw, name, dev);
  1546. if (ret) {
  1547. dev_info(dev, "fw image %s not available(%d)\n",
  1548. name, ret);
  1549. return ret;
  1550. }
  1551. }
  1552. hsw_sst_fw = sst_fw_new(dsp, fw, hsw);
  1553. if (hsw_sst_fw == NULL) {
  1554. dev_err(dev, "error: failed to load firmware\n");
  1555. ret = -ENOMEM;
  1556. goto out;
  1557. }
  1558. module = sst_module_get_from_id(dsp, module_id);
  1559. if (module == NULL) {
  1560. dev_err(dev, "error: no module %d in firmware %s\n",
  1561. module_id, name);
  1562. }
  1563. } else
  1564. dev_info(dev, "module %d (%s) already loaded\n",
  1565. module_id, name);
  1566. out:
  1567. /* release fw, but base fw should be released by acpi driver */
  1568. if (fw && module_id != SST_HSW_MODULE_BASE_FW)
  1569. release_firmware(fw);
  1570. return ret;
  1571. }
  1572. int sst_hsw_module_enable(struct sst_hsw *hsw,
  1573. u32 module_id, u32 instance_id)
  1574. {
  1575. int ret;
  1576. u32 header = 0;
  1577. struct sst_hsw_ipc_module_config config;
  1578. struct sst_module *module;
  1579. struct sst_module_runtime *runtime;
  1580. struct device *dev = hsw->dev;
  1581. struct sst_dsp *dsp = hsw->dsp;
  1582. if (!sst_hsw_is_module_loaded(hsw, module_id)) {
  1583. dev_dbg(dev, "module %d not loaded\n", module_id);
  1584. return 0;
  1585. }
  1586. if (sst_hsw_is_module_active(hsw, module_id)) {
  1587. dev_info(dev, "module %d already enabled\n", module_id);
  1588. return 0;
  1589. }
  1590. module = sst_module_get_from_id(dsp, module_id);
  1591. if (module == NULL) {
  1592. dev_err(dev, "module %d not valid\n", module_id);
  1593. return -ENXIO;
  1594. }
  1595. runtime = sst_module_runtime_get_from_id(module, module_id);
  1596. if (runtime == NULL) {
  1597. dev_err(dev, "runtime %d not valid", module_id);
  1598. return -ENXIO;
  1599. }
  1600. header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
  1601. IPC_MODULE_OPERATION(IPC_MODULE_ENABLE) |
  1602. IPC_MODULE_ID(module_id);
  1603. dev_dbg(dev, "module enable header: %x\n", header);
  1604. config.map.module_entries_count = 1;
  1605. config.map.module_entries[0].module_id = module->id;
  1606. config.map.module_entries[0].entry_point = module->entry;
  1607. config.persistent_mem.offset =
  1608. sst_dsp_get_offset(dsp,
  1609. runtime->persistent_offset, SST_MEM_DRAM);
  1610. config.persistent_mem.size = module->persistent_size;
  1611. config.scratch_mem.offset =
  1612. sst_dsp_get_offset(dsp,
  1613. dsp->scratch_offset, SST_MEM_DRAM);
  1614. config.scratch_mem.size = module->scratch_size;
  1615. dev_dbg(dev, "mod %d enable p:%d @ %x, s:%d @ %x, ep: %x",
  1616. config.map.module_entries[0].module_id,
  1617. config.persistent_mem.size,
  1618. config.persistent_mem.offset,
  1619. config.scratch_mem.size, config.scratch_mem.offset,
  1620. config.map.module_entries[0].entry_point);
  1621. ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
  1622. &config, sizeof(config), NULL, 0);
  1623. if (ret < 0)
  1624. dev_err(dev, "ipc: module enable failed - %d\n", ret);
  1625. else
  1626. module->state = SST_MODULE_STATE_ACTIVE;
  1627. return ret;
  1628. }
  1629. int sst_hsw_module_disable(struct sst_hsw *hsw,
  1630. u32 module_id, u32 instance_id)
  1631. {
  1632. int ret;
  1633. u32 header;
  1634. struct sst_module *module;
  1635. struct device *dev = hsw->dev;
  1636. struct sst_dsp *dsp = hsw->dsp;
  1637. if (!sst_hsw_is_module_loaded(hsw, module_id)) {
  1638. dev_dbg(dev, "module %d not loaded\n", module_id);
  1639. return 0;
  1640. }
  1641. if (!sst_hsw_is_module_active(hsw, module_id)) {
  1642. dev_info(dev, "module %d already disabled\n", module_id);
  1643. return 0;
  1644. }
  1645. module = sst_module_get_from_id(dsp, module_id);
  1646. if (module == NULL) {
  1647. dev_err(dev, "module %d not valid\n", module_id);
  1648. return -ENXIO;
  1649. }
  1650. header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
  1651. IPC_MODULE_OPERATION(IPC_MODULE_DISABLE) |
  1652. IPC_MODULE_ID(module_id);
  1653. ret = sst_ipc_tx_message_wait(&hsw->ipc, header, NULL, 0, NULL, 0);
  1654. if (ret < 0)
  1655. dev_err(dev, "module disable failed - %d\n", ret);
  1656. else
  1657. module->state = SST_MODULE_STATE_INITIALIZED;
  1658. return ret;
  1659. }
  1660. int sst_hsw_module_set_param(struct sst_hsw *hsw,
  1661. u32 module_id, u32 instance_id, u32 parameter_id,
  1662. u32 param_size, char *param)
  1663. {
  1664. int ret;
  1665. u32 header = 0;
  1666. u32 payload_size = 0, transfer_parameter_size = 0;
  1667. struct sst_hsw_transfer_parameter *parameter;
  1668. struct device *dev = hsw->dev;
  1669. header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
  1670. IPC_MODULE_OPERATION(IPC_MODULE_SET_PARAMETER) |
  1671. IPC_MODULE_ID(module_id);
  1672. dev_dbg(dev, "sst_hsw_module_set_param header=%x\n", header);
  1673. payload_size = param_size +
  1674. sizeof(struct sst_hsw_transfer_parameter) -
  1675. sizeof(struct sst_hsw_transfer_list);
  1676. dev_dbg(dev, "parameter size : %d\n", param_size);
  1677. dev_dbg(dev, "payload size : %d\n", payload_size);
  1678. if (payload_size <= SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE) {
  1679. /* short parameter, mailbox can contain data */
  1680. dev_dbg(dev, "transfer parameter size : %d\n",
  1681. transfer_parameter_size);
  1682. transfer_parameter_size = ALIGN(payload_size, 4);
  1683. dev_dbg(dev, "transfer parameter aligned size : %d\n",
  1684. transfer_parameter_size);
  1685. parameter = kzalloc(transfer_parameter_size, GFP_KERNEL);
  1686. if (parameter == NULL)
  1687. return -ENOMEM;
  1688. memcpy(parameter->data, param, param_size);
  1689. } else {
  1690. dev_warn(dev, "transfer parameter size too large!");
  1691. return 0;
  1692. }
  1693. parameter->parameter_id = parameter_id;
  1694. parameter->data_size = param_size;
  1695. ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
  1696. parameter, transfer_parameter_size , NULL, 0);
  1697. if (ret < 0)
  1698. dev_err(dev, "ipc: module set parameter failed - %d\n", ret);
  1699. kfree(parameter);
  1700. return ret;
  1701. }
  1702. static struct sst_dsp_device hsw_dev = {
  1703. .thread = hsw_irq_thread,
  1704. .ops = &haswell_ops,
  1705. };
  1706. static void hsw_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
  1707. {
  1708. /* send the message */
  1709. sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
  1710. sst_dsp_ipc_msg_tx(ipc->dsp, msg->header);
  1711. }
  1712. static void hsw_shim_dbg(struct sst_generic_ipc *ipc, const char *text)
  1713. {
  1714. struct sst_dsp *sst = ipc->dsp;
  1715. u32 isr, ipcd, imrx, ipcx;
  1716. ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
  1717. isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
  1718. ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
  1719. imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
  1720. dev_err(ipc->dev,
  1721. "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
  1722. text, ipcx, isr, ipcd, imrx);
  1723. }
  1724. static void hsw_tx_data_copy(struct ipc_message *msg, char *tx_data,
  1725. size_t tx_size)
  1726. {
  1727. memcpy(msg->tx_data, tx_data, tx_size);
  1728. }
  1729. static u64 hsw_reply_msg_match(u64 header, u64 *mask)
  1730. {
  1731. /* clear reply bits & status bits */
  1732. header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
  1733. *mask = (u64)-1;
  1734. return header;
  1735. }
  1736. static bool hsw_is_dsp_busy(struct sst_dsp *dsp)
  1737. {
  1738. u64 ipcx;
  1739. ipcx = sst_dsp_shim_read_unlocked(dsp, SST_IPCX);
  1740. return (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE));
  1741. }
  1742. int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
  1743. {
  1744. struct sst_hsw_ipc_fw_version version;
  1745. struct sst_hsw *hsw;
  1746. struct sst_generic_ipc *ipc;
  1747. int ret;
  1748. dev_dbg(dev, "initialising Audio DSP IPC\n");
  1749. hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
  1750. if (hsw == NULL)
  1751. return -ENOMEM;
  1752. hsw->dev = dev;
  1753. ipc = &hsw->ipc;
  1754. ipc->dev = dev;
  1755. ipc->ops.tx_msg = hsw_tx_msg;
  1756. ipc->ops.shim_dbg = hsw_shim_dbg;
  1757. ipc->ops.tx_data_copy = hsw_tx_data_copy;
  1758. ipc->ops.reply_msg_match = hsw_reply_msg_match;
  1759. ipc->ops.is_dsp_busy = hsw_is_dsp_busy;
  1760. ipc->tx_data_max_size = IPC_MAX_MAILBOX_BYTES;
  1761. ipc->rx_data_max_size = IPC_MAX_MAILBOX_BYTES;
  1762. ret = sst_ipc_init(ipc);
  1763. if (ret != 0)
  1764. goto ipc_init_err;
  1765. INIT_LIST_HEAD(&hsw->stream_list);
  1766. init_waitqueue_head(&hsw->boot_wait);
  1767. hsw_dev.thread_context = hsw;
  1768. /* init SST shim */
  1769. hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
  1770. if (hsw->dsp == NULL) {
  1771. ret = -ENODEV;
  1772. goto dsp_new_err;
  1773. }
  1774. ipc->dsp = hsw->dsp;
  1775. /* allocate DMA buffer for context storage */
  1776. hsw->dx_context = dma_alloc_coherent(hsw->dsp->dma_dev,
  1777. SST_HSW_DX_CONTEXT_SIZE, &hsw->dx_context_paddr, GFP_KERNEL);
  1778. if (hsw->dx_context == NULL) {
  1779. ret = -ENOMEM;
  1780. goto dma_err;
  1781. }
  1782. /* keep the DSP in reset state for base FW loading */
  1783. sst_dsp_reset(hsw->dsp);
  1784. /* load base module and other modules in base firmware image */
  1785. ret = sst_hsw_module_load(hsw, SST_HSW_MODULE_BASE_FW, 0, "Base");
  1786. if (ret < 0)
  1787. goto fw_err;
  1788. /* try to load module waves */
  1789. sst_hsw_module_load(hsw, SST_HSW_MODULE_WAVES, 0, "intel/IntcPP01.bin");
  1790. /* allocate scratch mem regions */
  1791. ret = sst_block_alloc_scratch(hsw->dsp);
  1792. if (ret < 0)
  1793. goto boot_err;
  1794. /* init param buffer */
  1795. sst_hsw_reset_param_buf(hsw);
  1796. /* wait for DSP boot completion */
  1797. sst_dsp_boot(hsw->dsp);
  1798. ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
  1799. msecs_to_jiffies(IPC_BOOT_MSECS));
  1800. if (ret == 0) {
  1801. ret = -EIO;
  1802. dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
  1803. sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
  1804. sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
  1805. goto boot_err;
  1806. }
  1807. /* init module state after boot */
  1808. sst_hsw_init_module_state(hsw);
  1809. /* get the FW version */
  1810. sst_hsw_fw_get_version(hsw, &version);
  1811. /* get the globalmixer */
  1812. ret = sst_hsw_mixer_get_info(hsw);
  1813. if (ret < 0) {
  1814. dev_err(hsw->dev, "error: failed to get stream info\n");
  1815. goto boot_err;
  1816. }
  1817. pdata->dsp = hsw;
  1818. return 0;
  1819. boot_err:
  1820. sst_dsp_reset(hsw->dsp);
  1821. sst_fw_free_all(hsw->dsp);
  1822. fw_err:
  1823. dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
  1824. hsw->dx_context, hsw->dx_context_paddr);
  1825. dma_err:
  1826. sst_dsp_free(hsw->dsp);
  1827. dsp_new_err:
  1828. sst_ipc_fini(ipc);
  1829. ipc_init_err:
  1830. return ret;
  1831. }
  1832. EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
  1833. void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
  1834. {
  1835. struct sst_hsw *hsw = pdata->dsp;
  1836. sst_dsp_reset(hsw->dsp);
  1837. sst_fw_free_all(hsw->dsp);
  1838. dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
  1839. hsw->dx_context, hsw->dx_context_paddr);
  1840. sst_dsp_free(hsw->dsp);
  1841. sst_ipc_fini(&hsw->ipc);
  1842. }
  1843. EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);