skl-sst-cldma.c 11 KB

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  1. /*
  2. * skl-sst-cldma.c - Code Loader DMA handler
  3. *
  4. * Copyright (C) 2015, Intel Corporation.
  5. * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
  6. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as version 2, as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. */
  17. #include <linux/device.h>
  18. #include <linux/mm.h>
  19. #include <linux/delay.h>
  20. #include "../common/sst-dsp.h"
  21. #include "../common/sst-dsp-priv.h"
  22. static void skl_cldma_int_enable(struct sst_dsp *ctx)
  23. {
  24. sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
  25. SKL_ADSPIC_CL_DMA, SKL_ADSPIC_CL_DMA);
  26. }
  27. void skl_cldma_int_disable(struct sst_dsp *ctx)
  28. {
  29. sst_dsp_shim_update_bits_unlocked(ctx,
  30. SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0);
  31. }
  32. static void skl_cldma_stream_run(struct sst_dsp *ctx, bool enable)
  33. {
  34. unsigned char val;
  35. int timeout;
  36. sst_dsp_shim_update_bits_unlocked(ctx,
  37. SKL_ADSP_REG_CL_SD_CTL,
  38. CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(enable));
  39. udelay(3);
  40. timeout = 300;
  41. do {
  42. /* waiting for hardware to report that the stream Run bit set */
  43. val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) &
  44. CL_SD_CTL_RUN_MASK;
  45. if (enable && val)
  46. break;
  47. else if (!enable && !val)
  48. break;
  49. udelay(3);
  50. } while (--timeout);
  51. if (timeout == 0)
  52. dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
  53. }
  54. static void skl_cldma_stream_clear(struct sst_dsp *ctx)
  55. {
  56. /* make sure Run bit is cleared before setting stream register */
  57. skl_cldma_stream_run(ctx, 0);
  58. sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
  59. CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
  60. sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
  61. CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
  62. sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
  63. CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
  64. sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
  65. CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
  66. sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
  67. sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
  68. sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
  69. sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
  70. }
  71. /* Code loader helper APIs */
  72. static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
  73. struct snd_dma_buffer *dmab_data,
  74. __le32 **bdlp, int size, int with_ioc)
  75. {
  76. __le32 *bdl = *bdlp;
  77. ctx->cl_dev.frags = 0;
  78. while (size > 0) {
  79. phys_addr_t addr = virt_to_phys(dmab_data->area +
  80. (ctx->cl_dev.frags * ctx->cl_dev.bufsize));
  81. bdl[0] = cpu_to_le32(lower_32_bits(addr));
  82. bdl[1] = cpu_to_le32(upper_32_bits(addr));
  83. bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize);
  84. size -= ctx->cl_dev.bufsize;
  85. bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
  86. bdl += 4;
  87. ctx->cl_dev.frags++;
  88. }
  89. }
  90. /*
  91. * Setup controller
  92. * Configure the registers to update the dma buffer address and
  93. * enable interrupts.
  94. * Note: Using the channel 1 for transfer
  95. */
  96. static void skl_cldma_setup_controller(struct sst_dsp *ctx,
  97. struct snd_dma_buffer *dmab_bdl, unsigned int max_size,
  98. u32 count)
  99. {
  100. skl_cldma_stream_clear(ctx);
  101. sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
  102. CL_SD_BDLPLBA(dmab_bdl->addr));
  103. sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
  104. CL_SD_BDLPUBA(dmab_bdl->addr));
  105. sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);
  106. sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);
  107. sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
  108. CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(1));
  109. sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
  110. CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(1));
  111. sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
  112. CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(1));
  113. sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
  114. CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(FW_CL_STREAM_NUMBER));
  115. }
  116. static void skl_cldma_setup_spb(struct sst_dsp *ctx,
  117. unsigned int size, bool enable)
  118. {
  119. if (enable)
  120. sst_dsp_shim_update_bits_unlocked(ctx,
  121. SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
  122. CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
  123. CL_SPBFIFO_SPBFCCTL_SPIBE(1));
  124. sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);
  125. }
  126. static void skl_cldma_cleanup_spb(struct sst_dsp *ctx)
  127. {
  128. sst_dsp_shim_update_bits_unlocked(ctx,
  129. SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
  130. CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
  131. CL_SPBFIFO_SPBFCCTL_SPIBE(0));
  132. sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
  133. }
  134. static void skl_cldma_cleanup(struct sst_dsp *ctx)
  135. {
  136. skl_cldma_cleanup_spb(ctx);
  137. skl_cldma_stream_clear(ctx);
  138. ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
  139. ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
  140. }
  141. int skl_cldma_wait_interruptible(struct sst_dsp *ctx)
  142. {
  143. int ret = 0;
  144. if (!wait_event_timeout(ctx->cl_dev.wait_queue,
  145. ctx->cl_dev.wait_condition,
  146. msecs_to_jiffies(SKL_WAIT_TIMEOUT))) {
  147. dev_err(ctx->dev, "%s: Wait timeout\n", __func__);
  148. ret = -EIO;
  149. goto cleanup;
  150. }
  151. dev_dbg(ctx->dev, "%s: Event wake\n", __func__);
  152. if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
  153. dev_err(ctx->dev, "%s: DMA Error\n", __func__);
  154. ret = -EIO;
  155. }
  156. cleanup:
  157. ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
  158. return ret;
  159. }
  160. static void skl_cldma_stop(struct sst_dsp *ctx)
  161. {
  162. skl_cldma_stream_run(ctx, false);
  163. }
  164. static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
  165. const void *curr_pos, bool intr_enable, bool trigger)
  166. {
  167. dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);
  168. dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",
  169. ctx->cl_dev.dma_buffer_offset, trigger);
  170. dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);
  171. /*
  172. * Check if the size exceeds buffer boundary. If it exceeds
  173. * max_buffer size, then copy till buffer size and then copy
  174. * remaining buffer from the start of ring buffer.
  175. */
  176. if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) {
  177. unsigned int size_b = ctx->cl_dev.bufsize -
  178. ctx->cl_dev.dma_buffer_offset;
  179. memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
  180. curr_pos, size_b);
  181. size -= size_b;
  182. curr_pos += size_b;
  183. ctx->cl_dev.dma_buffer_offset = 0;
  184. }
  185. memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
  186. curr_pos, size);
  187. if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
  188. ctx->cl_dev.dma_buffer_offset = 0;
  189. else
  190. ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;
  191. ctx->cl_dev.wait_condition = false;
  192. if (intr_enable)
  193. skl_cldma_int_enable(ctx);
  194. ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
  195. if (trigger)
  196. ctx->cl_dev.ops.cl_trigger(ctx, true);
  197. }
  198. /*
  199. * The CL dma doesn't have any way to update the transfer status until a BDL
  200. * buffer is fully transferred
  201. *
  202. * So Copying is divided in two parts.
  203. * 1. Interrupt on buffer done where the size to be transferred is more than
  204. * ring buffer size.
  205. * 2. Polling on fw register to identify if data left to transferred doesn't
  206. * fill the ring buffer. Caller takes care of polling the required status
  207. * register to identify the transfer status.
  208. * 3. if wait flag is set, waits for DBL interrupt to copy the next chunk till
  209. * bytes_left is 0.
  210. * if wait flag is not set, doesn't wait for BDL interrupt. after ccopying
  211. * the first chunk return the no of bytes_left to be copied.
  212. */
  213. static int
  214. skl_cldma_copy_to_buf(struct sst_dsp *ctx, const void *bin,
  215. u32 total_size, bool wait)
  216. {
  217. int ret = 0;
  218. bool start = true;
  219. unsigned int excess_bytes;
  220. u32 size;
  221. unsigned int bytes_left = total_size;
  222. const void *curr_pos = bin;
  223. if (total_size <= 0)
  224. return -EINVAL;
  225. dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left);
  226. while (bytes_left) {
  227. if (bytes_left > ctx->cl_dev.bufsize) {
  228. /*
  229. * dma transfers only till the write pointer as
  230. * updated in spib
  231. */
  232. if (ctx->cl_dev.curr_spib_pos == 0)
  233. ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;
  234. size = ctx->cl_dev.bufsize;
  235. skl_cldma_fill_buffer(ctx, size, curr_pos, true, start);
  236. if (wait) {
  237. start = false;
  238. ret = skl_cldma_wait_interruptible(ctx);
  239. if (ret < 0) {
  240. skl_cldma_stop(ctx);
  241. return ret;
  242. }
  243. }
  244. } else {
  245. skl_cldma_int_disable(ctx);
  246. if ((ctx->cl_dev.curr_spib_pos + bytes_left)
  247. <= ctx->cl_dev.bufsize) {
  248. ctx->cl_dev.curr_spib_pos += bytes_left;
  249. } else {
  250. excess_bytes = bytes_left -
  251. (ctx->cl_dev.bufsize -
  252. ctx->cl_dev.curr_spib_pos);
  253. ctx->cl_dev.curr_spib_pos = excess_bytes;
  254. }
  255. size = bytes_left;
  256. skl_cldma_fill_buffer(ctx, size,
  257. curr_pos, false, start);
  258. }
  259. bytes_left -= size;
  260. curr_pos = curr_pos + size;
  261. if (!wait)
  262. return bytes_left;
  263. }
  264. return bytes_left;
  265. }
  266. void skl_cldma_process_intr(struct sst_dsp *ctx)
  267. {
  268. u8 cl_dma_intr_status;
  269. cl_dma_intr_status =
  270. sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS);
  271. if (!(cl_dma_intr_status & SKL_CL_DMA_SD_INT_COMPLETE))
  272. ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;
  273. else
  274. ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;
  275. ctx->cl_dev.wait_condition = true;
  276. wake_up(&ctx->cl_dev.wait_queue);
  277. }
  278. int skl_cldma_prepare(struct sst_dsp *ctx)
  279. {
  280. int ret;
  281. __le32 *bdl;
  282. ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;
  283. /* Allocate cl ops */
  284. ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;
  285. ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
  286. ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
  287. ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
  288. ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run;
  289. ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
  290. ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
  291. ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
  292. /* Allocate buffer*/
  293. ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
  294. &ctx->cl_dev.dmab_data, ctx->cl_dev.bufsize);
  295. if (ret < 0) {
  296. dev_err(ctx->dev, "Alloc buffer for base fw failed: %x\n", ret);
  297. return ret;
  298. }
  299. /* Setup Code loader BDL */
  300. ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
  301. &ctx->cl_dev.dmab_bdl, PAGE_SIZE);
  302. if (ret < 0) {
  303. dev_err(ctx->dev, "Alloc buffer for blde failed: %x\n", ret);
  304. ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
  305. return ret;
  306. }
  307. bdl = (__le32 *)ctx->cl_dev.dmab_bdl.area;
  308. /* Allocate BDLs */
  309. ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,
  310. &bdl, ctx->cl_dev.bufsize, 1);
  311. ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,
  312. ctx->cl_dev.bufsize, ctx->cl_dev.frags);
  313. ctx->cl_dev.curr_spib_pos = 0;
  314. ctx->cl_dev.dma_buffer_offset = 0;
  315. init_waitqueue_head(&ctx->cl_dev.wait_queue);
  316. return ret;
  317. }