siu_pcm.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602
  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // siu_pcm.c - ALSA driver for Renesas SH7343, SH7722 SIU peripheral.
  4. //
  5. // Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  6. // Copyright (C) 2006 Carlos Munoz <carlos@kenati.com>
  7. #include <linux/delay.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/dmaengine.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/module.h>
  12. #include <linux/platform_device.h>
  13. #include <sound/control.h>
  14. #include <sound/core.h>
  15. #include <sound/pcm.h>
  16. #include <sound/pcm_params.h>
  17. #include <sound/soc.h>
  18. #include <asm/siu.h>
  19. #include "siu.h"
  20. #define DRV_NAME "siu-i2s"
  21. #define GET_MAX_PERIODS(buf_bytes, period_bytes) \
  22. ((buf_bytes) / (period_bytes))
  23. #define PERIOD_OFFSET(buf_addr, period_num, period_bytes) \
  24. ((buf_addr) + ((period_num) * (period_bytes)))
  25. #define RWF_STM_RD 0x01 /* Read in progress */
  26. #define RWF_STM_WT 0x02 /* Write in progress */
  27. struct siu_port *siu_ports[SIU_PORT_NUM];
  28. /* transfersize is number of u32 dma transfers per period */
  29. static int siu_pcm_stmwrite_stop(struct siu_port *port_info)
  30. {
  31. struct siu_info *info = siu_i2s_data;
  32. u32 __iomem *base = info->reg;
  33. struct siu_stream *siu_stream = &port_info->playback;
  34. u32 stfifo;
  35. if (!siu_stream->rw_flg)
  36. return -EPERM;
  37. /* output FIFO disable */
  38. stfifo = siu_read32(base + SIU_STFIFO);
  39. siu_write32(base + SIU_STFIFO, stfifo & ~0x0c180c18);
  40. pr_debug("%s: STFIFO %x -> %x\n", __func__,
  41. stfifo, stfifo & ~0x0c180c18);
  42. /* during stmwrite clear */
  43. siu_stream->rw_flg = 0;
  44. return 0;
  45. }
  46. static int siu_pcm_stmwrite_start(struct siu_port *port_info)
  47. {
  48. struct siu_stream *siu_stream = &port_info->playback;
  49. if (siu_stream->rw_flg)
  50. return -EPERM;
  51. /* Current period in buffer */
  52. port_info->playback.cur_period = 0;
  53. /* during stmwrite flag set */
  54. siu_stream->rw_flg = RWF_STM_WT;
  55. /* DMA transfer start */
  56. tasklet_schedule(&siu_stream->tasklet);
  57. return 0;
  58. }
  59. static void siu_dma_tx_complete(void *arg)
  60. {
  61. struct siu_stream *siu_stream = arg;
  62. if (!siu_stream->rw_flg)
  63. return;
  64. /* Update completed period count */
  65. if (++siu_stream->cur_period >=
  66. GET_MAX_PERIODS(siu_stream->buf_bytes,
  67. siu_stream->period_bytes))
  68. siu_stream->cur_period = 0;
  69. pr_debug("%s: done period #%d (%u/%u bytes), cookie %d\n",
  70. __func__, siu_stream->cur_period,
  71. siu_stream->cur_period * siu_stream->period_bytes,
  72. siu_stream->buf_bytes, siu_stream->cookie);
  73. tasklet_schedule(&siu_stream->tasklet);
  74. /* Notify alsa: a period is done */
  75. snd_pcm_period_elapsed(siu_stream->substream);
  76. }
  77. static int siu_pcm_wr_set(struct siu_port *port_info,
  78. dma_addr_t buff, u32 size)
  79. {
  80. struct siu_info *info = siu_i2s_data;
  81. u32 __iomem *base = info->reg;
  82. struct siu_stream *siu_stream = &port_info->playback;
  83. struct snd_pcm_substream *substream = siu_stream->substream;
  84. struct device *dev = substream->pcm->card->dev;
  85. struct dma_async_tx_descriptor *desc;
  86. dma_cookie_t cookie;
  87. struct scatterlist sg;
  88. u32 stfifo;
  89. sg_init_table(&sg, 1);
  90. sg_set_page(&sg, pfn_to_page(PFN_DOWN(buff)),
  91. size, offset_in_page(buff));
  92. sg_dma_len(&sg) = size;
  93. sg_dma_address(&sg) = buff;
  94. desc = dmaengine_prep_slave_sg(siu_stream->chan,
  95. &sg, 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  96. if (!desc) {
  97. dev_err(dev, "Failed to allocate a dma descriptor\n");
  98. return -ENOMEM;
  99. }
  100. desc->callback = siu_dma_tx_complete;
  101. desc->callback_param = siu_stream;
  102. cookie = dmaengine_submit(desc);
  103. if (cookie < 0) {
  104. dev_err(dev, "Failed to submit a dma transfer\n");
  105. return cookie;
  106. }
  107. siu_stream->tx_desc = desc;
  108. siu_stream->cookie = cookie;
  109. dma_async_issue_pending(siu_stream->chan);
  110. /* only output FIFO enable */
  111. stfifo = siu_read32(base + SIU_STFIFO);
  112. siu_write32(base + SIU_STFIFO, stfifo | (port_info->stfifo & 0x0c180c18));
  113. dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
  114. stfifo, stfifo | (port_info->stfifo & 0x0c180c18));
  115. return 0;
  116. }
  117. static int siu_pcm_rd_set(struct siu_port *port_info,
  118. dma_addr_t buff, size_t size)
  119. {
  120. struct siu_info *info = siu_i2s_data;
  121. u32 __iomem *base = info->reg;
  122. struct siu_stream *siu_stream = &port_info->capture;
  123. struct snd_pcm_substream *substream = siu_stream->substream;
  124. struct device *dev = substream->pcm->card->dev;
  125. struct dma_async_tx_descriptor *desc;
  126. dma_cookie_t cookie;
  127. struct scatterlist sg;
  128. u32 stfifo;
  129. dev_dbg(dev, "%s: %u@%llx\n", __func__, size, (unsigned long long)buff);
  130. sg_init_table(&sg, 1);
  131. sg_set_page(&sg, pfn_to_page(PFN_DOWN(buff)),
  132. size, offset_in_page(buff));
  133. sg_dma_len(&sg) = size;
  134. sg_dma_address(&sg) = buff;
  135. desc = dmaengine_prep_slave_sg(siu_stream->chan,
  136. &sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  137. if (!desc) {
  138. dev_err(dev, "Failed to allocate dma descriptor\n");
  139. return -ENOMEM;
  140. }
  141. desc->callback = siu_dma_tx_complete;
  142. desc->callback_param = siu_stream;
  143. cookie = dmaengine_submit(desc);
  144. if (cookie < 0) {
  145. dev_err(dev, "Failed to submit dma descriptor\n");
  146. return cookie;
  147. }
  148. siu_stream->tx_desc = desc;
  149. siu_stream->cookie = cookie;
  150. dma_async_issue_pending(siu_stream->chan);
  151. /* only input FIFO enable */
  152. stfifo = siu_read32(base + SIU_STFIFO);
  153. siu_write32(base + SIU_STFIFO, siu_read32(base + SIU_STFIFO) |
  154. (port_info->stfifo & 0x13071307));
  155. dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
  156. stfifo, stfifo | (port_info->stfifo & 0x13071307));
  157. return 0;
  158. }
  159. static void siu_io_tasklet(unsigned long data)
  160. {
  161. struct siu_stream *siu_stream = (struct siu_stream *)data;
  162. struct snd_pcm_substream *substream = siu_stream->substream;
  163. struct device *dev = substream->pcm->card->dev;
  164. struct snd_pcm_runtime *rt = substream->runtime;
  165. struct siu_port *port_info = siu_port_info(substream);
  166. dev_dbg(dev, "%s: flags %x\n", __func__, siu_stream->rw_flg);
  167. if (!siu_stream->rw_flg) {
  168. dev_dbg(dev, "%s: stream inactive\n", __func__);
  169. return;
  170. }
  171. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  172. dma_addr_t buff;
  173. size_t count;
  174. u8 *virt;
  175. buff = (dma_addr_t)PERIOD_OFFSET(rt->dma_addr,
  176. siu_stream->cur_period,
  177. siu_stream->period_bytes);
  178. virt = PERIOD_OFFSET(rt->dma_area,
  179. siu_stream->cur_period,
  180. siu_stream->period_bytes);
  181. count = siu_stream->period_bytes;
  182. /* DMA transfer start */
  183. siu_pcm_rd_set(port_info, buff, count);
  184. } else {
  185. siu_pcm_wr_set(port_info,
  186. (dma_addr_t)PERIOD_OFFSET(rt->dma_addr,
  187. siu_stream->cur_period,
  188. siu_stream->period_bytes),
  189. siu_stream->period_bytes);
  190. }
  191. }
  192. /* Capture */
  193. static int siu_pcm_stmread_start(struct siu_port *port_info)
  194. {
  195. struct siu_stream *siu_stream = &port_info->capture;
  196. if (siu_stream->xfer_cnt > 0x1000000)
  197. return -EINVAL;
  198. if (siu_stream->rw_flg)
  199. return -EPERM;
  200. /* Current period in buffer */
  201. siu_stream->cur_period = 0;
  202. /* during stmread flag set */
  203. siu_stream->rw_flg = RWF_STM_RD;
  204. tasklet_schedule(&siu_stream->tasklet);
  205. return 0;
  206. }
  207. static int siu_pcm_stmread_stop(struct siu_port *port_info)
  208. {
  209. struct siu_info *info = siu_i2s_data;
  210. u32 __iomem *base = info->reg;
  211. struct siu_stream *siu_stream = &port_info->capture;
  212. struct device *dev = siu_stream->substream->pcm->card->dev;
  213. u32 stfifo;
  214. if (!siu_stream->rw_flg)
  215. return -EPERM;
  216. /* input FIFO disable */
  217. stfifo = siu_read32(base + SIU_STFIFO);
  218. siu_write32(base + SIU_STFIFO, stfifo & ~0x13071307);
  219. dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
  220. stfifo, stfifo & ~0x13071307);
  221. /* during stmread flag clear */
  222. siu_stream->rw_flg = 0;
  223. return 0;
  224. }
  225. static int siu_pcm_hw_params(struct snd_pcm_substream *ss,
  226. struct snd_pcm_hw_params *hw_params)
  227. {
  228. struct siu_info *info = siu_i2s_data;
  229. struct device *dev = ss->pcm->card->dev;
  230. int ret;
  231. dev_dbg(dev, "%s: port=%d\n", __func__, info->port_id);
  232. ret = snd_pcm_lib_malloc_pages(ss, params_buffer_bytes(hw_params));
  233. if (ret < 0)
  234. dev_err(dev, "snd_pcm_lib_malloc_pages() failed\n");
  235. return ret;
  236. }
  237. static int siu_pcm_hw_free(struct snd_pcm_substream *ss)
  238. {
  239. struct siu_info *info = siu_i2s_data;
  240. struct siu_port *port_info = siu_port_info(ss);
  241. struct device *dev = ss->pcm->card->dev;
  242. struct siu_stream *siu_stream;
  243. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
  244. siu_stream = &port_info->playback;
  245. else
  246. siu_stream = &port_info->capture;
  247. dev_dbg(dev, "%s: port=%d\n", __func__, info->port_id);
  248. return snd_pcm_lib_free_pages(ss);
  249. }
  250. static bool filter(struct dma_chan *chan, void *slave)
  251. {
  252. struct sh_dmae_slave *param = slave;
  253. pr_debug("%s: slave ID %d\n", __func__, param->shdma_slave.slave_id);
  254. chan->private = &param->shdma_slave;
  255. return true;
  256. }
  257. static int siu_pcm_open(struct snd_pcm_substream *ss)
  258. {
  259. /* Playback / Capture */
  260. struct snd_soc_pcm_runtime *rtd = ss->private_data;
  261. struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
  262. struct siu_platform *pdata = component->dev->platform_data;
  263. struct siu_info *info = siu_i2s_data;
  264. struct siu_port *port_info = siu_port_info(ss);
  265. struct siu_stream *siu_stream;
  266. u32 port = info->port_id;
  267. struct device *dev = ss->pcm->card->dev;
  268. dma_cap_mask_t mask;
  269. struct sh_dmae_slave *param;
  270. dma_cap_zero(mask);
  271. dma_cap_set(DMA_SLAVE, mask);
  272. dev_dbg(dev, "%s, port=%d@%p\n", __func__, port, port_info);
  273. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  274. siu_stream = &port_info->playback;
  275. param = &siu_stream->param;
  276. param->shdma_slave.slave_id = port ? pdata->dma_slave_tx_b :
  277. pdata->dma_slave_tx_a;
  278. } else {
  279. siu_stream = &port_info->capture;
  280. param = &siu_stream->param;
  281. param->shdma_slave.slave_id = port ? pdata->dma_slave_rx_b :
  282. pdata->dma_slave_rx_a;
  283. }
  284. /* Get DMA channel */
  285. siu_stream->chan = dma_request_channel(mask, filter, param);
  286. if (!siu_stream->chan) {
  287. dev_err(dev, "DMA channel allocation failed!\n");
  288. return -EBUSY;
  289. }
  290. siu_stream->substream = ss;
  291. return 0;
  292. }
  293. static int siu_pcm_close(struct snd_pcm_substream *ss)
  294. {
  295. struct siu_info *info = siu_i2s_data;
  296. struct device *dev = ss->pcm->card->dev;
  297. struct siu_port *port_info = siu_port_info(ss);
  298. struct siu_stream *siu_stream;
  299. dev_dbg(dev, "%s: port=%d\n", __func__, info->port_id);
  300. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
  301. siu_stream = &port_info->playback;
  302. else
  303. siu_stream = &port_info->capture;
  304. dma_release_channel(siu_stream->chan);
  305. siu_stream->chan = NULL;
  306. siu_stream->substream = NULL;
  307. return 0;
  308. }
  309. static int siu_pcm_prepare(struct snd_pcm_substream *ss)
  310. {
  311. struct siu_info *info = siu_i2s_data;
  312. struct siu_port *port_info = siu_port_info(ss);
  313. struct device *dev = ss->pcm->card->dev;
  314. struct snd_pcm_runtime *rt = ss->runtime;
  315. struct siu_stream *siu_stream;
  316. snd_pcm_sframes_t xfer_cnt;
  317. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
  318. siu_stream = &port_info->playback;
  319. else
  320. siu_stream = &port_info->capture;
  321. rt = siu_stream->substream->runtime;
  322. siu_stream->buf_bytes = snd_pcm_lib_buffer_bytes(ss);
  323. siu_stream->period_bytes = snd_pcm_lib_period_bytes(ss);
  324. dev_dbg(dev, "%s: port=%d, %d channels, period=%u bytes\n", __func__,
  325. info->port_id, rt->channels, siu_stream->period_bytes);
  326. /* We only support buffers that are multiples of the period */
  327. if (siu_stream->buf_bytes % siu_stream->period_bytes) {
  328. dev_err(dev, "%s() - buffer=%d not multiple of period=%d\n",
  329. __func__, siu_stream->buf_bytes,
  330. siu_stream->period_bytes);
  331. return -EINVAL;
  332. }
  333. xfer_cnt = bytes_to_frames(rt, siu_stream->period_bytes);
  334. if (!xfer_cnt || xfer_cnt > 0x1000000)
  335. return -EINVAL;
  336. siu_stream->format = rt->format;
  337. siu_stream->xfer_cnt = xfer_cnt;
  338. dev_dbg(dev, "port=%d buf=%lx buf_bytes=%d period_bytes=%d "
  339. "format=%d channels=%d xfer_cnt=%d\n", info->port_id,
  340. (unsigned long)rt->dma_addr, siu_stream->buf_bytes,
  341. siu_stream->period_bytes,
  342. siu_stream->format, rt->channels, (int)xfer_cnt);
  343. return 0;
  344. }
  345. static int siu_pcm_trigger(struct snd_pcm_substream *ss, int cmd)
  346. {
  347. struct siu_info *info = siu_i2s_data;
  348. struct device *dev = ss->pcm->card->dev;
  349. struct siu_port *port_info = siu_port_info(ss);
  350. int ret;
  351. dev_dbg(dev, "%s: port=%d@%p, cmd=%d\n", __func__,
  352. info->port_id, port_info, cmd);
  353. switch (cmd) {
  354. case SNDRV_PCM_TRIGGER_START:
  355. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
  356. ret = siu_pcm_stmwrite_start(port_info);
  357. else
  358. ret = siu_pcm_stmread_start(port_info);
  359. if (ret < 0)
  360. dev_warn(dev, "%s: start failed on port=%d\n",
  361. __func__, info->port_id);
  362. break;
  363. case SNDRV_PCM_TRIGGER_STOP:
  364. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
  365. siu_pcm_stmwrite_stop(port_info);
  366. else
  367. siu_pcm_stmread_stop(port_info);
  368. ret = 0;
  369. break;
  370. default:
  371. dev_err(dev, "%s() unsupported cmd=%d\n", __func__, cmd);
  372. ret = -EINVAL;
  373. }
  374. return ret;
  375. }
  376. /*
  377. * So far only resolution of one period is supported, subject to extending the
  378. * dmangine API
  379. */
  380. static snd_pcm_uframes_t siu_pcm_pointer_dma(struct snd_pcm_substream *ss)
  381. {
  382. struct device *dev = ss->pcm->card->dev;
  383. struct siu_info *info = siu_i2s_data;
  384. u32 __iomem *base = info->reg;
  385. struct siu_port *port_info = siu_port_info(ss);
  386. struct snd_pcm_runtime *rt = ss->runtime;
  387. size_t ptr;
  388. struct siu_stream *siu_stream;
  389. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
  390. siu_stream = &port_info->playback;
  391. else
  392. siu_stream = &port_info->capture;
  393. /*
  394. * ptr is the offset into the buffer where the dma is currently at. We
  395. * check if the dma buffer has just wrapped.
  396. */
  397. ptr = PERIOD_OFFSET(rt->dma_addr,
  398. siu_stream->cur_period,
  399. siu_stream->period_bytes) - rt->dma_addr;
  400. dev_dbg(dev,
  401. "%s: port=%d, events %x, FSTS %x, xferred %u/%u, cookie %d\n",
  402. __func__, info->port_id, siu_read32(base + SIU_EVNTC),
  403. siu_read32(base + SIU_SBFSTS), ptr, siu_stream->buf_bytes,
  404. siu_stream->cookie);
  405. if (ptr >= siu_stream->buf_bytes)
  406. ptr = 0;
  407. return bytes_to_frames(ss->runtime, ptr);
  408. }
  409. static int siu_pcm_new(struct snd_soc_pcm_runtime *rtd)
  410. {
  411. /* card->dev == socdev->dev, see snd_soc_new_pcms() */
  412. struct snd_card *card = rtd->card->snd_card;
  413. struct snd_pcm *pcm = rtd->pcm;
  414. struct siu_info *info = siu_i2s_data;
  415. struct platform_device *pdev = to_platform_device(card->dev);
  416. int ret;
  417. int i;
  418. /* pdev->id selects between SIUA and SIUB */
  419. if (pdev->id < 0 || pdev->id >= SIU_PORT_NUM)
  420. return -EINVAL;
  421. info->port_id = pdev->id;
  422. /*
  423. * While the siu has 2 ports, only one port can be on at a time (only 1
  424. * SPB). So far all the boards using the siu had only one of the ports
  425. * wired to a codec. To simplify things, we only register one port with
  426. * alsa. In case both ports are needed, it should be changed here
  427. */
  428. for (i = pdev->id; i < pdev->id + 1; i++) {
  429. struct siu_port **port_info = &siu_ports[i];
  430. ret = siu_init_port(i, port_info, card);
  431. if (ret < 0)
  432. return ret;
  433. ret = snd_pcm_lib_preallocate_pages_for_all(pcm,
  434. SNDRV_DMA_TYPE_DEV, NULL,
  435. SIU_BUFFER_BYTES_MAX, SIU_BUFFER_BYTES_MAX);
  436. if (ret < 0) {
  437. dev_err(card->dev,
  438. "snd_pcm_lib_preallocate_pages_for_all() err=%d",
  439. ret);
  440. goto fail;
  441. }
  442. (*port_info)->pcm = pcm;
  443. /* IO tasklets */
  444. tasklet_init(&(*port_info)->playback.tasklet, siu_io_tasklet,
  445. (unsigned long)&(*port_info)->playback);
  446. tasklet_init(&(*port_info)->capture.tasklet, siu_io_tasklet,
  447. (unsigned long)&(*port_info)->capture);
  448. }
  449. dev_info(card->dev, "SuperH SIU driver initialized.\n");
  450. return 0;
  451. fail:
  452. siu_free_port(siu_ports[pdev->id]);
  453. dev_err(card->dev, "SIU: failed to initialize.\n");
  454. return ret;
  455. }
  456. static void siu_pcm_free(struct snd_pcm *pcm)
  457. {
  458. struct platform_device *pdev = to_platform_device(pcm->card->dev);
  459. struct siu_port *port_info = siu_ports[pdev->id];
  460. tasklet_kill(&port_info->capture.tasklet);
  461. tasklet_kill(&port_info->playback.tasklet);
  462. siu_free_port(port_info);
  463. dev_dbg(pcm->card->dev, "%s\n", __func__);
  464. }
  465. static const struct snd_pcm_ops siu_pcm_ops = {
  466. .open = siu_pcm_open,
  467. .close = siu_pcm_close,
  468. .ioctl = snd_pcm_lib_ioctl,
  469. .hw_params = siu_pcm_hw_params,
  470. .hw_free = siu_pcm_hw_free,
  471. .prepare = siu_pcm_prepare,
  472. .trigger = siu_pcm_trigger,
  473. .pointer = siu_pcm_pointer_dma,
  474. };
  475. struct snd_soc_component_driver siu_component = {
  476. .name = DRV_NAME,
  477. .ops = &siu_pcm_ops,
  478. .pcm_new = siu_pcm_new,
  479. .pcm_free = siu_pcm_free,
  480. };
  481. EXPORT_SYMBOL_GPL(siu_component);