swim3.c 32 KB

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  1. /*
  2. * Driver for the SWIM3 (Super Woz Integrated Machine 3)
  3. * floppy controller found on Power Macintoshes.
  4. *
  5. * Copyright (C) 1996 Paul Mackerras.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. /*
  13. * TODO:
  14. * handle 2 drives
  15. * handle GCR disks
  16. */
  17. #undef DEBUG
  18. #include <linux/stddef.h>
  19. #include <linux/kernel.h>
  20. #include <linux/sched/signal.h>
  21. #include <linux/timer.h>
  22. #include <linux/delay.h>
  23. #include <linux/fd.h>
  24. #include <linux/ioctl.h>
  25. #include <linux/blkdev.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/mutex.h>
  28. #include <linux/module.h>
  29. #include <linux/spinlock.h>
  30. #include <linux/wait.h>
  31. #include <asm/io.h>
  32. #include <asm/dbdma.h>
  33. #include <asm/prom.h>
  34. #include <linux/uaccess.h>
  35. #include <asm/mediabay.h>
  36. #include <asm/machdep.h>
  37. #include <asm/pmac_feature.h>
  38. #define MAX_FLOPPIES 2
  39. static DEFINE_MUTEX(swim3_mutex);
  40. static struct gendisk *disks[MAX_FLOPPIES];
  41. enum swim_state {
  42. idle,
  43. locating,
  44. seeking,
  45. settling,
  46. do_transfer,
  47. jogging,
  48. available,
  49. revalidating,
  50. ejecting
  51. };
  52. #define REG(x) unsigned char x; char x ## _pad[15];
  53. /*
  54. * The names for these registers mostly represent speculation on my part.
  55. * It will be interesting to see how close they are to the names Apple uses.
  56. */
  57. struct swim3 {
  58. REG(data);
  59. REG(timer); /* counts down at 1MHz */
  60. REG(error);
  61. REG(mode);
  62. REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */
  63. REG(setup);
  64. REG(control); /* writing bits clears them */
  65. REG(status); /* writing bits sets them in control */
  66. REG(intr);
  67. REG(nseek); /* # tracks to seek */
  68. REG(ctrack); /* current track number */
  69. REG(csect); /* current sector number */
  70. REG(gap3); /* size of gap 3 in track format */
  71. REG(sector); /* sector # to read or write */
  72. REG(nsect); /* # sectors to read or write */
  73. REG(intr_enable);
  74. };
  75. #define control_bic control
  76. #define control_bis status
  77. /* Bits in select register */
  78. #define CA_MASK 7
  79. #define LSTRB 8
  80. /* Bits in control register */
  81. #define DO_SEEK 0x80
  82. #define FORMAT 0x40
  83. #define SELECT 0x20
  84. #define WRITE_SECTORS 0x10
  85. #define DO_ACTION 0x08
  86. #define DRIVE2_ENABLE 0x04
  87. #define DRIVE_ENABLE 0x02
  88. #define INTR_ENABLE 0x01
  89. /* Bits in status register */
  90. #define FIFO_1BYTE 0x80
  91. #define FIFO_2BYTE 0x40
  92. #define ERROR 0x20
  93. #define DATA 0x08
  94. #define RDDATA 0x04
  95. #define INTR_PENDING 0x02
  96. #define MARK_BYTE 0x01
  97. /* Bits in intr and intr_enable registers */
  98. #define ERROR_INTR 0x20
  99. #define DATA_CHANGED 0x10
  100. #define TRANSFER_DONE 0x08
  101. #define SEEN_SECTOR 0x04
  102. #define SEEK_DONE 0x02
  103. #define TIMER_DONE 0x01
  104. /* Bits in error register */
  105. #define ERR_DATA_CRC 0x80
  106. #define ERR_ADDR_CRC 0x40
  107. #define ERR_OVERRUN 0x04
  108. #define ERR_UNDERRUN 0x01
  109. /* Bits in setup register */
  110. #define S_SW_RESET 0x80
  111. #define S_GCR_WRITE 0x40
  112. #define S_IBM_DRIVE 0x20
  113. #define S_TEST_MODE 0x10
  114. #define S_FCLK_DIV2 0x08
  115. #define S_GCR 0x04
  116. #define S_COPY_PROT 0x02
  117. #define S_INV_WDATA 0x01
  118. /* Select values for swim3_action */
  119. #define SEEK_POSITIVE 0
  120. #define SEEK_NEGATIVE 4
  121. #define STEP 1
  122. #define MOTOR_ON 2
  123. #define MOTOR_OFF 6
  124. #define INDEX 3
  125. #define EJECT 7
  126. #define SETMFM 9
  127. #define SETGCR 13
  128. /* Select values for swim3_select and swim3_readbit */
  129. #define STEP_DIR 0
  130. #define STEPPING 1
  131. #define MOTOR_ON 2
  132. #define RELAX 3 /* also eject in progress */
  133. #define READ_DATA_0 4
  134. #define ONEMEG_DRIVE 5
  135. #define SINGLE_SIDED 6 /* drive or diskette is 4MB type? */
  136. #define DRIVE_PRESENT 7
  137. #define DISK_IN 8
  138. #define WRITE_PROT 9
  139. #define TRACK_ZERO 10
  140. #define TACHO 11
  141. #define READ_DATA_1 12
  142. #define GCR_MODE 13
  143. #define SEEK_COMPLETE 14
  144. #define TWOMEG_MEDIA 15
  145. /* Definitions of values used in writing and formatting */
  146. #define DATA_ESCAPE 0x99
  147. #define GCR_SYNC_EXC 0x3f
  148. #define GCR_SYNC_CONV 0x80
  149. #define GCR_FIRST_MARK 0xd5
  150. #define GCR_SECOND_MARK 0xaa
  151. #define GCR_ADDR_MARK "\xd5\xaa\x00"
  152. #define GCR_DATA_MARK "\xd5\xaa\x0b"
  153. #define GCR_SLIP_BYTE "\x27\xaa"
  154. #define GCR_SELF_SYNC "\x3f\xbf\x1e\x34\x3c\x3f"
  155. #define DATA_99 "\x99\x99"
  156. #define MFM_ADDR_MARK "\x99\xa1\x99\xa1\x99\xa1\x99\xfe"
  157. #define MFM_INDEX_MARK "\x99\xc2\x99\xc2\x99\xc2\x99\xfc"
  158. #define MFM_GAP_LEN 12
  159. struct floppy_state {
  160. enum swim_state state;
  161. struct swim3 __iomem *swim3; /* hardware registers */
  162. struct dbdma_regs __iomem *dma; /* DMA controller registers */
  163. int swim3_intr; /* interrupt number for SWIM3 */
  164. int dma_intr; /* interrupt number for DMA channel */
  165. int cur_cyl; /* cylinder head is on, or -1 */
  166. int cur_sector; /* last sector we saw go past */
  167. int req_cyl; /* the cylinder for the current r/w request */
  168. int head; /* head number ditto */
  169. int req_sector; /* sector number ditto */
  170. int scount; /* # sectors we're transferring at present */
  171. int retries;
  172. int settle_time;
  173. int secpercyl; /* disk geometry information */
  174. int secpertrack;
  175. int total_secs;
  176. int write_prot; /* 1 if write-protected, 0 if not, -1 dunno */
  177. struct dbdma_cmd *dma_cmd;
  178. int ref_count;
  179. int expect_cyl;
  180. struct timer_list timeout;
  181. int timeout_pending;
  182. int ejected;
  183. wait_queue_head_t wait;
  184. int wanted;
  185. struct macio_dev *mdev;
  186. char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)];
  187. int index;
  188. struct request *cur_req;
  189. };
  190. #define swim3_err(fmt, arg...) dev_err(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
  191. #define swim3_warn(fmt, arg...) dev_warn(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
  192. #define swim3_info(fmt, arg...) dev_info(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
  193. #ifdef DEBUG
  194. #define swim3_dbg(fmt, arg...) dev_dbg(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
  195. #else
  196. #define swim3_dbg(fmt, arg...) do { } while(0)
  197. #endif
  198. static struct floppy_state floppy_states[MAX_FLOPPIES];
  199. static int floppy_count = 0;
  200. static DEFINE_SPINLOCK(swim3_lock);
  201. static unsigned short write_preamble[] = {
  202. 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, /* gap field */
  203. 0, 0, 0, 0, 0, 0, /* sync field */
  204. 0x99a1, 0x99a1, 0x99a1, 0x99fb, /* data address mark */
  205. 0x990f /* no escape for 512 bytes */
  206. };
  207. static unsigned short write_postamble[] = {
  208. 0x9904, /* insert CRC */
  209. 0x4e4e, 0x4e4e,
  210. 0x9908, /* stop writing */
  211. 0, 0, 0, 0, 0, 0
  212. };
  213. static void seek_track(struct floppy_state *fs, int n);
  214. static void init_dma(struct dbdma_cmd *cp, int cmd, void *buf, int count);
  215. static void act(struct floppy_state *fs);
  216. static void scan_timeout(struct timer_list *t);
  217. static void seek_timeout(struct timer_list *t);
  218. static void settle_timeout(struct timer_list *t);
  219. static void xfer_timeout(struct timer_list *t);
  220. static irqreturn_t swim3_interrupt(int irq, void *dev_id);
  221. /*static void fd_dma_interrupt(int irq, void *dev_id);*/
  222. static int grab_drive(struct floppy_state *fs, enum swim_state state,
  223. int interruptible);
  224. static void release_drive(struct floppy_state *fs);
  225. static int fd_eject(struct floppy_state *fs);
  226. static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
  227. unsigned int cmd, unsigned long param);
  228. static int floppy_open(struct block_device *bdev, fmode_t mode);
  229. static void floppy_release(struct gendisk *disk, fmode_t mode);
  230. static unsigned int floppy_check_events(struct gendisk *disk,
  231. unsigned int clearing);
  232. static int floppy_revalidate(struct gendisk *disk);
  233. static bool swim3_end_request(struct floppy_state *fs, blk_status_t err, unsigned int nr_bytes)
  234. {
  235. struct request *req = fs->cur_req;
  236. int rc;
  237. swim3_dbg(" end request, err=%d nr_bytes=%d, cur_req=%p\n",
  238. err, nr_bytes, req);
  239. if (err)
  240. nr_bytes = blk_rq_cur_bytes(req);
  241. rc = __blk_end_request(req, err, nr_bytes);
  242. if (rc)
  243. return true;
  244. fs->cur_req = NULL;
  245. return false;
  246. }
  247. static void swim3_select(struct floppy_state *fs, int sel)
  248. {
  249. struct swim3 __iomem *sw = fs->swim3;
  250. out_8(&sw->select, RELAX);
  251. if (sel & 8)
  252. out_8(&sw->control_bis, SELECT);
  253. else
  254. out_8(&sw->control_bic, SELECT);
  255. out_8(&sw->select, sel & CA_MASK);
  256. }
  257. static void swim3_action(struct floppy_state *fs, int action)
  258. {
  259. struct swim3 __iomem *sw = fs->swim3;
  260. swim3_select(fs, action);
  261. udelay(1);
  262. out_8(&sw->select, sw->select | LSTRB);
  263. udelay(2);
  264. out_8(&sw->select, sw->select & ~LSTRB);
  265. udelay(1);
  266. }
  267. static int swim3_readbit(struct floppy_state *fs, int bit)
  268. {
  269. struct swim3 __iomem *sw = fs->swim3;
  270. int stat;
  271. swim3_select(fs, bit);
  272. udelay(1);
  273. stat = in_8(&sw->status);
  274. return (stat & DATA) == 0;
  275. }
  276. static void start_request(struct floppy_state *fs)
  277. {
  278. struct request *req;
  279. unsigned long x;
  280. swim3_dbg("start request, initial state=%d\n", fs->state);
  281. if (fs->state == idle && fs->wanted) {
  282. fs->state = available;
  283. wake_up(&fs->wait);
  284. return;
  285. }
  286. while (fs->state == idle) {
  287. swim3_dbg("start request, idle loop, cur_req=%p\n", fs->cur_req);
  288. if (!fs->cur_req) {
  289. fs->cur_req = blk_fetch_request(disks[fs->index]->queue);
  290. swim3_dbg(" fetched request %p\n", fs->cur_req);
  291. if (!fs->cur_req)
  292. break;
  293. }
  294. req = fs->cur_req;
  295. if (fs->mdev->media_bay &&
  296. check_media_bay(fs->mdev->media_bay) != MB_FD) {
  297. swim3_dbg("%s", " media bay absent, dropping req\n");
  298. swim3_end_request(fs, BLK_STS_IOERR, 0);
  299. continue;
  300. }
  301. #if 0 /* This is really too verbose */
  302. swim3_dbg("do_fd_req: dev=%s cmd=%d sec=%ld nr_sec=%u buf=%p\n",
  303. req->rq_disk->disk_name, req->cmd,
  304. (long)blk_rq_pos(req), blk_rq_sectors(req),
  305. bio_data(req->bio));
  306. swim3_dbg(" current_nr_sectors=%u\n",
  307. blk_rq_cur_sectors(req));
  308. #endif
  309. if (blk_rq_pos(req) >= fs->total_secs) {
  310. swim3_dbg(" pos out of bounds (%ld, max is %ld)\n",
  311. (long)blk_rq_pos(req), (long)fs->total_secs);
  312. swim3_end_request(fs, BLK_STS_IOERR, 0);
  313. continue;
  314. }
  315. if (fs->ejected) {
  316. swim3_dbg("%s", " disk ejected\n");
  317. swim3_end_request(fs, BLK_STS_IOERR, 0);
  318. continue;
  319. }
  320. if (rq_data_dir(req) == WRITE) {
  321. if (fs->write_prot < 0)
  322. fs->write_prot = swim3_readbit(fs, WRITE_PROT);
  323. if (fs->write_prot) {
  324. swim3_dbg("%s", " try to write, disk write protected\n");
  325. swim3_end_request(fs, BLK_STS_IOERR, 0);
  326. continue;
  327. }
  328. }
  329. /* Do not remove the cast. blk_rq_pos(req) is now a
  330. * sector_t and can be 64 bits, but it will never go
  331. * past 32 bits for this driver anyway, so we can
  332. * safely cast it down and not have to do a 64/32
  333. * division
  334. */
  335. fs->req_cyl = ((long)blk_rq_pos(req)) / fs->secpercyl;
  336. x = ((long)blk_rq_pos(req)) % fs->secpercyl;
  337. fs->head = x / fs->secpertrack;
  338. fs->req_sector = x % fs->secpertrack + 1;
  339. fs->state = do_transfer;
  340. fs->retries = 0;
  341. act(fs);
  342. }
  343. }
  344. static void do_fd_request(struct request_queue * q)
  345. {
  346. start_request(q->queuedata);
  347. }
  348. static void set_timeout(struct floppy_state *fs, int nticks,
  349. void (*proc)(struct timer_list *t))
  350. {
  351. if (fs->timeout_pending)
  352. del_timer(&fs->timeout);
  353. fs->timeout.expires = jiffies + nticks;
  354. fs->timeout.function = proc;
  355. add_timer(&fs->timeout);
  356. fs->timeout_pending = 1;
  357. }
  358. static inline void scan_track(struct floppy_state *fs)
  359. {
  360. struct swim3 __iomem *sw = fs->swim3;
  361. swim3_select(fs, READ_DATA_0);
  362. in_8(&sw->intr); /* clear SEEN_SECTOR bit */
  363. in_8(&sw->error);
  364. out_8(&sw->intr_enable, SEEN_SECTOR);
  365. out_8(&sw->control_bis, DO_ACTION);
  366. /* enable intr when track found */
  367. set_timeout(fs, HZ, scan_timeout); /* enable timeout */
  368. }
  369. static inline void seek_track(struct floppy_state *fs, int n)
  370. {
  371. struct swim3 __iomem *sw = fs->swim3;
  372. if (n >= 0) {
  373. swim3_action(fs, SEEK_POSITIVE);
  374. sw->nseek = n;
  375. } else {
  376. swim3_action(fs, SEEK_NEGATIVE);
  377. sw->nseek = -n;
  378. }
  379. fs->expect_cyl = (fs->cur_cyl >= 0)? fs->cur_cyl + n: -1;
  380. swim3_select(fs, STEP);
  381. in_8(&sw->error);
  382. /* enable intr when seek finished */
  383. out_8(&sw->intr_enable, SEEK_DONE);
  384. out_8(&sw->control_bis, DO_SEEK);
  385. set_timeout(fs, 3*HZ, seek_timeout); /* enable timeout */
  386. fs->settle_time = 0;
  387. }
  388. static inline void init_dma(struct dbdma_cmd *cp, int cmd,
  389. void *buf, int count)
  390. {
  391. cp->req_count = cpu_to_le16(count);
  392. cp->command = cpu_to_le16(cmd);
  393. cp->phy_addr = cpu_to_le32(virt_to_bus(buf));
  394. cp->xfer_status = 0;
  395. }
  396. static inline void setup_transfer(struct floppy_state *fs)
  397. {
  398. int n;
  399. struct swim3 __iomem *sw = fs->swim3;
  400. struct dbdma_cmd *cp = fs->dma_cmd;
  401. struct dbdma_regs __iomem *dr = fs->dma;
  402. struct request *req = fs->cur_req;
  403. if (blk_rq_cur_sectors(req) <= 0) {
  404. swim3_warn("%s", "Transfer 0 sectors ?\n");
  405. return;
  406. }
  407. if (rq_data_dir(req) == WRITE)
  408. n = 1;
  409. else {
  410. n = fs->secpertrack - fs->req_sector + 1;
  411. if (n > blk_rq_cur_sectors(req))
  412. n = blk_rq_cur_sectors(req);
  413. }
  414. swim3_dbg(" setup xfer at sect %d (of %d) head %d for %d\n",
  415. fs->req_sector, fs->secpertrack, fs->head, n);
  416. fs->scount = n;
  417. swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0);
  418. out_8(&sw->sector, fs->req_sector);
  419. out_8(&sw->nsect, n);
  420. out_8(&sw->gap3, 0);
  421. out_le32(&dr->cmdptr, virt_to_bus(cp));
  422. if (rq_data_dir(req) == WRITE) {
  423. /* Set up 3 dma commands: write preamble, data, postamble */
  424. init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble));
  425. ++cp;
  426. init_dma(cp, OUTPUT_MORE, bio_data(req->bio), 512);
  427. ++cp;
  428. init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble));
  429. } else {
  430. init_dma(cp, INPUT_LAST, bio_data(req->bio), n * 512);
  431. }
  432. ++cp;
  433. out_le16(&cp->command, DBDMA_STOP);
  434. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  435. in_8(&sw->error);
  436. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  437. if (rq_data_dir(req) == WRITE)
  438. out_8(&sw->control_bis, WRITE_SECTORS);
  439. in_8(&sw->intr);
  440. out_le32(&dr->control, (RUN << 16) | RUN);
  441. /* enable intr when transfer complete */
  442. out_8(&sw->intr_enable, TRANSFER_DONE);
  443. out_8(&sw->control_bis, DO_ACTION);
  444. set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */
  445. }
  446. static void act(struct floppy_state *fs)
  447. {
  448. for (;;) {
  449. swim3_dbg(" act loop, state=%d, req_cyl=%d, cur_cyl=%d\n",
  450. fs->state, fs->req_cyl, fs->cur_cyl);
  451. switch (fs->state) {
  452. case idle:
  453. return; /* XXX shouldn't get here */
  454. case locating:
  455. if (swim3_readbit(fs, TRACK_ZERO)) {
  456. swim3_dbg("%s", " locate track 0\n");
  457. fs->cur_cyl = 0;
  458. if (fs->req_cyl == 0)
  459. fs->state = do_transfer;
  460. else
  461. fs->state = seeking;
  462. break;
  463. }
  464. scan_track(fs);
  465. return;
  466. case seeking:
  467. if (fs->cur_cyl < 0) {
  468. fs->expect_cyl = -1;
  469. fs->state = locating;
  470. break;
  471. }
  472. if (fs->req_cyl == fs->cur_cyl) {
  473. swim3_warn("%s", "Whoops, seeking 0\n");
  474. fs->state = do_transfer;
  475. break;
  476. }
  477. seek_track(fs, fs->req_cyl - fs->cur_cyl);
  478. return;
  479. case settling:
  480. /* check for SEEK_COMPLETE after 30ms */
  481. fs->settle_time = (HZ + 32) / 33;
  482. set_timeout(fs, fs->settle_time, settle_timeout);
  483. return;
  484. case do_transfer:
  485. if (fs->cur_cyl != fs->req_cyl) {
  486. if (fs->retries > 5) {
  487. swim3_err("Wrong cylinder in transfer, want: %d got %d\n",
  488. fs->req_cyl, fs->cur_cyl);
  489. swim3_end_request(fs, BLK_STS_IOERR, 0);
  490. fs->state = idle;
  491. return;
  492. }
  493. fs->state = seeking;
  494. break;
  495. }
  496. setup_transfer(fs);
  497. return;
  498. case jogging:
  499. seek_track(fs, -5);
  500. return;
  501. default:
  502. swim3_err("Unknown state %d\n", fs->state);
  503. return;
  504. }
  505. }
  506. }
  507. static void scan_timeout(struct timer_list *t)
  508. {
  509. struct floppy_state *fs = from_timer(fs, t, timeout);
  510. struct swim3 __iomem *sw = fs->swim3;
  511. unsigned long flags;
  512. swim3_dbg("* scan timeout, state=%d\n", fs->state);
  513. spin_lock_irqsave(&swim3_lock, flags);
  514. fs->timeout_pending = 0;
  515. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  516. out_8(&sw->select, RELAX);
  517. out_8(&sw->intr_enable, 0);
  518. fs->cur_cyl = -1;
  519. if (fs->retries > 5) {
  520. swim3_end_request(fs, BLK_STS_IOERR, 0);
  521. fs->state = idle;
  522. start_request(fs);
  523. } else {
  524. fs->state = jogging;
  525. act(fs);
  526. }
  527. spin_unlock_irqrestore(&swim3_lock, flags);
  528. }
  529. static void seek_timeout(struct timer_list *t)
  530. {
  531. struct floppy_state *fs = from_timer(fs, t, timeout);
  532. struct swim3 __iomem *sw = fs->swim3;
  533. unsigned long flags;
  534. swim3_dbg("* seek timeout, state=%d\n", fs->state);
  535. spin_lock_irqsave(&swim3_lock, flags);
  536. fs->timeout_pending = 0;
  537. out_8(&sw->control_bic, DO_SEEK);
  538. out_8(&sw->select, RELAX);
  539. out_8(&sw->intr_enable, 0);
  540. swim3_err("%s", "Seek timeout\n");
  541. swim3_end_request(fs, BLK_STS_IOERR, 0);
  542. fs->state = idle;
  543. start_request(fs);
  544. spin_unlock_irqrestore(&swim3_lock, flags);
  545. }
  546. static void settle_timeout(struct timer_list *t)
  547. {
  548. struct floppy_state *fs = from_timer(fs, t, timeout);
  549. struct swim3 __iomem *sw = fs->swim3;
  550. unsigned long flags;
  551. swim3_dbg("* settle timeout, state=%d\n", fs->state);
  552. spin_lock_irqsave(&swim3_lock, flags);
  553. fs->timeout_pending = 0;
  554. if (swim3_readbit(fs, SEEK_COMPLETE)) {
  555. out_8(&sw->select, RELAX);
  556. fs->state = locating;
  557. act(fs);
  558. goto unlock;
  559. }
  560. out_8(&sw->select, RELAX);
  561. if (fs->settle_time < 2*HZ) {
  562. ++fs->settle_time;
  563. set_timeout(fs, 1, settle_timeout);
  564. goto unlock;
  565. }
  566. swim3_err("%s", "Seek settle timeout\n");
  567. swim3_end_request(fs, BLK_STS_IOERR, 0);
  568. fs->state = idle;
  569. start_request(fs);
  570. unlock:
  571. spin_unlock_irqrestore(&swim3_lock, flags);
  572. }
  573. static void xfer_timeout(struct timer_list *t)
  574. {
  575. struct floppy_state *fs = from_timer(fs, t, timeout);
  576. struct swim3 __iomem *sw = fs->swim3;
  577. struct dbdma_regs __iomem *dr = fs->dma;
  578. unsigned long flags;
  579. int n;
  580. swim3_dbg("* xfer timeout, state=%d\n", fs->state);
  581. spin_lock_irqsave(&swim3_lock, flags);
  582. fs->timeout_pending = 0;
  583. out_le32(&dr->control, RUN << 16);
  584. /* We must wait a bit for dbdma to stop */
  585. for (n = 0; (in_le32(&dr->status) & ACTIVE) && n < 1000; n++)
  586. udelay(1);
  587. out_8(&sw->intr_enable, 0);
  588. out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
  589. out_8(&sw->select, RELAX);
  590. swim3_err("Timeout %sing sector %ld\n",
  591. (rq_data_dir(fs->cur_req)==WRITE? "writ": "read"),
  592. (long)blk_rq_pos(fs->cur_req));
  593. swim3_end_request(fs, BLK_STS_IOERR, 0);
  594. fs->state = idle;
  595. start_request(fs);
  596. spin_unlock_irqrestore(&swim3_lock, flags);
  597. }
  598. static irqreturn_t swim3_interrupt(int irq, void *dev_id)
  599. {
  600. struct floppy_state *fs = (struct floppy_state *) dev_id;
  601. struct swim3 __iomem *sw = fs->swim3;
  602. int intr, err, n;
  603. int stat, resid;
  604. struct dbdma_regs __iomem *dr;
  605. struct dbdma_cmd *cp;
  606. unsigned long flags;
  607. struct request *req = fs->cur_req;
  608. swim3_dbg("* interrupt, state=%d\n", fs->state);
  609. spin_lock_irqsave(&swim3_lock, flags);
  610. intr = in_8(&sw->intr);
  611. err = (intr & ERROR_INTR)? in_8(&sw->error): 0;
  612. if ((intr & ERROR_INTR) && fs->state != do_transfer)
  613. swim3_err("Non-transfer error interrupt: state=%d, dir=%x, intr=%x, err=%x\n",
  614. fs->state, rq_data_dir(req), intr, err);
  615. switch (fs->state) {
  616. case locating:
  617. if (intr & SEEN_SECTOR) {
  618. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  619. out_8(&sw->select, RELAX);
  620. out_8(&sw->intr_enable, 0);
  621. del_timer(&fs->timeout);
  622. fs->timeout_pending = 0;
  623. if (sw->ctrack == 0xff) {
  624. swim3_err("%s", "Seen sector but cyl=ff?\n");
  625. fs->cur_cyl = -1;
  626. if (fs->retries > 5) {
  627. swim3_end_request(fs, BLK_STS_IOERR, 0);
  628. fs->state = idle;
  629. start_request(fs);
  630. } else {
  631. fs->state = jogging;
  632. act(fs);
  633. }
  634. break;
  635. }
  636. fs->cur_cyl = sw->ctrack;
  637. fs->cur_sector = sw->csect;
  638. if (fs->expect_cyl != -1 && fs->expect_cyl != fs->cur_cyl)
  639. swim3_err("Expected cyl %d, got %d\n",
  640. fs->expect_cyl, fs->cur_cyl);
  641. fs->state = do_transfer;
  642. act(fs);
  643. }
  644. break;
  645. case seeking:
  646. case jogging:
  647. if (sw->nseek == 0) {
  648. out_8(&sw->control_bic, DO_SEEK);
  649. out_8(&sw->select, RELAX);
  650. out_8(&sw->intr_enable, 0);
  651. del_timer(&fs->timeout);
  652. fs->timeout_pending = 0;
  653. if (fs->state == seeking)
  654. ++fs->retries;
  655. fs->state = settling;
  656. act(fs);
  657. }
  658. break;
  659. case settling:
  660. out_8(&sw->intr_enable, 0);
  661. del_timer(&fs->timeout);
  662. fs->timeout_pending = 0;
  663. act(fs);
  664. break;
  665. case do_transfer:
  666. if ((intr & (ERROR_INTR | TRANSFER_DONE)) == 0)
  667. break;
  668. out_8(&sw->intr_enable, 0);
  669. out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
  670. out_8(&sw->select, RELAX);
  671. del_timer(&fs->timeout);
  672. fs->timeout_pending = 0;
  673. dr = fs->dma;
  674. cp = fs->dma_cmd;
  675. if (rq_data_dir(req) == WRITE)
  676. ++cp;
  677. /*
  678. * Check that the main data transfer has finished.
  679. * On writing, the swim3 sometimes doesn't use
  680. * up all the bytes of the postamble, so we can still
  681. * see DMA active here. That doesn't matter as long
  682. * as all the sector data has been transferred.
  683. */
  684. if ((intr & ERROR_INTR) == 0 && cp->xfer_status == 0) {
  685. /* wait a little while for DMA to complete */
  686. for (n = 0; n < 100; ++n) {
  687. if (cp->xfer_status != 0)
  688. break;
  689. udelay(1);
  690. barrier();
  691. }
  692. }
  693. /* turn off DMA */
  694. out_le32(&dr->control, (RUN | PAUSE) << 16);
  695. stat = le16_to_cpu(cp->xfer_status);
  696. resid = le16_to_cpu(cp->res_count);
  697. if (intr & ERROR_INTR) {
  698. n = fs->scount - 1 - resid / 512;
  699. if (n > 0) {
  700. blk_update_request(req, 0, n << 9);
  701. fs->req_sector += n;
  702. }
  703. if (fs->retries < 5) {
  704. ++fs->retries;
  705. act(fs);
  706. } else {
  707. swim3_err("Error %sing block %ld (err=%x)\n",
  708. rq_data_dir(req) == WRITE? "writ": "read",
  709. (long)blk_rq_pos(req), err);
  710. swim3_end_request(fs, BLK_STS_IOERR, 0);
  711. fs->state = idle;
  712. }
  713. } else {
  714. if ((stat & ACTIVE) == 0 || resid != 0) {
  715. /* musta been an error */
  716. swim3_err("fd dma error: stat=%x resid=%d\n", stat, resid);
  717. swim3_err(" state=%d, dir=%x, intr=%x, err=%x\n",
  718. fs->state, rq_data_dir(req), intr, err);
  719. swim3_end_request(fs, BLK_STS_IOERR, 0);
  720. fs->state = idle;
  721. start_request(fs);
  722. break;
  723. }
  724. fs->retries = 0;
  725. if (swim3_end_request(fs, 0, fs->scount << 9)) {
  726. fs->req_sector += fs->scount;
  727. if (fs->req_sector > fs->secpertrack) {
  728. fs->req_sector -= fs->secpertrack;
  729. if (++fs->head > 1) {
  730. fs->head = 0;
  731. ++fs->req_cyl;
  732. }
  733. }
  734. act(fs);
  735. } else
  736. fs->state = idle;
  737. }
  738. if (fs->state == idle)
  739. start_request(fs);
  740. break;
  741. default:
  742. swim3_err("Don't know what to do in state %d\n", fs->state);
  743. }
  744. spin_unlock_irqrestore(&swim3_lock, flags);
  745. return IRQ_HANDLED;
  746. }
  747. /*
  748. static void fd_dma_interrupt(int irq, void *dev_id)
  749. {
  750. }
  751. */
  752. /* Called under the mutex to grab exclusive access to a drive */
  753. static int grab_drive(struct floppy_state *fs, enum swim_state state,
  754. int interruptible)
  755. {
  756. unsigned long flags;
  757. swim3_dbg("%s", "-> grab drive\n");
  758. spin_lock_irqsave(&swim3_lock, flags);
  759. if (fs->state != idle && fs->state != available) {
  760. ++fs->wanted;
  761. /* this will enable irqs in order to sleep */
  762. if (!interruptible)
  763. wait_event_lock_irq(fs->wait,
  764. fs->state == available,
  765. swim3_lock);
  766. else if (wait_event_interruptible_lock_irq(fs->wait,
  767. fs->state == available,
  768. swim3_lock)) {
  769. --fs->wanted;
  770. spin_unlock_irqrestore(&swim3_lock, flags);
  771. return -EINTR;
  772. }
  773. --fs->wanted;
  774. }
  775. fs->state = state;
  776. spin_unlock_irqrestore(&swim3_lock, flags);
  777. return 0;
  778. }
  779. static void release_drive(struct floppy_state *fs)
  780. {
  781. unsigned long flags;
  782. swim3_dbg("%s", "-> release drive\n");
  783. spin_lock_irqsave(&swim3_lock, flags);
  784. fs->state = idle;
  785. start_request(fs);
  786. spin_unlock_irqrestore(&swim3_lock, flags);
  787. }
  788. static int fd_eject(struct floppy_state *fs)
  789. {
  790. int err, n;
  791. err = grab_drive(fs, ejecting, 1);
  792. if (err)
  793. return err;
  794. swim3_action(fs, EJECT);
  795. for (n = 20; n > 0; --n) {
  796. if (signal_pending(current)) {
  797. err = -EINTR;
  798. break;
  799. }
  800. swim3_select(fs, RELAX);
  801. schedule_timeout_interruptible(1);
  802. if (swim3_readbit(fs, DISK_IN) == 0)
  803. break;
  804. }
  805. swim3_select(fs, RELAX);
  806. udelay(150);
  807. fs->ejected = 1;
  808. release_drive(fs);
  809. return err;
  810. }
  811. static struct floppy_struct floppy_type =
  812. { 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,NULL }; /* 7 1.44MB 3.5" */
  813. static int floppy_locked_ioctl(struct block_device *bdev, fmode_t mode,
  814. unsigned int cmd, unsigned long param)
  815. {
  816. struct floppy_state *fs = bdev->bd_disk->private_data;
  817. int err;
  818. if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))
  819. return -EPERM;
  820. if (fs->mdev->media_bay &&
  821. check_media_bay(fs->mdev->media_bay) != MB_FD)
  822. return -ENXIO;
  823. switch (cmd) {
  824. case FDEJECT:
  825. if (fs->ref_count != 1)
  826. return -EBUSY;
  827. err = fd_eject(fs);
  828. return err;
  829. case FDGETPRM:
  830. if (copy_to_user((void __user *) param, &floppy_type,
  831. sizeof(struct floppy_struct)))
  832. return -EFAULT;
  833. return 0;
  834. }
  835. return -ENOTTY;
  836. }
  837. static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
  838. unsigned int cmd, unsigned long param)
  839. {
  840. int ret;
  841. mutex_lock(&swim3_mutex);
  842. ret = floppy_locked_ioctl(bdev, mode, cmd, param);
  843. mutex_unlock(&swim3_mutex);
  844. return ret;
  845. }
  846. static int floppy_open(struct block_device *bdev, fmode_t mode)
  847. {
  848. struct floppy_state *fs = bdev->bd_disk->private_data;
  849. struct swim3 __iomem *sw = fs->swim3;
  850. int n, err = 0;
  851. if (fs->ref_count == 0) {
  852. if (fs->mdev->media_bay &&
  853. check_media_bay(fs->mdev->media_bay) != MB_FD)
  854. return -ENXIO;
  855. out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2);
  856. out_8(&sw->control_bic, 0xff);
  857. out_8(&sw->mode, 0x95);
  858. udelay(10);
  859. out_8(&sw->intr_enable, 0);
  860. out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE);
  861. swim3_action(fs, MOTOR_ON);
  862. fs->write_prot = -1;
  863. fs->cur_cyl = -1;
  864. for (n = 0; n < 2 * HZ; ++n) {
  865. if (n >= HZ/30 && swim3_readbit(fs, SEEK_COMPLETE))
  866. break;
  867. if (signal_pending(current)) {
  868. err = -EINTR;
  869. break;
  870. }
  871. swim3_select(fs, RELAX);
  872. schedule_timeout_interruptible(1);
  873. }
  874. if (err == 0 && (swim3_readbit(fs, SEEK_COMPLETE) == 0
  875. || swim3_readbit(fs, DISK_IN) == 0))
  876. err = -ENXIO;
  877. swim3_action(fs, SETMFM);
  878. swim3_select(fs, RELAX);
  879. } else if (fs->ref_count == -1 || mode & FMODE_EXCL)
  880. return -EBUSY;
  881. if (err == 0 && (mode & FMODE_NDELAY) == 0
  882. && (mode & (FMODE_READ|FMODE_WRITE))) {
  883. check_disk_change(bdev);
  884. if (fs->ejected)
  885. err = -ENXIO;
  886. }
  887. if (err == 0 && (mode & FMODE_WRITE)) {
  888. if (fs->write_prot < 0)
  889. fs->write_prot = swim3_readbit(fs, WRITE_PROT);
  890. if (fs->write_prot)
  891. err = -EROFS;
  892. }
  893. if (err) {
  894. if (fs->ref_count == 0) {
  895. swim3_action(fs, MOTOR_OFF);
  896. out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE);
  897. swim3_select(fs, RELAX);
  898. }
  899. return err;
  900. }
  901. if (mode & FMODE_EXCL)
  902. fs->ref_count = -1;
  903. else
  904. ++fs->ref_count;
  905. return 0;
  906. }
  907. static int floppy_unlocked_open(struct block_device *bdev, fmode_t mode)
  908. {
  909. int ret;
  910. mutex_lock(&swim3_mutex);
  911. ret = floppy_open(bdev, mode);
  912. mutex_unlock(&swim3_mutex);
  913. return ret;
  914. }
  915. static void floppy_release(struct gendisk *disk, fmode_t mode)
  916. {
  917. struct floppy_state *fs = disk->private_data;
  918. struct swim3 __iomem *sw = fs->swim3;
  919. mutex_lock(&swim3_mutex);
  920. if (fs->ref_count > 0)
  921. --fs->ref_count;
  922. else if (fs->ref_count == -1)
  923. fs->ref_count = 0;
  924. if (fs->ref_count == 0) {
  925. swim3_action(fs, MOTOR_OFF);
  926. out_8(&sw->control_bic, 0xff);
  927. swim3_select(fs, RELAX);
  928. }
  929. mutex_unlock(&swim3_mutex);
  930. }
  931. static unsigned int floppy_check_events(struct gendisk *disk,
  932. unsigned int clearing)
  933. {
  934. struct floppy_state *fs = disk->private_data;
  935. return fs->ejected ? DISK_EVENT_MEDIA_CHANGE : 0;
  936. }
  937. static int floppy_revalidate(struct gendisk *disk)
  938. {
  939. struct floppy_state *fs = disk->private_data;
  940. struct swim3 __iomem *sw;
  941. int ret, n;
  942. if (fs->mdev->media_bay &&
  943. check_media_bay(fs->mdev->media_bay) != MB_FD)
  944. return -ENXIO;
  945. sw = fs->swim3;
  946. grab_drive(fs, revalidating, 0);
  947. out_8(&sw->intr_enable, 0);
  948. out_8(&sw->control_bis, DRIVE_ENABLE);
  949. swim3_action(fs, MOTOR_ON); /* necessary? */
  950. fs->write_prot = -1;
  951. fs->cur_cyl = -1;
  952. mdelay(1);
  953. for (n = HZ; n > 0; --n) {
  954. if (swim3_readbit(fs, SEEK_COMPLETE))
  955. break;
  956. if (signal_pending(current))
  957. break;
  958. swim3_select(fs, RELAX);
  959. schedule_timeout_interruptible(1);
  960. }
  961. ret = swim3_readbit(fs, SEEK_COMPLETE) == 0
  962. || swim3_readbit(fs, DISK_IN) == 0;
  963. if (ret)
  964. swim3_action(fs, MOTOR_OFF);
  965. else {
  966. fs->ejected = 0;
  967. swim3_action(fs, SETMFM);
  968. }
  969. swim3_select(fs, RELAX);
  970. release_drive(fs);
  971. return ret;
  972. }
  973. static const struct block_device_operations floppy_fops = {
  974. .open = floppy_unlocked_open,
  975. .release = floppy_release,
  976. .ioctl = floppy_ioctl,
  977. .check_events = floppy_check_events,
  978. .revalidate_disk= floppy_revalidate,
  979. };
  980. static void swim3_mb_event(struct macio_dev* mdev, int mb_state)
  981. {
  982. struct floppy_state *fs = macio_get_drvdata(mdev);
  983. struct swim3 __iomem *sw;
  984. if (!fs)
  985. return;
  986. sw = fs->swim3;
  987. if (mb_state != MB_FD)
  988. return;
  989. /* Clear state */
  990. out_8(&sw->intr_enable, 0);
  991. in_8(&sw->intr);
  992. in_8(&sw->error);
  993. }
  994. static int swim3_add_device(struct macio_dev *mdev, int index)
  995. {
  996. struct device_node *swim = mdev->ofdev.dev.of_node;
  997. struct floppy_state *fs = &floppy_states[index];
  998. int rc = -EBUSY;
  999. /* Do this first for message macros */
  1000. memset(fs, 0, sizeof(*fs));
  1001. fs->mdev = mdev;
  1002. fs->index = index;
  1003. /* Check & Request resources */
  1004. if (macio_resource_count(mdev) < 2) {
  1005. swim3_err("%s", "No address in device-tree\n");
  1006. return -ENXIO;
  1007. }
  1008. if (macio_irq_count(mdev) < 1) {
  1009. swim3_err("%s", "No interrupt in device-tree\n");
  1010. return -ENXIO;
  1011. }
  1012. if (macio_request_resource(mdev, 0, "swim3 (mmio)")) {
  1013. swim3_err("%s", "Can't request mmio resource\n");
  1014. return -EBUSY;
  1015. }
  1016. if (macio_request_resource(mdev, 1, "swim3 (dma)")) {
  1017. swim3_err("%s", "Can't request dma resource\n");
  1018. macio_release_resource(mdev, 0);
  1019. return -EBUSY;
  1020. }
  1021. dev_set_drvdata(&mdev->ofdev.dev, fs);
  1022. if (mdev->media_bay == NULL)
  1023. pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1);
  1024. fs->state = idle;
  1025. fs->swim3 = (struct swim3 __iomem *)
  1026. ioremap(macio_resource_start(mdev, 0), 0x200);
  1027. if (fs->swim3 == NULL) {
  1028. swim3_err("%s", "Couldn't map mmio registers\n");
  1029. rc = -ENOMEM;
  1030. goto out_release;
  1031. }
  1032. fs->dma = (struct dbdma_regs __iomem *)
  1033. ioremap(macio_resource_start(mdev, 1), 0x200);
  1034. if (fs->dma == NULL) {
  1035. swim3_err("%s", "Couldn't map dma registers\n");
  1036. iounmap(fs->swim3);
  1037. rc = -ENOMEM;
  1038. goto out_release;
  1039. }
  1040. fs->swim3_intr = macio_irq(mdev, 0);
  1041. fs->dma_intr = macio_irq(mdev, 1);
  1042. fs->cur_cyl = -1;
  1043. fs->cur_sector = -1;
  1044. fs->secpercyl = 36;
  1045. fs->secpertrack = 18;
  1046. fs->total_secs = 2880;
  1047. init_waitqueue_head(&fs->wait);
  1048. fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space);
  1049. memset(fs->dma_cmd, 0, 2 * sizeof(struct dbdma_cmd));
  1050. fs->dma_cmd[1].command = cpu_to_le16(DBDMA_STOP);
  1051. if (mdev->media_bay == NULL || check_media_bay(mdev->media_bay) == MB_FD)
  1052. swim3_mb_event(mdev, MB_FD);
  1053. if (request_irq(fs->swim3_intr, swim3_interrupt, 0, "SWIM3", fs)) {
  1054. swim3_err("%s", "Couldn't request interrupt\n");
  1055. pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 0);
  1056. goto out_unmap;
  1057. return -EBUSY;
  1058. }
  1059. timer_setup(&fs->timeout, NULL, 0);
  1060. swim3_info("SWIM3 floppy controller %s\n",
  1061. mdev->media_bay ? "in media bay" : "");
  1062. return 0;
  1063. out_unmap:
  1064. iounmap(fs->dma);
  1065. iounmap(fs->swim3);
  1066. out_release:
  1067. macio_release_resource(mdev, 0);
  1068. macio_release_resource(mdev, 1);
  1069. return rc;
  1070. }
  1071. static int swim3_attach(struct macio_dev *mdev,
  1072. const struct of_device_id *match)
  1073. {
  1074. struct gendisk *disk;
  1075. int index, rc;
  1076. index = floppy_count++;
  1077. if (index >= MAX_FLOPPIES)
  1078. return -ENXIO;
  1079. /* Add the drive */
  1080. rc = swim3_add_device(mdev, index);
  1081. if (rc)
  1082. return rc;
  1083. /* Now register that disk. Same comment about failure handling */
  1084. disk = disks[index] = alloc_disk(1);
  1085. if (disk == NULL)
  1086. return -ENOMEM;
  1087. disk->queue = blk_init_queue(do_fd_request, &swim3_lock);
  1088. if (disk->queue == NULL) {
  1089. put_disk(disk);
  1090. return -ENOMEM;
  1091. }
  1092. blk_queue_bounce_limit(disk->queue, BLK_BOUNCE_HIGH);
  1093. disk->queue->queuedata = &floppy_states[index];
  1094. if (index == 0) {
  1095. /* If we failed, there isn't much we can do as the driver is still
  1096. * too dumb to remove the device, just bail out
  1097. */
  1098. if (register_blkdev(FLOPPY_MAJOR, "fd"))
  1099. return 0;
  1100. }
  1101. disk->major = FLOPPY_MAJOR;
  1102. disk->first_minor = index;
  1103. disk->fops = &floppy_fops;
  1104. disk->private_data = &floppy_states[index];
  1105. disk->flags |= GENHD_FL_REMOVABLE;
  1106. sprintf(disk->disk_name, "fd%d", index);
  1107. set_capacity(disk, 2880);
  1108. add_disk(disk);
  1109. return 0;
  1110. }
  1111. static const struct of_device_id swim3_match[] =
  1112. {
  1113. {
  1114. .name = "swim3",
  1115. },
  1116. {
  1117. .compatible = "ohare-swim3"
  1118. },
  1119. {
  1120. .compatible = "swim3"
  1121. },
  1122. { /* end of list */ }
  1123. };
  1124. static struct macio_driver swim3_driver =
  1125. {
  1126. .driver = {
  1127. .name = "swim3",
  1128. .of_match_table = swim3_match,
  1129. },
  1130. .probe = swim3_attach,
  1131. #ifdef CONFIG_PMAC_MEDIABAY
  1132. .mediabay_event = swim3_mb_event,
  1133. #endif
  1134. #if 0
  1135. .suspend = swim3_suspend,
  1136. .resume = swim3_resume,
  1137. #endif
  1138. };
  1139. int swim3_init(void)
  1140. {
  1141. macio_register_driver(&swim3_driver);
  1142. return 0;
  1143. }
  1144. module_init(swim3_init)
  1145. MODULE_LICENSE("GPL");
  1146. MODULE_AUTHOR("Paul Mackerras");
  1147. MODULE_ALIAS_BLOCKDEV_MAJOR(FLOPPY_MAJOR);