dfl-fme-main.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for FPGA Management Engine (FME)
  4. *
  5. * Copyright (C) 2017-2018 Intel Corporation, Inc.
  6. *
  7. * Authors:
  8. * Kang Luwei <luwei.kang@intel.com>
  9. * Xiao Guangrong <guangrong.xiao@linux.intel.com>
  10. * Joseph Grecco <joe.grecco@intel.com>
  11. * Enno Luebbers <enno.luebbers@intel.com>
  12. * Tim Whisonant <tim.whisonant@intel.com>
  13. * Ananda Ravuri <ananda.ravuri@intel.com>
  14. * Henry Mitchel <henry.mitchel@intel.com>
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/fpga-dfl.h>
  19. #include "dfl.h"
  20. #include "dfl-fme.h"
  21. static ssize_t ports_num_show(struct device *dev,
  22. struct device_attribute *attr, char *buf)
  23. {
  24. void __iomem *base;
  25. u64 v;
  26. base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
  27. v = readq(base + FME_HDR_CAP);
  28. return scnprintf(buf, PAGE_SIZE, "%u\n",
  29. (unsigned int)FIELD_GET(FME_CAP_NUM_PORTS, v));
  30. }
  31. static DEVICE_ATTR_RO(ports_num);
  32. /*
  33. * Bitstream (static FPGA region) identifier number. It contains the
  34. * detailed version and other information of this static FPGA region.
  35. */
  36. static ssize_t bitstream_id_show(struct device *dev,
  37. struct device_attribute *attr, char *buf)
  38. {
  39. void __iomem *base;
  40. u64 v;
  41. base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
  42. v = readq(base + FME_HDR_BITSTREAM_ID);
  43. return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
  44. }
  45. static DEVICE_ATTR_RO(bitstream_id);
  46. /*
  47. * Bitstream (static FPGA region) meta data. It contains the synthesis
  48. * date, seed and other information of this static FPGA region.
  49. */
  50. static ssize_t bitstream_metadata_show(struct device *dev,
  51. struct device_attribute *attr, char *buf)
  52. {
  53. void __iomem *base;
  54. u64 v;
  55. base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
  56. v = readq(base + FME_HDR_BITSTREAM_MD);
  57. return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
  58. }
  59. static DEVICE_ATTR_RO(bitstream_metadata);
  60. static const struct attribute *fme_hdr_attrs[] = {
  61. &dev_attr_ports_num.attr,
  62. &dev_attr_bitstream_id.attr,
  63. &dev_attr_bitstream_metadata.attr,
  64. NULL,
  65. };
  66. static int fme_hdr_init(struct platform_device *pdev,
  67. struct dfl_feature *feature)
  68. {
  69. void __iomem *base = feature->ioaddr;
  70. int ret;
  71. dev_dbg(&pdev->dev, "FME HDR Init.\n");
  72. dev_dbg(&pdev->dev, "FME cap %llx.\n",
  73. (unsigned long long)readq(base + FME_HDR_CAP));
  74. ret = sysfs_create_files(&pdev->dev.kobj, fme_hdr_attrs);
  75. if (ret)
  76. return ret;
  77. return 0;
  78. }
  79. static void fme_hdr_uinit(struct platform_device *pdev,
  80. struct dfl_feature *feature)
  81. {
  82. dev_dbg(&pdev->dev, "FME HDR UInit.\n");
  83. sysfs_remove_files(&pdev->dev.kobj, fme_hdr_attrs);
  84. }
  85. static const struct dfl_feature_ops fme_hdr_ops = {
  86. .init = fme_hdr_init,
  87. .uinit = fme_hdr_uinit,
  88. };
  89. static struct dfl_feature_driver fme_feature_drvs[] = {
  90. {
  91. .id = FME_FEATURE_ID_HEADER,
  92. .ops = &fme_hdr_ops,
  93. },
  94. {
  95. .id = FME_FEATURE_ID_PR_MGMT,
  96. .ops = &pr_mgmt_ops,
  97. },
  98. {
  99. .ops = NULL,
  100. },
  101. };
  102. static long fme_ioctl_check_extension(struct dfl_feature_platform_data *pdata,
  103. unsigned long arg)
  104. {
  105. /* No extension support for now */
  106. return 0;
  107. }
  108. static int fme_open(struct inode *inode, struct file *filp)
  109. {
  110. struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode);
  111. struct dfl_feature_platform_data *pdata = dev_get_platdata(&fdev->dev);
  112. int ret;
  113. if (WARN_ON(!pdata))
  114. return -ENODEV;
  115. ret = dfl_feature_dev_use_begin(pdata);
  116. if (ret)
  117. return ret;
  118. dev_dbg(&fdev->dev, "Device File Open\n");
  119. filp->private_data = pdata;
  120. return 0;
  121. }
  122. static int fme_release(struct inode *inode, struct file *filp)
  123. {
  124. struct dfl_feature_platform_data *pdata = filp->private_data;
  125. struct platform_device *pdev = pdata->dev;
  126. dev_dbg(&pdev->dev, "Device File Release\n");
  127. dfl_feature_dev_use_end(pdata);
  128. return 0;
  129. }
  130. static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
  131. {
  132. struct dfl_feature_platform_data *pdata = filp->private_data;
  133. struct platform_device *pdev = pdata->dev;
  134. struct dfl_feature *f;
  135. long ret;
  136. dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd);
  137. switch (cmd) {
  138. case DFL_FPGA_GET_API_VERSION:
  139. return DFL_FPGA_API_VERSION;
  140. case DFL_FPGA_CHECK_EXTENSION:
  141. return fme_ioctl_check_extension(pdata, arg);
  142. default:
  143. /*
  144. * Let sub-feature's ioctl function to handle the cmd.
  145. * Sub-feature's ioctl returns -ENODEV when cmd is not
  146. * handled in this sub feature, and returns 0 or other
  147. * error code if cmd is handled.
  148. */
  149. dfl_fpga_dev_for_each_feature(pdata, f) {
  150. if (f->ops && f->ops->ioctl) {
  151. ret = f->ops->ioctl(pdev, f, cmd, arg);
  152. if (ret != -ENODEV)
  153. return ret;
  154. }
  155. }
  156. }
  157. return -EINVAL;
  158. }
  159. static int fme_dev_init(struct platform_device *pdev)
  160. {
  161. struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
  162. struct dfl_fme *fme;
  163. fme = devm_kzalloc(&pdev->dev, sizeof(*fme), GFP_KERNEL);
  164. if (!fme)
  165. return -ENOMEM;
  166. fme->pdata = pdata;
  167. mutex_lock(&pdata->lock);
  168. dfl_fpga_pdata_set_private(pdata, fme);
  169. mutex_unlock(&pdata->lock);
  170. return 0;
  171. }
  172. static void fme_dev_destroy(struct platform_device *pdev)
  173. {
  174. struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
  175. struct dfl_fme *fme;
  176. mutex_lock(&pdata->lock);
  177. fme = dfl_fpga_pdata_get_private(pdata);
  178. dfl_fpga_pdata_set_private(pdata, NULL);
  179. mutex_unlock(&pdata->lock);
  180. }
  181. static const struct file_operations fme_fops = {
  182. .owner = THIS_MODULE,
  183. .open = fme_open,
  184. .release = fme_release,
  185. .unlocked_ioctl = fme_ioctl,
  186. };
  187. static int fme_probe(struct platform_device *pdev)
  188. {
  189. int ret;
  190. ret = fme_dev_init(pdev);
  191. if (ret)
  192. goto exit;
  193. ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs);
  194. if (ret)
  195. goto dev_destroy;
  196. ret = dfl_fpga_dev_ops_register(pdev, &fme_fops, THIS_MODULE);
  197. if (ret)
  198. goto feature_uinit;
  199. return 0;
  200. feature_uinit:
  201. dfl_fpga_dev_feature_uinit(pdev);
  202. dev_destroy:
  203. fme_dev_destroy(pdev);
  204. exit:
  205. return ret;
  206. }
  207. static int fme_remove(struct platform_device *pdev)
  208. {
  209. dfl_fpga_dev_ops_unregister(pdev);
  210. dfl_fpga_dev_feature_uinit(pdev);
  211. fme_dev_destroy(pdev);
  212. return 0;
  213. }
  214. static struct platform_driver fme_driver = {
  215. .driver = {
  216. .name = DFL_FPGA_FEATURE_DEV_FME,
  217. },
  218. .probe = fme_probe,
  219. .remove = fme_remove,
  220. };
  221. module_platform_driver(fme_driver);
  222. MODULE_DESCRIPTION("FPGA Management Engine driver");
  223. MODULE_AUTHOR("Intel Corporation");
  224. MODULE_LICENSE("GPL v2");
  225. MODULE_ALIAS("platform:dfl-fme");