i2c-designware-pcidrv.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Synopsys DesignWare I2C adapter driver (master only).
  4. *
  5. * Based on the TI DAVINCI I2C adapter driver.
  6. *
  7. * Copyright (C) 2006 Texas Instruments.
  8. * Copyright (C) 2007 MontaVista Software Inc.
  9. * Copyright (C) 2009 Provigent Ltd.
  10. * Copyright (C) 2011, 2015, 2016 Intel Corporation.
  11. */
  12. #include <linux/acpi.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. #include <linux/errno.h>
  16. #include <linux/i2c.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/sched.h>
  24. #include <linux/slab.h>
  25. #include "i2c-designware-core.h"
  26. #define DRIVER_NAME "i2c-designware-pci"
  27. enum dw_pci_ctl_id_t {
  28. medfield,
  29. merrifield,
  30. baytrail,
  31. cherrytrail,
  32. haswell,
  33. };
  34. struct dw_scl_sda_cfg {
  35. u32 ss_hcnt;
  36. u32 fs_hcnt;
  37. u32 ss_lcnt;
  38. u32 fs_lcnt;
  39. u32 sda_hold;
  40. };
  41. struct dw_pci_controller {
  42. u32 bus_num;
  43. u32 bus_cfg;
  44. u32 tx_fifo_depth;
  45. u32 rx_fifo_depth;
  46. u32 clk_khz;
  47. u32 functionality;
  48. u32 flags;
  49. struct dw_scl_sda_cfg *scl_sda_cfg;
  50. int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
  51. };
  52. #define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
  53. DW_IC_CON_SLAVE_DISABLE | \
  54. DW_IC_CON_RESTART_EN)
  55. /* Merrifield HCNT/LCNT/SDA hold time */
  56. static struct dw_scl_sda_cfg mrfld_config = {
  57. .ss_hcnt = 0x2f8,
  58. .fs_hcnt = 0x87,
  59. .ss_lcnt = 0x37b,
  60. .fs_lcnt = 0x10a,
  61. };
  62. /* BayTrail HCNT/LCNT/SDA hold time */
  63. static struct dw_scl_sda_cfg byt_config = {
  64. .ss_hcnt = 0x200,
  65. .fs_hcnt = 0x55,
  66. .ss_lcnt = 0x200,
  67. .fs_lcnt = 0x99,
  68. .sda_hold = 0x6,
  69. };
  70. /* Haswell HCNT/LCNT/SDA hold time */
  71. static struct dw_scl_sda_cfg hsw_config = {
  72. .ss_hcnt = 0x01b0,
  73. .fs_hcnt = 0x48,
  74. .ss_lcnt = 0x01fb,
  75. .fs_lcnt = 0xa0,
  76. .sda_hold = 0x9,
  77. };
  78. static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
  79. {
  80. switch (pdev->device) {
  81. case 0x0817:
  82. c->bus_cfg &= ~DW_IC_CON_SPEED_MASK;
  83. c->bus_cfg |= DW_IC_CON_SPEED_STD;
  84. /* fall through */
  85. case 0x0818:
  86. case 0x0819:
  87. c->bus_num = pdev->device - 0x817 + 3;
  88. return 0;
  89. case 0x082C:
  90. case 0x082D:
  91. case 0x082E:
  92. c->bus_num = pdev->device - 0x82C + 0;
  93. return 0;
  94. }
  95. return -ENODEV;
  96. }
  97. static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
  98. {
  99. /*
  100. * On Intel Merrifield the user visible i2c busses are enumerated
  101. * [1..7]. So, we add 1 to shift the default range. Besides that the
  102. * first PCI slot provides 4 functions, that's why we have to add 0 to
  103. * the first slot and 4 to the next one.
  104. */
  105. switch (PCI_SLOT(pdev->devfn)) {
  106. case 8:
  107. c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
  108. return 0;
  109. case 9:
  110. c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
  111. return 0;
  112. }
  113. return -ENODEV;
  114. }
  115. static struct dw_pci_controller dw_pci_controllers[] = {
  116. [medfield] = {
  117. .bus_num = -1,
  118. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  119. .tx_fifo_depth = 32,
  120. .rx_fifo_depth = 32,
  121. .functionality = I2C_FUNC_10BIT_ADDR,
  122. .clk_khz = 25000,
  123. .setup = mfld_setup,
  124. },
  125. [merrifield] = {
  126. .bus_num = -1,
  127. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  128. .tx_fifo_depth = 64,
  129. .rx_fifo_depth = 64,
  130. .functionality = I2C_FUNC_10BIT_ADDR,
  131. .scl_sda_cfg = &mrfld_config,
  132. .setup = mrfld_setup,
  133. },
  134. [baytrail] = {
  135. .bus_num = -1,
  136. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  137. .tx_fifo_depth = 32,
  138. .rx_fifo_depth = 32,
  139. .functionality = I2C_FUNC_10BIT_ADDR,
  140. .scl_sda_cfg = &byt_config,
  141. },
  142. [haswell] = {
  143. .bus_num = -1,
  144. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  145. .tx_fifo_depth = 32,
  146. .rx_fifo_depth = 32,
  147. .functionality = I2C_FUNC_10BIT_ADDR,
  148. .scl_sda_cfg = &hsw_config,
  149. },
  150. [cherrytrail] = {
  151. .bus_num = -1,
  152. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  153. .tx_fifo_depth = 32,
  154. .rx_fifo_depth = 32,
  155. .functionality = I2C_FUNC_10BIT_ADDR,
  156. .flags = MODEL_CHERRYTRAIL,
  157. .scl_sda_cfg = &byt_config,
  158. },
  159. };
  160. #ifdef CONFIG_PM
  161. static int i2c_dw_pci_suspend(struct device *dev)
  162. {
  163. struct pci_dev *pdev = to_pci_dev(dev);
  164. struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);
  165. i_dev->disable(i_dev);
  166. return 0;
  167. }
  168. static int i2c_dw_pci_resume(struct device *dev)
  169. {
  170. struct pci_dev *pdev = to_pci_dev(dev);
  171. struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);
  172. return i_dev->init(i_dev);
  173. }
  174. #endif
  175. static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
  176. i2c_dw_pci_resume, NULL);
  177. static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
  178. {
  179. return dev->controller->clk_khz;
  180. }
  181. static int i2c_dw_pci_probe(struct pci_dev *pdev,
  182. const struct pci_device_id *id)
  183. {
  184. struct dw_i2c_dev *dev;
  185. struct i2c_adapter *adap;
  186. int r;
  187. struct dw_pci_controller *controller;
  188. struct dw_scl_sda_cfg *cfg;
  189. if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
  190. dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
  191. id->driver_data);
  192. return -EINVAL;
  193. }
  194. controller = &dw_pci_controllers[id->driver_data];
  195. r = pcim_enable_device(pdev);
  196. if (r) {
  197. dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
  198. r);
  199. return r;
  200. }
  201. r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
  202. if (r) {
  203. dev_err(&pdev->dev, "I/O memory remapping failed\n");
  204. return r;
  205. }
  206. dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
  207. if (!dev)
  208. return -ENOMEM;
  209. dev->clk = NULL;
  210. dev->controller = controller;
  211. dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
  212. dev->base = pcim_iomap_table(pdev)[0];
  213. dev->dev = &pdev->dev;
  214. dev->irq = pdev->irq;
  215. dev->flags |= controller->flags;
  216. if (controller->setup) {
  217. r = controller->setup(pdev, controller);
  218. if (r)
  219. return r;
  220. }
  221. dev->functionality = controller->functionality |
  222. DW_IC_DEFAULT_FUNCTIONALITY;
  223. dev->master_cfg = controller->bus_cfg;
  224. if (controller->scl_sda_cfg) {
  225. cfg = controller->scl_sda_cfg;
  226. dev->ss_hcnt = cfg->ss_hcnt;
  227. dev->fs_hcnt = cfg->fs_hcnt;
  228. dev->ss_lcnt = cfg->ss_lcnt;
  229. dev->fs_lcnt = cfg->fs_lcnt;
  230. dev->sda_hold_time = cfg->sda_hold;
  231. }
  232. pci_set_drvdata(pdev, dev);
  233. dev->tx_fifo_depth = controller->tx_fifo_depth;
  234. dev->rx_fifo_depth = controller->rx_fifo_depth;
  235. adap = &dev->adapter;
  236. adap->owner = THIS_MODULE;
  237. adap->class = 0;
  238. ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
  239. adap->nr = controller->bus_num;
  240. r = i2c_dw_probe(dev);
  241. if (r)
  242. return r;
  243. pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
  244. pm_runtime_use_autosuspend(&pdev->dev);
  245. pm_runtime_put_autosuspend(&pdev->dev);
  246. pm_runtime_allow(&pdev->dev);
  247. return 0;
  248. }
  249. static void i2c_dw_pci_remove(struct pci_dev *pdev)
  250. {
  251. struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
  252. dev->disable(dev);
  253. pm_runtime_forbid(&pdev->dev);
  254. pm_runtime_get_noresume(&pdev->dev);
  255. i2c_del_adapter(&dev->adapter);
  256. }
  257. /* work with hotplug and coldplug */
  258. MODULE_ALIAS("i2c_designware-pci");
  259. static const struct pci_device_id i2_designware_pci_ids[] = {
  260. /* Medfield */
  261. { PCI_VDEVICE(INTEL, 0x0817), medfield },
  262. { PCI_VDEVICE(INTEL, 0x0818), medfield },
  263. { PCI_VDEVICE(INTEL, 0x0819), medfield },
  264. { PCI_VDEVICE(INTEL, 0x082C), medfield },
  265. { PCI_VDEVICE(INTEL, 0x082D), medfield },
  266. { PCI_VDEVICE(INTEL, 0x082E), medfield },
  267. /* Merrifield */
  268. { PCI_VDEVICE(INTEL, 0x1195), merrifield },
  269. { PCI_VDEVICE(INTEL, 0x1196), merrifield },
  270. /* Baytrail */
  271. { PCI_VDEVICE(INTEL, 0x0F41), baytrail },
  272. { PCI_VDEVICE(INTEL, 0x0F42), baytrail },
  273. { PCI_VDEVICE(INTEL, 0x0F43), baytrail },
  274. { PCI_VDEVICE(INTEL, 0x0F44), baytrail },
  275. { PCI_VDEVICE(INTEL, 0x0F45), baytrail },
  276. { PCI_VDEVICE(INTEL, 0x0F46), baytrail },
  277. { PCI_VDEVICE(INTEL, 0x0F47), baytrail },
  278. /* Haswell */
  279. { PCI_VDEVICE(INTEL, 0x9c61), haswell },
  280. { PCI_VDEVICE(INTEL, 0x9c62), haswell },
  281. /* Braswell / Cherrytrail */
  282. { PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
  283. { PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
  284. { PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
  285. { PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
  286. { PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
  287. { PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
  288. { PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
  289. { 0,}
  290. };
  291. MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
  292. static struct pci_driver dw_i2c_driver = {
  293. .name = DRIVER_NAME,
  294. .id_table = i2_designware_pci_ids,
  295. .probe = i2c_dw_pci_probe,
  296. .remove = i2c_dw_pci_remove,
  297. .driver = {
  298. .pm = &i2c_dw_pm_ops,
  299. },
  300. };
  301. module_pci_driver(dw_i2c_driver);
  302. MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
  303. MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
  304. MODULE_LICENSE("GPL");