pci-versatile.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2004 Koninklijke Philips Electronics NV
  4. *
  5. * Conversion to platform driver and DT:
  6. * Copyright 2014 Linaro Ltd.
  7. *
  8. * 14/04/2005 Initial version, colin.king@philips.com
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_pci.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/pci.h>
  16. #include <linux/platform_device.h>
  17. #include "../pci.h"
  18. static void __iomem *versatile_pci_base;
  19. static void __iomem *versatile_cfg_base[2];
  20. #define PCI_IMAP(m) (versatile_pci_base + ((m) * 4))
  21. #define PCI_SMAP(m) (versatile_pci_base + 0x14 + ((m) * 4))
  22. #define PCI_SELFID (versatile_pci_base + 0xc)
  23. #define VP_PCI_DEVICE_ID 0x030010ee
  24. #define VP_PCI_CLASS_ID 0x0b400000
  25. static u32 pci_slot_ignore;
  26. static int __init versatile_pci_slot_ignore(char *str)
  27. {
  28. int retval;
  29. int slot;
  30. while ((retval = get_option(&str, &slot))) {
  31. if ((slot < 0) || (slot > 31))
  32. pr_err("Illegal slot value: %d\n", slot);
  33. else
  34. pci_slot_ignore |= (1 << slot);
  35. }
  36. return 1;
  37. }
  38. __setup("pci_slot_ignore=", versatile_pci_slot_ignore);
  39. static void __iomem *versatile_map_bus(struct pci_bus *bus,
  40. unsigned int devfn, int offset)
  41. {
  42. unsigned int busnr = bus->number;
  43. if (pci_slot_ignore & (1 << PCI_SLOT(devfn)))
  44. return NULL;
  45. return versatile_cfg_base[1] + ((busnr << 16) | (devfn << 8) | offset);
  46. }
  47. static struct pci_ops pci_versatile_ops = {
  48. .map_bus = versatile_map_bus,
  49. .read = pci_generic_config_read32,
  50. .write = pci_generic_config_write,
  51. };
  52. static int versatile_pci_parse_request_of_pci_ranges(struct device *dev,
  53. struct list_head *res)
  54. {
  55. int err, mem = 1, res_valid = 0;
  56. resource_size_t iobase;
  57. struct resource_entry *win, *tmp;
  58. err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, res, &iobase);
  59. if (err)
  60. return err;
  61. err = devm_request_pci_bus_resources(dev, res);
  62. if (err)
  63. goto out_release_res;
  64. resource_list_for_each_entry_safe(win, tmp, res) {
  65. struct resource *res = win->res;
  66. switch (resource_type(res)) {
  67. case IORESOURCE_IO:
  68. err = devm_pci_remap_iospace(dev, res, iobase);
  69. if (err) {
  70. dev_warn(dev, "error %d: failed to map resource %pR\n",
  71. err, res);
  72. resource_list_destroy_entry(win);
  73. }
  74. break;
  75. case IORESOURCE_MEM:
  76. res_valid |= !(res->flags & IORESOURCE_PREFETCH);
  77. writel(res->start >> 28, PCI_IMAP(mem));
  78. writel(PHYS_OFFSET >> 28, PCI_SMAP(mem));
  79. mem++;
  80. break;
  81. }
  82. }
  83. if (res_valid)
  84. return 0;
  85. dev_err(dev, "non-prefetchable memory resource required\n");
  86. err = -EINVAL;
  87. out_release_res:
  88. pci_free_resource_list(res);
  89. return err;
  90. }
  91. static int versatile_pci_probe(struct platform_device *pdev)
  92. {
  93. struct device *dev = &pdev->dev;
  94. struct resource *res;
  95. int ret, i, myslot = -1;
  96. u32 val;
  97. void __iomem *local_pci_cfg_base;
  98. struct pci_bus *bus, *child;
  99. struct pci_host_bridge *bridge;
  100. LIST_HEAD(pci_res);
  101. bridge = devm_pci_alloc_host_bridge(dev, 0);
  102. if (!bridge)
  103. return -ENOMEM;
  104. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  105. versatile_pci_base = devm_ioremap_resource(dev, res);
  106. if (IS_ERR(versatile_pci_base))
  107. return PTR_ERR(versatile_pci_base);
  108. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  109. versatile_cfg_base[0] = devm_ioremap_resource(dev, res);
  110. if (IS_ERR(versatile_cfg_base[0]))
  111. return PTR_ERR(versatile_cfg_base[0]);
  112. res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  113. versatile_cfg_base[1] = devm_pci_remap_cfg_resource(dev, res);
  114. if (IS_ERR(versatile_cfg_base[1]))
  115. return PTR_ERR(versatile_cfg_base[1]);
  116. ret = versatile_pci_parse_request_of_pci_ranges(dev, &pci_res);
  117. if (ret)
  118. return ret;
  119. /*
  120. * We need to discover the PCI core first to configure itself
  121. * before the main PCI probing is performed
  122. */
  123. for (i = 0; i < 32; i++) {
  124. if ((readl(versatile_cfg_base[0] + (i << 11) + PCI_VENDOR_ID) == VP_PCI_DEVICE_ID) &&
  125. (readl(versatile_cfg_base[0] + (i << 11) + PCI_CLASS_REVISION) == VP_PCI_CLASS_ID)) {
  126. myslot = i;
  127. break;
  128. }
  129. }
  130. if (myslot == -1) {
  131. dev_err(dev, "Cannot find PCI core!\n");
  132. return -EIO;
  133. }
  134. /*
  135. * Do not to map Versatile FPGA PCI device into memory space
  136. */
  137. pci_slot_ignore |= (1 << myslot);
  138. dev_info(dev, "PCI core found (slot %d)\n", myslot);
  139. writel(myslot, PCI_SELFID);
  140. local_pci_cfg_base = versatile_cfg_base[1] + (myslot << 11);
  141. val = readl(local_pci_cfg_base + PCI_COMMAND);
  142. val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
  143. writel(val, local_pci_cfg_base + PCI_COMMAND);
  144. /*
  145. * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
  146. */
  147. writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
  148. writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
  149. writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
  150. /*
  151. * For many years the kernel and QEMU were symbiotically buggy
  152. * in that they both assumed the same broken IRQ mapping.
  153. * QEMU therefore attempts to auto-detect old broken kernels
  154. * so that they still work on newer QEMU as they did on old
  155. * QEMU. Since we now use the correct (ie matching-hardware)
  156. * IRQ mapping we write a definitely different value to a
  157. * PCI_INTERRUPT_LINE register to tell QEMU that we expect
  158. * real hardware behaviour and it need not be backwards
  159. * compatible for us. This write is harmless on real hardware.
  160. */
  161. writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);
  162. pci_add_flags(PCI_ENABLE_PROC_DOMAINS);
  163. pci_add_flags(PCI_REASSIGN_ALL_BUS);
  164. list_splice_init(&pci_res, &bridge->windows);
  165. bridge->dev.parent = dev;
  166. bridge->sysdata = NULL;
  167. bridge->busnr = 0;
  168. bridge->ops = &pci_versatile_ops;
  169. bridge->map_irq = of_irq_parse_and_map_pci;
  170. bridge->swizzle_irq = pci_common_swizzle;
  171. ret = pci_scan_root_bus_bridge(bridge);
  172. if (ret < 0)
  173. return ret;
  174. bus = bridge->bus;
  175. pci_assign_unassigned_bus_resources(bus);
  176. list_for_each_entry(child, &bus->children, node)
  177. pcie_bus_configure_settings(child);
  178. pci_bus_add_devices(bus);
  179. return 0;
  180. }
  181. static const struct of_device_id versatile_pci_of_match[] = {
  182. { .compatible = "arm,versatile-pci", },
  183. { },
  184. };
  185. MODULE_DEVICE_TABLE(of, versatile_pci_of_match);
  186. static struct platform_driver versatile_pci_driver = {
  187. .driver = {
  188. .name = "versatile-pci",
  189. .of_match_table = versatile_pci_of_match,
  190. .suppress_bind_attrs = true,
  191. },
  192. .probe = versatile_pci_probe,
  193. };
  194. module_platform_driver(versatile_pci_driver);
  195. MODULE_DESCRIPTION("Versatile PCI driver");
  196. MODULE_LICENSE("GPL v2");