pinctrl-sun50i-h6-r.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Allwinner H6 R_PIO pin controller driver
  4. *
  5. * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
  6. *
  7. * Based on pinctrl-sun6i-a31-r.c, which is:
  8. * Copyright (C) 2014 Boris Brezillon
  9. * Boris Brezillon <boris.brezillon@free-electrons.com>
  10. * Copyright (C) 2014 Maxime Ripard
  11. * Maxime Ripard <maxime.ripard@free-electrons.com>
  12. */
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/pinctrl/pinctrl.h>
  18. #include <linux/reset.h>
  19. #include "pinctrl-sunxi.h"
  20. static const struct sunxi_desc_pin sun50i_h6_r_pins[] = {
  21. SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
  22. SUNXI_FUNCTION(0x0, "gpio_in"),
  23. SUNXI_FUNCTION(0x1, "gpio_out"),
  24. SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
  25. SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
  26. SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
  27. SUNXI_FUNCTION(0x0, "gpio_in"),
  28. SUNXI_FUNCTION(0x1, "gpio_out"),
  29. SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
  30. SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
  31. SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
  32. SUNXI_FUNCTION(0x0, "gpio_in"),
  33. SUNXI_FUNCTION(0x1, "gpio_out"),
  34. SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
  35. SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
  36. SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
  37. SUNXI_FUNCTION(0x0, "gpio_in"),
  38. SUNXI_FUNCTION(0x1, "gpio_out"),
  39. SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
  40. SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
  41. SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
  42. SUNXI_FUNCTION(0x0, "gpio_in"),
  43. SUNXI_FUNCTION(0x1, "gpio_out"),
  44. SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
  45. SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
  46. SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
  47. SUNXI_FUNCTION(0x0, "gpio_in"),
  48. SUNXI_FUNCTION(0x1, "gpio_out"),
  49. SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
  50. SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
  51. SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
  52. SUNXI_FUNCTION(0x0, "gpio_in"),
  53. SUNXI_FUNCTION(0x1, "gpio_out"),
  54. SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
  55. SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
  56. SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
  57. SUNXI_FUNCTION(0x0, "gpio_in"),
  58. SUNXI_FUNCTION(0x1, "gpio_out"),
  59. SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
  60. SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
  61. SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
  62. SUNXI_FUNCTION(0x0, "gpio_in"),
  63. SUNXI_FUNCTION(0x1, "gpio_out"),
  64. SUNXI_FUNCTION(0x2, "s_pwm"),
  65. SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
  66. SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
  67. SUNXI_FUNCTION(0x0, "gpio_in"),
  68. SUNXI_FUNCTION(0x1, "gpio_out"),
  69. SUNXI_FUNCTION(0x2, "s_cir_rx"),
  70. SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
  71. SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
  72. SUNXI_FUNCTION(0x0, "gpio_in"),
  73. SUNXI_FUNCTION(0x1, "gpio_out"),
  74. SUNXI_FUNCTION(0x2, "s_w1"),
  75. SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
  76. /* Hole */
  77. SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
  78. SUNXI_FUNCTION(0x0, "gpio_in"),
  79. SUNXI_FUNCTION(0x1, "gpio_out"),
  80. SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PM_EINT0 */
  81. SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
  82. SUNXI_FUNCTION(0x0, "gpio_in"),
  83. SUNXI_FUNCTION(0x1, "gpio_out"),
  84. SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PM_EINT1 */
  85. SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
  86. SUNXI_FUNCTION(0x0, "gpio_in"),
  87. SUNXI_FUNCTION(0x1, "gpio_out"),
  88. SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2), /* PM_EINT2 */
  89. SUNXI_FUNCTION(0x3, "1wire")),
  90. SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
  91. SUNXI_FUNCTION(0x0, "gpio_in"),
  92. SUNXI_FUNCTION(0x1, "gpio_out"),
  93. SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PM_EINT3 */
  94. SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
  95. SUNXI_FUNCTION(0x0, "gpio_in"),
  96. SUNXI_FUNCTION(0x1, "gpio_out"),
  97. SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PM_EINT4 */
  98. };
  99. static const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_data = {
  100. .pins = sun50i_h6_r_pins,
  101. .npins = ARRAY_SIZE(sun50i_h6_r_pins),
  102. .pin_base = PL_BASE,
  103. .irq_banks = 2,
  104. };
  105. static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev)
  106. {
  107. return sunxi_pinctrl_init(pdev,
  108. &sun50i_h6_r_pinctrl_data);
  109. }
  110. static const struct of_device_id sun50i_h6_r_pinctrl_match[] = {
  111. { .compatible = "allwinner,sun50i-h6-r-pinctrl", },
  112. {}
  113. };
  114. static struct platform_driver sun50i_h6_r_pinctrl_driver = {
  115. .probe = sun50i_h6_r_pinctrl_probe,
  116. .driver = {
  117. .name = "sun50i-h6-r-pinctrl",
  118. .of_match_table = sun50i_h6_r_pinctrl_match,
  119. },
  120. };
  121. builtin_platform_driver(sun50i_h6_r_pinctrl_driver);