s5m8767.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright (c) 2011 Samsung Electronics Co., Ltd
  4. // http://www.samsung.com
  5. #include <linux/err.h>
  6. #include <linux/of_gpio.h>
  7. #include <linux/gpio/consumer.h>
  8. #include <linux/module.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/regulator/driver.h>
  11. #include <linux/regulator/machine.h>
  12. #include <linux/mfd/samsung/core.h>
  13. #include <linux/mfd/samsung/s5m8767.h>
  14. #include <linux/regulator/of_regulator.h>
  15. #include <linux/regmap.h>
  16. #define S5M8767_OPMODE_NORMAL_MODE 0x1
  17. struct s5m8767_info {
  18. struct device *dev;
  19. struct sec_pmic_dev *iodev;
  20. int num_regulators;
  21. struct sec_opmode_data *opmode;
  22. int ramp_delay;
  23. bool buck2_ramp;
  24. bool buck3_ramp;
  25. bool buck4_ramp;
  26. bool buck2_gpiodvs;
  27. bool buck3_gpiodvs;
  28. bool buck4_gpiodvs;
  29. u8 buck2_vol[8];
  30. u8 buck3_vol[8];
  31. u8 buck4_vol[8];
  32. int buck_gpios[3];
  33. int buck_ds[3];
  34. int buck_gpioindex;
  35. };
  36. struct sec_voltage_desc {
  37. int max;
  38. int min;
  39. int step;
  40. };
  41. static const struct sec_voltage_desc buck_voltage_val1 = {
  42. .max = 2225000,
  43. .min = 650000,
  44. .step = 6250,
  45. };
  46. static const struct sec_voltage_desc buck_voltage_val2 = {
  47. .max = 1600000,
  48. .min = 600000,
  49. .step = 6250,
  50. };
  51. static const struct sec_voltage_desc buck_voltage_val3 = {
  52. .max = 3000000,
  53. .min = 750000,
  54. .step = 12500,
  55. };
  56. static const struct sec_voltage_desc ldo_voltage_val1 = {
  57. .max = 3950000,
  58. .min = 800000,
  59. .step = 50000,
  60. };
  61. static const struct sec_voltage_desc ldo_voltage_val2 = {
  62. .max = 2375000,
  63. .min = 800000,
  64. .step = 25000,
  65. };
  66. static const struct sec_voltage_desc *reg_voltage_map[] = {
  67. [S5M8767_LDO1] = &ldo_voltage_val2,
  68. [S5M8767_LDO2] = &ldo_voltage_val2,
  69. [S5M8767_LDO3] = &ldo_voltage_val1,
  70. [S5M8767_LDO4] = &ldo_voltage_val1,
  71. [S5M8767_LDO5] = &ldo_voltage_val1,
  72. [S5M8767_LDO6] = &ldo_voltage_val2,
  73. [S5M8767_LDO7] = &ldo_voltage_val2,
  74. [S5M8767_LDO8] = &ldo_voltage_val2,
  75. [S5M8767_LDO9] = &ldo_voltage_val1,
  76. [S5M8767_LDO10] = &ldo_voltage_val1,
  77. [S5M8767_LDO11] = &ldo_voltage_val1,
  78. [S5M8767_LDO12] = &ldo_voltage_val1,
  79. [S5M8767_LDO13] = &ldo_voltage_val1,
  80. [S5M8767_LDO14] = &ldo_voltage_val1,
  81. [S5M8767_LDO15] = &ldo_voltage_val2,
  82. [S5M8767_LDO16] = &ldo_voltage_val1,
  83. [S5M8767_LDO17] = &ldo_voltage_val1,
  84. [S5M8767_LDO18] = &ldo_voltage_val1,
  85. [S5M8767_LDO19] = &ldo_voltage_val1,
  86. [S5M8767_LDO20] = &ldo_voltage_val1,
  87. [S5M8767_LDO21] = &ldo_voltage_val1,
  88. [S5M8767_LDO22] = &ldo_voltage_val1,
  89. [S5M8767_LDO23] = &ldo_voltage_val1,
  90. [S5M8767_LDO24] = &ldo_voltage_val1,
  91. [S5M8767_LDO25] = &ldo_voltage_val1,
  92. [S5M8767_LDO26] = &ldo_voltage_val1,
  93. [S5M8767_LDO27] = &ldo_voltage_val1,
  94. [S5M8767_LDO28] = &ldo_voltage_val1,
  95. [S5M8767_BUCK1] = &buck_voltage_val1,
  96. [S5M8767_BUCK2] = &buck_voltage_val2,
  97. [S5M8767_BUCK3] = &buck_voltage_val2,
  98. [S5M8767_BUCK4] = &buck_voltage_val2,
  99. [S5M8767_BUCK5] = &buck_voltage_val1,
  100. [S5M8767_BUCK6] = &buck_voltage_val1,
  101. [S5M8767_BUCK7] = &buck_voltage_val3,
  102. [S5M8767_BUCK8] = &buck_voltage_val3,
  103. [S5M8767_BUCK9] = &buck_voltage_val3,
  104. };
  105. static unsigned int s5m8767_opmode_reg[][4] = {
  106. /* {OFF, ON, LOWPOWER, SUSPEND} */
  107. /* LDO1 ... LDO28 */
  108. {0x0, 0x3, 0x2, 0x1}, /* LDO1 */
  109. {0x0, 0x3, 0x2, 0x1},
  110. {0x0, 0x3, 0x2, 0x1},
  111. {0x0, 0x0, 0x0, 0x0},
  112. {0x0, 0x3, 0x2, 0x1}, /* LDO5 */
  113. {0x0, 0x3, 0x2, 0x1},
  114. {0x0, 0x3, 0x2, 0x1},
  115. {0x0, 0x3, 0x2, 0x1},
  116. {0x0, 0x3, 0x2, 0x1},
  117. {0x0, 0x3, 0x2, 0x1}, /* LDO10 */
  118. {0x0, 0x3, 0x2, 0x1},
  119. {0x0, 0x3, 0x2, 0x1},
  120. {0x0, 0x3, 0x2, 0x1},
  121. {0x0, 0x3, 0x2, 0x1},
  122. {0x0, 0x3, 0x2, 0x1}, /* LDO15 */
  123. {0x0, 0x3, 0x2, 0x1},
  124. {0x0, 0x3, 0x2, 0x1},
  125. {0x0, 0x0, 0x0, 0x0},
  126. {0x0, 0x3, 0x2, 0x1},
  127. {0x0, 0x3, 0x2, 0x1}, /* LDO20 */
  128. {0x0, 0x3, 0x2, 0x1},
  129. {0x0, 0x3, 0x2, 0x1},
  130. {0x0, 0x0, 0x0, 0x0},
  131. {0x0, 0x3, 0x2, 0x1},
  132. {0x0, 0x3, 0x2, 0x1}, /* LDO25 */
  133. {0x0, 0x3, 0x2, 0x1},
  134. {0x0, 0x3, 0x2, 0x1},
  135. {0x0, 0x3, 0x2, 0x1}, /* LDO28 */
  136. /* BUCK1 ... BUCK9 */
  137. {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */
  138. {0x0, 0x3, 0x1, 0x1},
  139. {0x0, 0x3, 0x1, 0x1},
  140. {0x0, 0x3, 0x1, 0x1},
  141. {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */
  142. {0x0, 0x3, 0x1, 0x1},
  143. {0x0, 0x3, 0x1, 0x1},
  144. {0x0, 0x3, 0x1, 0x1},
  145. {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */
  146. };
  147. static int s5m8767_get_register(struct s5m8767_info *s5m8767, int reg_id,
  148. int *reg, int *enable_ctrl)
  149. {
  150. int i;
  151. unsigned int mode;
  152. switch (reg_id) {
  153. case S5M8767_LDO1 ... S5M8767_LDO2:
  154. *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
  155. break;
  156. case S5M8767_LDO3 ... S5M8767_LDO28:
  157. *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
  158. break;
  159. case S5M8767_BUCK1:
  160. *reg = S5M8767_REG_BUCK1CTRL1;
  161. break;
  162. case S5M8767_BUCK2 ... S5M8767_BUCK4:
  163. *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9;
  164. break;
  165. case S5M8767_BUCK5:
  166. *reg = S5M8767_REG_BUCK5CTRL1;
  167. break;
  168. case S5M8767_BUCK6 ... S5M8767_BUCK9:
  169. *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2;
  170. break;
  171. default:
  172. return -EINVAL;
  173. }
  174. for (i = 0; i < s5m8767->num_regulators; i++) {
  175. if (s5m8767->opmode[i].id == reg_id) {
  176. mode = s5m8767->opmode[i].mode;
  177. break;
  178. }
  179. }
  180. if (i >= s5m8767->num_regulators)
  181. return -EINVAL;
  182. *enable_ctrl = s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT;
  183. return 0;
  184. }
  185. static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767)
  186. {
  187. int reg;
  188. switch (reg_id) {
  189. case S5M8767_LDO1 ... S5M8767_LDO2:
  190. reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
  191. break;
  192. case S5M8767_LDO3 ... S5M8767_LDO28:
  193. reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
  194. break;
  195. case S5M8767_BUCK1:
  196. reg = S5M8767_REG_BUCK1CTRL2;
  197. break;
  198. case S5M8767_BUCK2:
  199. reg = S5M8767_REG_BUCK2DVS1;
  200. if (s5m8767->buck2_gpiodvs)
  201. reg += s5m8767->buck_gpioindex;
  202. break;
  203. case S5M8767_BUCK3:
  204. reg = S5M8767_REG_BUCK3DVS1;
  205. if (s5m8767->buck3_gpiodvs)
  206. reg += s5m8767->buck_gpioindex;
  207. break;
  208. case S5M8767_BUCK4:
  209. reg = S5M8767_REG_BUCK4DVS1;
  210. if (s5m8767->buck4_gpiodvs)
  211. reg += s5m8767->buck_gpioindex;
  212. break;
  213. case S5M8767_BUCK5:
  214. reg = S5M8767_REG_BUCK5CTRL2;
  215. break;
  216. case S5M8767_BUCK6 ... S5M8767_BUCK9:
  217. reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2;
  218. break;
  219. default:
  220. return -EINVAL;
  221. }
  222. return reg;
  223. }
  224. static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc,
  225. int min_vol)
  226. {
  227. int selector = 0;
  228. if (desc == NULL)
  229. return -EINVAL;
  230. if (min_vol > desc->max)
  231. return -EINVAL;
  232. if (min_vol < desc->min)
  233. min_vol = desc->min;
  234. selector = DIV_ROUND_UP(min_vol - desc->min, desc->step);
  235. if (desc->min + desc->step * selector > desc->max)
  236. return -EINVAL;
  237. return selector;
  238. }
  239. static inline int s5m8767_set_high(struct s5m8767_info *s5m8767)
  240. {
  241. int temp_index = s5m8767->buck_gpioindex;
  242. gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
  243. gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
  244. gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
  245. return 0;
  246. }
  247. static inline int s5m8767_set_low(struct s5m8767_info *s5m8767)
  248. {
  249. int temp_index = s5m8767->buck_gpioindex;
  250. gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
  251. gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
  252. gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
  253. return 0;
  254. }
  255. static int s5m8767_set_voltage_sel(struct regulator_dev *rdev,
  256. unsigned selector)
  257. {
  258. struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
  259. int reg_id = rdev_get_id(rdev);
  260. int old_index, index = 0;
  261. u8 *buck234_vol = NULL;
  262. switch (reg_id) {
  263. case S5M8767_LDO1 ... S5M8767_LDO28:
  264. break;
  265. case S5M8767_BUCK1 ... S5M8767_BUCK6:
  266. if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs)
  267. buck234_vol = &s5m8767->buck2_vol[0];
  268. else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs)
  269. buck234_vol = &s5m8767->buck3_vol[0];
  270. else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs)
  271. buck234_vol = &s5m8767->buck4_vol[0];
  272. break;
  273. case S5M8767_BUCK7 ... S5M8767_BUCK8:
  274. return -EINVAL;
  275. case S5M8767_BUCK9:
  276. break;
  277. default:
  278. return -EINVAL;
  279. }
  280. /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */
  281. if (buck234_vol) {
  282. while (*buck234_vol != selector) {
  283. buck234_vol++;
  284. index++;
  285. }
  286. old_index = s5m8767->buck_gpioindex;
  287. s5m8767->buck_gpioindex = index;
  288. if (index > old_index)
  289. return s5m8767_set_high(s5m8767);
  290. else
  291. return s5m8767_set_low(s5m8767);
  292. } else {
  293. return regulator_set_voltage_sel_regmap(rdev, selector);
  294. }
  295. }
  296. static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev,
  297. unsigned int old_sel,
  298. unsigned int new_sel)
  299. {
  300. struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
  301. const struct sec_voltage_desc *desc;
  302. int reg_id = rdev_get_id(rdev);
  303. desc = reg_voltage_map[reg_id];
  304. if ((old_sel < new_sel) && s5m8767->ramp_delay)
  305. return DIV_ROUND_UP(desc->step * (new_sel - old_sel),
  306. s5m8767->ramp_delay * 1000);
  307. return 0;
  308. }
  309. static const struct regulator_ops s5m8767_ops = {
  310. .list_voltage = regulator_list_voltage_linear,
  311. .is_enabled = regulator_is_enabled_regmap,
  312. .enable = regulator_enable_regmap,
  313. .disable = regulator_disable_regmap,
  314. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  315. .set_voltage_sel = s5m8767_set_voltage_sel,
  316. .set_voltage_time_sel = s5m8767_set_voltage_time_sel,
  317. };
  318. static const struct regulator_ops s5m8767_buck78_ops = {
  319. .list_voltage = regulator_list_voltage_linear,
  320. .is_enabled = regulator_is_enabled_regmap,
  321. .enable = regulator_enable_regmap,
  322. .disable = regulator_disable_regmap,
  323. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  324. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  325. };
  326. #define s5m8767_regulator_desc(_name) { \
  327. .name = #_name, \
  328. .id = S5M8767_##_name, \
  329. .ops = &s5m8767_ops, \
  330. .type = REGULATOR_VOLTAGE, \
  331. .owner = THIS_MODULE, \
  332. }
  333. #define s5m8767_regulator_buck78_desc(_name) { \
  334. .name = #_name, \
  335. .id = S5M8767_##_name, \
  336. .ops = &s5m8767_buck78_ops, \
  337. .type = REGULATOR_VOLTAGE, \
  338. .owner = THIS_MODULE, \
  339. }
  340. static struct regulator_desc regulators[] = {
  341. s5m8767_regulator_desc(LDO1),
  342. s5m8767_regulator_desc(LDO2),
  343. s5m8767_regulator_desc(LDO3),
  344. s5m8767_regulator_desc(LDO4),
  345. s5m8767_regulator_desc(LDO5),
  346. s5m8767_regulator_desc(LDO6),
  347. s5m8767_regulator_desc(LDO7),
  348. s5m8767_regulator_desc(LDO8),
  349. s5m8767_regulator_desc(LDO9),
  350. s5m8767_regulator_desc(LDO10),
  351. s5m8767_regulator_desc(LDO11),
  352. s5m8767_regulator_desc(LDO12),
  353. s5m8767_regulator_desc(LDO13),
  354. s5m8767_regulator_desc(LDO14),
  355. s5m8767_regulator_desc(LDO15),
  356. s5m8767_regulator_desc(LDO16),
  357. s5m8767_regulator_desc(LDO17),
  358. s5m8767_regulator_desc(LDO18),
  359. s5m8767_regulator_desc(LDO19),
  360. s5m8767_regulator_desc(LDO20),
  361. s5m8767_regulator_desc(LDO21),
  362. s5m8767_regulator_desc(LDO22),
  363. s5m8767_regulator_desc(LDO23),
  364. s5m8767_regulator_desc(LDO24),
  365. s5m8767_regulator_desc(LDO25),
  366. s5m8767_regulator_desc(LDO26),
  367. s5m8767_regulator_desc(LDO27),
  368. s5m8767_regulator_desc(LDO28),
  369. s5m8767_regulator_desc(BUCK1),
  370. s5m8767_regulator_desc(BUCK2),
  371. s5m8767_regulator_desc(BUCK3),
  372. s5m8767_regulator_desc(BUCK4),
  373. s5m8767_regulator_desc(BUCK5),
  374. s5m8767_regulator_desc(BUCK6),
  375. s5m8767_regulator_buck78_desc(BUCK7),
  376. s5m8767_regulator_buck78_desc(BUCK8),
  377. s5m8767_regulator_desc(BUCK9),
  378. };
  379. /*
  380. * Enable GPIO control over BUCK9 in regulator_config for that regulator.
  381. */
  382. static void s5m8767_regulator_config_ext_control(struct s5m8767_info *s5m8767,
  383. struct sec_regulator_data *rdata,
  384. struct regulator_config *config)
  385. {
  386. int i, mode = 0;
  387. if (rdata->id != S5M8767_BUCK9)
  388. return;
  389. /* Check if opmode for regulator matches S5M8767_ENCTRL_USE_GPIO */
  390. for (i = 0; i < s5m8767->num_regulators; i++) {
  391. const struct sec_opmode_data *opmode = &s5m8767->opmode[i];
  392. if (opmode->id == rdata->id) {
  393. mode = s5m8767_opmode_reg[rdata->id][opmode->mode];
  394. break;
  395. }
  396. }
  397. if (mode != S5M8767_ENCTRL_USE_GPIO) {
  398. dev_warn(s5m8767->dev,
  399. "ext-control for %s: mismatched op_mode (%x), ignoring\n",
  400. rdata->reg_node->name, mode);
  401. return;
  402. }
  403. if (!rdata->ext_control_gpiod) {
  404. dev_warn(s5m8767->dev,
  405. "ext-control for %s: GPIO not valid, ignoring\n",
  406. rdata->reg_node->name);
  407. return;
  408. }
  409. config->ena_gpiod = rdata->ext_control_gpiod;
  410. }
  411. /*
  412. * Turn on GPIO control over BUCK9.
  413. */
  414. static int s5m8767_enable_ext_control(struct s5m8767_info *s5m8767,
  415. struct regulator_dev *rdev)
  416. {
  417. int id = rdev_get_id(rdev);
  418. int ret, reg, enable_ctrl;
  419. if (id != S5M8767_BUCK9)
  420. return -EINVAL;
  421. ret = s5m8767_get_register(s5m8767, id, &reg, &enable_ctrl);
  422. if (ret)
  423. return ret;
  424. return regmap_update_bits(s5m8767->iodev->regmap_pmic,
  425. reg, S5M8767_ENCTRL_MASK,
  426. S5M8767_ENCTRL_USE_GPIO << S5M8767_ENCTRL_SHIFT);
  427. }
  428. #ifdef CONFIG_OF
  429. static int s5m8767_pmic_dt_parse_dvs_gpio(struct sec_pmic_dev *iodev,
  430. struct sec_platform_data *pdata,
  431. struct device_node *pmic_np)
  432. {
  433. int i, gpio;
  434. for (i = 0; i < 3; i++) {
  435. gpio = of_get_named_gpio(pmic_np,
  436. "s5m8767,pmic-buck-dvs-gpios", i);
  437. if (!gpio_is_valid(gpio)) {
  438. dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
  439. return -EINVAL;
  440. }
  441. pdata->buck_gpios[i] = gpio;
  442. }
  443. return 0;
  444. }
  445. static int s5m8767_pmic_dt_parse_ds_gpio(struct sec_pmic_dev *iodev,
  446. struct sec_platform_data *pdata,
  447. struct device_node *pmic_np)
  448. {
  449. int i, gpio;
  450. for (i = 0; i < 3; i++) {
  451. gpio = of_get_named_gpio(pmic_np,
  452. "s5m8767,pmic-buck-ds-gpios", i);
  453. if (!gpio_is_valid(gpio)) {
  454. dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
  455. return -EINVAL;
  456. }
  457. pdata->buck_ds[i] = gpio;
  458. }
  459. return 0;
  460. }
  461. static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
  462. struct sec_platform_data *pdata)
  463. {
  464. struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
  465. struct device_node *pmic_np, *regulators_np, *reg_np;
  466. struct sec_regulator_data *rdata;
  467. struct sec_opmode_data *rmode;
  468. unsigned int i, dvs_voltage_nr = 8, ret;
  469. pmic_np = iodev->dev->of_node;
  470. if (!pmic_np) {
  471. dev_err(iodev->dev, "could not find pmic sub-node\n");
  472. return -ENODEV;
  473. }
  474. regulators_np = of_get_child_by_name(pmic_np, "regulators");
  475. if (!regulators_np) {
  476. dev_err(iodev->dev, "could not find regulators sub-node\n");
  477. return -EINVAL;
  478. }
  479. /* count the number of regulators to be supported in pmic */
  480. pdata->num_regulators = of_get_child_count(regulators_np);
  481. rdata = devm_kcalloc(&pdev->dev,
  482. pdata->num_regulators, sizeof(*rdata),
  483. GFP_KERNEL);
  484. if (!rdata) {
  485. of_node_put(regulators_np);
  486. return -ENOMEM;
  487. }
  488. rmode = devm_kcalloc(&pdev->dev,
  489. pdata->num_regulators, sizeof(*rmode),
  490. GFP_KERNEL);
  491. if (!rmode) {
  492. of_node_put(regulators_np);
  493. return -ENOMEM;
  494. }
  495. pdata->regulators = rdata;
  496. pdata->opmode = rmode;
  497. for_each_child_of_node(regulators_np, reg_np) {
  498. for (i = 0; i < ARRAY_SIZE(regulators); i++)
  499. if (!of_node_cmp(reg_np->name, regulators[i].name))
  500. break;
  501. if (i == ARRAY_SIZE(regulators)) {
  502. dev_warn(iodev->dev,
  503. "don't know how to configure regulator %s\n",
  504. reg_np->name);
  505. continue;
  506. }
  507. rdata->ext_control_gpiod = devm_gpiod_get_from_of_node(&pdev->dev,
  508. reg_np,
  509. "s5m8767,pmic-ext-control-gpios",
  510. 0,
  511. GPIOD_OUT_HIGH,
  512. "s5m8767");
  513. if (IS_ERR(rdata->ext_control_gpiod))
  514. return PTR_ERR(rdata->ext_control_gpiod);
  515. rdata->id = i;
  516. rdata->initdata = of_get_regulator_init_data(
  517. &pdev->dev, reg_np,
  518. &regulators[i]);
  519. rdata->reg_node = reg_np;
  520. rdata++;
  521. rmode->id = i;
  522. if (of_property_read_u32(reg_np, "op_mode",
  523. &rmode->mode)) {
  524. dev_warn(iodev->dev,
  525. "no op_mode property property at %pOF\n",
  526. reg_np);
  527. rmode->mode = S5M8767_OPMODE_NORMAL_MODE;
  528. }
  529. rmode++;
  530. }
  531. of_node_put(regulators_np);
  532. if (of_get_property(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs", NULL)) {
  533. pdata->buck2_gpiodvs = true;
  534. if (of_property_read_u32_array(pmic_np,
  535. "s5m8767,pmic-buck2-dvs-voltage",
  536. pdata->buck2_voltage, dvs_voltage_nr)) {
  537. dev_err(iodev->dev, "buck2 voltages not specified\n");
  538. return -EINVAL;
  539. }
  540. }
  541. if (of_get_property(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs", NULL)) {
  542. pdata->buck3_gpiodvs = true;
  543. if (of_property_read_u32_array(pmic_np,
  544. "s5m8767,pmic-buck3-dvs-voltage",
  545. pdata->buck3_voltage, dvs_voltage_nr)) {
  546. dev_err(iodev->dev, "buck3 voltages not specified\n");
  547. return -EINVAL;
  548. }
  549. }
  550. if (of_get_property(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs", NULL)) {
  551. pdata->buck4_gpiodvs = true;
  552. if (of_property_read_u32_array(pmic_np,
  553. "s5m8767,pmic-buck4-dvs-voltage",
  554. pdata->buck4_voltage, dvs_voltage_nr)) {
  555. dev_err(iodev->dev, "buck4 voltages not specified\n");
  556. return -EINVAL;
  557. }
  558. }
  559. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
  560. pdata->buck4_gpiodvs) {
  561. ret = s5m8767_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np);
  562. if (ret)
  563. return -EINVAL;
  564. if (of_property_read_u32(pmic_np,
  565. "s5m8767,pmic-buck-default-dvs-idx",
  566. &pdata->buck_default_idx)) {
  567. pdata->buck_default_idx = 0;
  568. } else {
  569. if (pdata->buck_default_idx >= 8) {
  570. pdata->buck_default_idx = 0;
  571. dev_info(iodev->dev,
  572. "invalid value for default dvs index, use 0\n");
  573. }
  574. }
  575. }
  576. ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np);
  577. if (ret)
  578. return -EINVAL;
  579. if (of_get_property(pmic_np, "s5m8767,pmic-buck2-ramp-enable", NULL))
  580. pdata->buck2_ramp_enable = true;
  581. if (of_get_property(pmic_np, "s5m8767,pmic-buck3-ramp-enable", NULL))
  582. pdata->buck3_ramp_enable = true;
  583. if (of_get_property(pmic_np, "s5m8767,pmic-buck4-ramp-enable", NULL))
  584. pdata->buck4_ramp_enable = true;
  585. if (pdata->buck2_ramp_enable || pdata->buck3_ramp_enable
  586. || pdata->buck4_ramp_enable) {
  587. if (of_property_read_u32(pmic_np, "s5m8767,pmic-buck-ramp-delay",
  588. &pdata->buck_ramp_delay))
  589. pdata->buck_ramp_delay = 0;
  590. }
  591. return 0;
  592. }
  593. #else
  594. static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
  595. struct sec_platform_data *pdata)
  596. {
  597. return 0;
  598. }
  599. #endif /* CONFIG_OF */
  600. static int s5m8767_pmic_probe(struct platform_device *pdev)
  601. {
  602. struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
  603. struct sec_platform_data *pdata = iodev->pdata;
  604. struct regulator_config config = { };
  605. struct s5m8767_info *s5m8767;
  606. int i, ret, buck_init;
  607. if (!pdata) {
  608. dev_err(pdev->dev.parent, "Platform data not supplied\n");
  609. return -ENODEV;
  610. }
  611. if (iodev->dev->of_node) {
  612. ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata);
  613. if (ret)
  614. return ret;
  615. }
  616. if (pdata->buck2_gpiodvs) {
  617. if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) {
  618. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  619. return -EINVAL;
  620. }
  621. }
  622. if (pdata->buck3_gpiodvs) {
  623. if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) {
  624. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  625. return -EINVAL;
  626. }
  627. }
  628. if (pdata->buck4_gpiodvs) {
  629. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) {
  630. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  631. return -EINVAL;
  632. }
  633. }
  634. s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info),
  635. GFP_KERNEL);
  636. if (!s5m8767)
  637. return -ENOMEM;
  638. s5m8767->dev = &pdev->dev;
  639. s5m8767->iodev = iodev;
  640. s5m8767->num_regulators = pdata->num_regulators;
  641. platform_set_drvdata(pdev, s5m8767);
  642. s5m8767->buck_gpioindex = pdata->buck_default_idx;
  643. s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs;
  644. s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs;
  645. s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs;
  646. s5m8767->buck_gpios[0] = pdata->buck_gpios[0];
  647. s5m8767->buck_gpios[1] = pdata->buck_gpios[1];
  648. s5m8767->buck_gpios[2] = pdata->buck_gpios[2];
  649. s5m8767->buck_ds[0] = pdata->buck_ds[0];
  650. s5m8767->buck_ds[1] = pdata->buck_ds[1];
  651. s5m8767->buck_ds[2] = pdata->buck_ds[2];
  652. s5m8767->ramp_delay = pdata->buck_ramp_delay;
  653. s5m8767->buck2_ramp = pdata->buck2_ramp_enable;
  654. s5m8767->buck3_ramp = pdata->buck3_ramp_enable;
  655. s5m8767->buck4_ramp = pdata->buck4_ramp_enable;
  656. s5m8767->opmode = pdata->opmode;
  657. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  658. pdata->buck2_init);
  659. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK2DVS2,
  660. buck_init);
  661. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  662. pdata->buck3_init);
  663. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK3DVS2,
  664. buck_init);
  665. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  666. pdata->buck4_init);
  667. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK4DVS2,
  668. buck_init);
  669. for (i = 0; i < 8; i++) {
  670. if (s5m8767->buck2_gpiodvs) {
  671. s5m8767->buck2_vol[i] =
  672. s5m8767_convert_voltage_to_sel(
  673. &buck_voltage_val2,
  674. pdata->buck2_voltage[i]);
  675. }
  676. if (s5m8767->buck3_gpiodvs) {
  677. s5m8767->buck3_vol[i] =
  678. s5m8767_convert_voltage_to_sel(
  679. &buck_voltage_val2,
  680. pdata->buck3_voltage[i]);
  681. }
  682. if (s5m8767->buck4_gpiodvs) {
  683. s5m8767->buck4_vol[i] =
  684. s5m8767_convert_voltage_to_sel(
  685. &buck_voltage_val2,
  686. pdata->buck4_voltage[i]);
  687. }
  688. }
  689. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
  690. pdata->buck4_gpiodvs) {
  691. if (!gpio_is_valid(pdata->buck_gpios[0]) ||
  692. !gpio_is_valid(pdata->buck_gpios[1]) ||
  693. !gpio_is_valid(pdata->buck_gpios[2])) {
  694. dev_err(&pdev->dev, "GPIO NOT VALID\n");
  695. return -EINVAL;
  696. }
  697. ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0],
  698. "S5M8767 SET1");
  699. if (ret)
  700. return ret;
  701. ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1],
  702. "S5M8767 SET2");
  703. if (ret)
  704. return ret;
  705. ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2],
  706. "S5M8767 SET3");
  707. if (ret)
  708. return ret;
  709. /* SET1 GPIO */
  710. gpio_direction_output(pdata->buck_gpios[0],
  711. (s5m8767->buck_gpioindex >> 2) & 0x1);
  712. /* SET2 GPIO */
  713. gpio_direction_output(pdata->buck_gpios[1],
  714. (s5m8767->buck_gpioindex >> 1) & 0x1);
  715. /* SET3 GPIO */
  716. gpio_direction_output(pdata->buck_gpios[2],
  717. (s5m8767->buck_gpioindex >> 0) & 0x1);
  718. }
  719. ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2");
  720. if (ret)
  721. return ret;
  722. ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3");
  723. if (ret)
  724. return ret;
  725. ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4");
  726. if (ret)
  727. return ret;
  728. /* DS2 GPIO */
  729. gpio_direction_output(pdata->buck_ds[0], 0x0);
  730. /* DS3 GPIO */
  731. gpio_direction_output(pdata->buck_ds[1], 0x0);
  732. /* DS4 GPIO */
  733. gpio_direction_output(pdata->buck_ds[2], 0x0);
  734. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
  735. pdata->buck4_gpiodvs) {
  736. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  737. S5M8767_REG_BUCK2CTRL, 1 << 1,
  738. (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1));
  739. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  740. S5M8767_REG_BUCK3CTRL, 1 << 1,
  741. (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1));
  742. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  743. S5M8767_REG_BUCK4CTRL, 1 << 1,
  744. (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1));
  745. }
  746. /* Initialize GPIO DVS registers */
  747. for (i = 0; i < 8; i++) {
  748. if (s5m8767->buck2_gpiodvs) {
  749. regmap_write(s5m8767->iodev->regmap_pmic,
  750. S5M8767_REG_BUCK2DVS1 + i,
  751. s5m8767->buck2_vol[i]);
  752. }
  753. if (s5m8767->buck3_gpiodvs) {
  754. regmap_write(s5m8767->iodev->regmap_pmic,
  755. S5M8767_REG_BUCK3DVS1 + i,
  756. s5m8767->buck3_vol[i]);
  757. }
  758. if (s5m8767->buck4_gpiodvs) {
  759. regmap_write(s5m8767->iodev->regmap_pmic,
  760. S5M8767_REG_BUCK4DVS1 + i,
  761. s5m8767->buck4_vol[i]);
  762. }
  763. }
  764. if (s5m8767->buck2_ramp)
  765. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  766. S5M8767_REG_DVSRAMP, 0x08, 0x08);
  767. if (s5m8767->buck3_ramp)
  768. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  769. S5M8767_REG_DVSRAMP, 0x04, 0x04);
  770. if (s5m8767->buck4_ramp)
  771. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  772. S5M8767_REG_DVSRAMP, 0x02, 0x02);
  773. if (s5m8767->buck2_ramp || s5m8767->buck3_ramp
  774. || s5m8767->buck4_ramp) {
  775. unsigned int val;
  776. switch (s5m8767->ramp_delay) {
  777. case 5:
  778. val = S5M8767_DVS_BUCK_RAMP_5;
  779. break;
  780. case 10:
  781. val = S5M8767_DVS_BUCK_RAMP_10;
  782. break;
  783. case 25:
  784. val = S5M8767_DVS_BUCK_RAMP_25;
  785. break;
  786. case 50:
  787. val = S5M8767_DVS_BUCK_RAMP_50;
  788. break;
  789. case 100:
  790. val = S5M8767_DVS_BUCK_RAMP_100;
  791. break;
  792. default:
  793. val = S5M8767_DVS_BUCK_RAMP_10;
  794. }
  795. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  796. S5M8767_REG_DVSRAMP,
  797. S5M8767_DVS_BUCK_RAMP_MASK,
  798. val << S5M8767_DVS_BUCK_RAMP_SHIFT);
  799. }
  800. for (i = 0; i < pdata->num_regulators; i++) {
  801. const struct sec_voltage_desc *desc;
  802. int id = pdata->regulators[i].id;
  803. int enable_reg, enable_val;
  804. struct regulator_dev *rdev;
  805. desc = reg_voltage_map[id];
  806. if (desc) {
  807. regulators[id].n_voltages =
  808. (desc->max - desc->min) / desc->step + 1;
  809. regulators[id].min_uV = desc->min;
  810. regulators[id].uV_step = desc->step;
  811. regulators[id].vsel_reg =
  812. s5m8767_get_vsel_reg(id, s5m8767);
  813. if (id < S5M8767_BUCK1)
  814. regulators[id].vsel_mask = 0x3f;
  815. else
  816. regulators[id].vsel_mask = 0xff;
  817. ret = s5m8767_get_register(s5m8767, id, &enable_reg,
  818. &enable_val);
  819. if (ret) {
  820. dev_err(s5m8767->dev, "error reading registers\n");
  821. return ret;
  822. }
  823. regulators[id].enable_reg = enable_reg;
  824. regulators[id].enable_mask = S5M8767_ENCTRL_MASK;
  825. regulators[id].enable_val = enable_val;
  826. }
  827. config.dev = s5m8767->dev;
  828. config.init_data = pdata->regulators[i].initdata;
  829. config.driver_data = s5m8767;
  830. config.regmap = iodev->regmap_pmic;
  831. config.of_node = pdata->regulators[i].reg_node;
  832. config.ena_gpiod = NULL;
  833. if (pdata->regulators[i].ext_control_gpiod)
  834. s5m8767_regulator_config_ext_control(s5m8767,
  835. &pdata->regulators[i], &config);
  836. rdev = devm_regulator_register(&pdev->dev, &regulators[id],
  837. &config);
  838. if (IS_ERR(rdev)) {
  839. ret = PTR_ERR(rdev);
  840. dev_err(s5m8767->dev, "regulator init failed for %d\n",
  841. id);
  842. return ret;
  843. }
  844. if (pdata->regulators[i].ext_control_gpiod) {
  845. ret = s5m8767_enable_ext_control(s5m8767, rdev);
  846. if (ret < 0) {
  847. dev_err(s5m8767->dev,
  848. "failed to enable gpio control over %s: %d\n",
  849. rdev->desc->name, ret);
  850. return ret;
  851. }
  852. }
  853. }
  854. return 0;
  855. }
  856. static const struct platform_device_id s5m8767_pmic_id[] = {
  857. { "s5m8767-pmic", 0},
  858. { },
  859. };
  860. MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id);
  861. static struct platform_driver s5m8767_pmic_driver = {
  862. .driver = {
  863. .name = "s5m8767-pmic",
  864. },
  865. .probe = s5m8767_pmic_probe,
  866. .id_table = s5m8767_pmic_id,
  867. };
  868. static int __init s5m8767_pmic_init(void)
  869. {
  870. return platform_driver_register(&s5m8767_pmic_driver);
  871. }
  872. subsys_initcall(s5m8767_pmic_init);
  873. static void __exit s5m8767_pmic_exit(void)
  874. {
  875. platform_driver_unregister(&s5m8767_pmic_driver);
  876. }
  877. module_exit(s5m8767_pmic_exit);
  878. /* Module information */
  879. MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
  880. MODULE_DESCRIPTION("SAMSUNG S5M8767 Regulator Driver");
  881. MODULE_LICENSE("GPL");