tegra210-smaug.dts 55 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/mfd/max77620.h>
  5. #include <dt-bindings/pinctrl/pinctrl-tegra.h>
  6. #include "tegra210.dtsi"
  7. / {
  8. model = "Google Pixel C";
  9. compatible = "google,smaug-rev8", "google,smaug-rev7",
  10. "google,smaug-rev6", "google,smaug-rev5",
  11. "google,smaug-rev4", "google,smaug-rev3",
  12. "google,smaug-rev2", "google,smaug-rev1",
  13. "google,smaug", "nvidia,tegra210";
  14. aliases {
  15. serial0 = &uarta;
  16. };
  17. chosen {
  18. bootargs = "earlycon";
  19. stdout-path = "serial0:115200n8";
  20. };
  21. memory {
  22. device_type = "memory";
  23. reg = <0x0 0x80000000 0x0 0xc0000000>;
  24. };
  25. host1x@50000000 {
  26. dpaux: dpaux@545c0000 {
  27. status = "okay";
  28. };
  29. };
  30. pinmux: pinmux@700008d4 {
  31. pinctrl-names = "boot";
  32. pinctrl-0 = <&state_boot>;
  33. state_boot: pinmux {
  34. pex_l0_rst_n_pa0 {
  35. nvidia,pins = "pex_l0_rst_n_pa0";
  36. nvidia,function = "rsvd1";
  37. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  38. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  39. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  40. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  41. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  42. };
  43. pex_l0_clkreq_n_pa1 {
  44. nvidia,pins = "pex_l0_clkreq_n_pa1";
  45. nvidia,function = "rsvd1";
  46. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  47. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  48. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  49. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  50. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  51. };
  52. pex_wake_n_pa2 {
  53. nvidia,pins = "pex_wake_n_pa2";
  54. nvidia,function = "rsvd1";
  55. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  56. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  57. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  58. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  59. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  60. };
  61. pex_l1_rst_n_pa3 {
  62. nvidia,pins = "pex_l1_rst_n_pa3";
  63. nvidia,function = "rsvd1";
  64. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  65. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  66. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  67. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  68. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  69. };
  70. pex_l1_clkreq_n_pa4 {
  71. nvidia,pins = "pex_l1_clkreq_n_pa4";
  72. nvidia,function = "rsvd1";
  73. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  74. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  75. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  76. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  77. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  78. };
  79. sata_led_active_pa5 {
  80. nvidia,pins = "sata_led_active_pa5";
  81. nvidia,function = "rsvd1";
  82. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  83. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  84. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  85. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  86. };
  87. pa6 {
  88. nvidia,pins = "pa6";
  89. nvidia,function = "rsvd1";
  90. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  91. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  92. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  93. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  94. };
  95. dap1_fs_pb0 {
  96. nvidia,pins = "dap1_fs_pb0";
  97. nvidia,function = "i2s1";
  98. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  99. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  100. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  101. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  102. };
  103. dap1_din_pb1 {
  104. nvidia,pins = "dap1_din_pb1";
  105. nvidia,function = "i2s1";
  106. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  107. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  108. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  109. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  110. };
  111. dap1_dout_pb2 {
  112. nvidia,pins = "dap1_dout_pb2";
  113. nvidia,function = "i2s1";
  114. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  115. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  116. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  117. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  118. };
  119. dap1_sclk_pb3 {
  120. nvidia,pins = "dap1_sclk_pb3";
  121. nvidia,function = "i2s1";
  122. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  123. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  124. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  125. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  126. };
  127. spi2_mosi_pb4 {
  128. nvidia,pins = "spi2_mosi_pb4";
  129. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  130. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  131. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  132. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  133. };
  134. spi2_miso_pb5 {
  135. nvidia,pins = "spi2_miso_pb5";
  136. nvidia,function = "rsvd2";
  137. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  138. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  139. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  140. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  141. };
  142. spi2_sck_pb6 {
  143. nvidia,pins = "spi2_sck_pb6";
  144. nvidia,function = "rsvd2";
  145. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  146. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  147. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  148. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  149. };
  150. spi2_cs0_pb7 {
  151. nvidia,pins = "spi2_cs0_pb7";
  152. nvidia,function = "rsvd2";
  153. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  154. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  155. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  156. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  157. };
  158. spi1_mosi_pc0 {
  159. nvidia,pins = "spi1_mosi_pc0";
  160. nvidia,function = "spi1";
  161. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  162. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  163. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  164. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  165. };
  166. spi1_miso_pc1 {
  167. nvidia,pins = "spi1_miso_pc1";
  168. nvidia,function = "spi1";
  169. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  170. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  171. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  172. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  173. };
  174. spi1_sck_pc2 {
  175. nvidia,pins = "spi1_sck_pc2";
  176. nvidia,function = "spi1";
  177. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  178. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  179. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  180. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  181. };
  182. spi1_cs0_pc3 {
  183. nvidia,pins = "spi1_cs0_pc3";
  184. nvidia,function = "spi1";
  185. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  186. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  187. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  188. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  189. };
  190. spi1_cs1_pc4 {
  191. nvidia,pins = "spi1_cs1_pc4";
  192. nvidia,function = "rsvd1";
  193. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  194. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  195. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  196. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  197. };
  198. spi4_sck_pc5 {
  199. nvidia,pins = "spi4_sck_pc5";
  200. nvidia,function = "rsvd1";
  201. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  202. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  203. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  204. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  205. };
  206. spi4_cs0_pc6 {
  207. nvidia,pins = "spi4_cs0_pc6";
  208. nvidia,function = "rsvd1";
  209. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  210. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  211. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  212. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  213. };
  214. spi4_mosi_pc7 {
  215. nvidia,pins = "spi4_mosi_pc7";
  216. nvidia,function = "rsvd1";
  217. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  218. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  219. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  220. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  221. };
  222. spi4_miso_pd0 {
  223. nvidia,pins = "spi4_miso_pd0";
  224. nvidia,function = "rsvd1";
  225. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  226. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  227. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  228. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  229. };
  230. uart3_tx_pd1 {
  231. nvidia,pins = "uart3_tx_pd1";
  232. nvidia,function = "uartc";
  233. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  234. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  235. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  236. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  237. };
  238. uart3_rx_pd2 {
  239. nvidia,pins = "uart3_rx_pd2";
  240. nvidia,function = "uartc";
  241. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  242. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  243. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  244. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  245. };
  246. uart3_rts_pd3 {
  247. nvidia,pins = "uart3_rts_pd3";
  248. nvidia,function = "uartc";
  249. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  250. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  251. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  252. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  253. };
  254. uart3_cts_pd4 {
  255. nvidia,pins = "uart3_cts_pd4";
  256. nvidia,function = "uartc";
  257. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  258. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  259. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  260. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  261. };
  262. dmic1_clk_pe0 {
  263. nvidia,pins = "dmic1_clk_pe0";
  264. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  265. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  266. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  267. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  268. };
  269. dmic1_dat_pe1 {
  270. nvidia,pins = "dmic1_dat_pe1";
  271. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  272. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  273. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  274. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  275. };
  276. dmic2_clk_pe2 {
  277. nvidia,pins = "dmic2_clk_pe2";
  278. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  279. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  280. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  281. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  282. };
  283. dmic2_dat_pe3 {
  284. nvidia,pins = "dmic2_dat_pe3";
  285. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  286. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  287. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  288. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  289. };
  290. dmic3_clk_pe4 {
  291. nvidia,pins = "dmic3_clk_pe4";
  292. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  293. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  294. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  295. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  296. };
  297. dmic3_dat_pe5 {
  298. nvidia,pins = "dmic3_dat_pe5";
  299. nvidia,function = "rsvd2";
  300. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  301. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  302. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  303. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  304. };
  305. pe6 {
  306. nvidia,pins = "pe6";
  307. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  308. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  309. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  310. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  311. };
  312. pe7 {
  313. nvidia,pins = "pe7";
  314. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  315. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  316. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  317. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  318. };
  319. gen3_i2c_scl_pf0 {
  320. nvidia,pins = "gen3_i2c_scl_pf0";
  321. nvidia,function = "i2c3";
  322. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  323. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  324. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  325. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  326. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  327. };
  328. gen3_i2c_sda_pf1 {
  329. nvidia,pins = "gen3_i2c_sda_pf1";
  330. nvidia,function = "i2c3";
  331. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  332. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  333. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  334. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  335. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  336. };
  337. uart2_tx_pg0 {
  338. nvidia,pins = "uart2_tx_pg0";
  339. nvidia,function = "uartb";
  340. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  341. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  342. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  343. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  344. };
  345. uart2_rx_pg1 {
  346. nvidia,pins = "uart2_rx_pg1";
  347. nvidia,function = "uartb";
  348. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  349. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  350. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  351. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  352. };
  353. uart2_rts_pg2 {
  354. nvidia,pins = "uart2_rts_pg2";
  355. nvidia,function = "rsvd2";
  356. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  357. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  358. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  359. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  360. };
  361. uart2_cts_pg3 {
  362. nvidia,pins = "uart2_cts_pg3";
  363. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  364. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  365. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  366. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  367. };
  368. wifi_en_ph0 {
  369. nvidia,pins = "wifi_en_ph0";
  370. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  371. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  372. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  373. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  374. };
  375. wifi_rst_ph1 {
  376. nvidia,pins = "wifi_rst_ph1";
  377. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  378. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  379. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  380. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  381. };
  382. wifi_wake_ap_ph2 {
  383. nvidia,pins = "wifi_wake_ap_ph2";
  384. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  385. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  386. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  387. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  388. };
  389. ap_wake_bt_ph3 {
  390. nvidia,pins = "ap_wake_bt_ph3";
  391. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  392. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  393. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  394. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  395. };
  396. bt_rst_ph4 {
  397. nvidia,pins = "bt_rst_ph4";
  398. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  399. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  400. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  401. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  402. };
  403. bt_wake_ap_ph5 {
  404. nvidia,pins = "bt_wake_ap_ph5";
  405. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  406. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  407. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  408. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  409. };
  410. ph6 {
  411. nvidia,pins = "ph6";
  412. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  413. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  414. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  415. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  416. };
  417. ap_wake_nfc_ph7 {
  418. nvidia,pins = "ap_wake_nfc_ph7";
  419. nvidia,function = "rsvd0";
  420. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  421. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  422. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  423. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  424. };
  425. nfc_en_pi0 {
  426. nvidia,pins = "nfc_en_pi0";
  427. nvidia,function = "rsvd0";
  428. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  429. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  430. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  431. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  432. };
  433. nfc_int_pi1 {
  434. nvidia,pins = "nfc_int_pi1";
  435. nvidia,function = "rsvd0";
  436. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  437. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  438. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  439. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  440. };
  441. gps_en_pi2 {
  442. nvidia,pins = "gps_en_pi2";
  443. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  444. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  445. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  446. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  447. };
  448. gps_rst_pi3 {
  449. nvidia,pins = "gps_rst_pi3";
  450. nvidia,function = "rsvd0";
  451. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  452. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  453. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  454. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  455. };
  456. uart4_tx_pi4 {
  457. nvidia,pins = "uart4_tx_pi4";
  458. nvidia,function = "uartd";
  459. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  460. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  461. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  462. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  463. };
  464. uart4_rx_pi5 {
  465. nvidia,pins = "uart4_rx_pi5";
  466. nvidia,function = "uartd";
  467. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  468. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  469. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  470. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  471. };
  472. uart4_rts_pi6 {
  473. nvidia,pins = "uart4_rts_pi6";
  474. nvidia,function = "uartd";
  475. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  476. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  477. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  478. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  479. };
  480. uart4_cts_pi7 {
  481. nvidia,pins = "uart4_cts_pi7";
  482. nvidia,function = "uartd";
  483. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  484. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  485. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  486. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  487. };
  488. gen1_i2c_sda_pj0 {
  489. nvidia,pins = "gen1_i2c_sda_pj0";
  490. nvidia,function = "i2c1";
  491. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  492. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  493. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  494. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  495. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  496. };
  497. gen1_i2c_scl_pj1 {
  498. nvidia,pins = "gen1_i2c_scl_pj1";
  499. nvidia,function = "i2c1";
  500. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  501. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  502. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  503. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  504. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  505. };
  506. gen2_i2c_scl_pj2 {
  507. nvidia,pins = "gen2_i2c_scl_pj2";
  508. nvidia,function = "i2c2";
  509. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  510. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  511. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  512. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  513. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  514. };
  515. gen2_i2c_sda_pj3 {
  516. nvidia,pins = "gen2_i2c_sda_pj3";
  517. nvidia,function = "i2c2";
  518. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  519. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  520. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  521. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  522. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  523. };
  524. dap4_fs_pj4 {
  525. nvidia,pins = "dap4_fs_pj4";
  526. nvidia,function = "rsvd1";
  527. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  528. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  529. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  530. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  531. };
  532. dap4_din_pj5 {
  533. nvidia,pins = "dap4_din_pj5";
  534. nvidia,function = "rsvd1";
  535. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  536. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  537. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  538. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  539. };
  540. dap4_dout_pj6 {
  541. nvidia,pins = "dap4_dout_pj6";
  542. nvidia,function = "rsvd1";
  543. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  544. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  545. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  546. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  547. };
  548. dap4_sclk_pj7 {
  549. nvidia,pins = "dap4_sclk_pj7";
  550. nvidia,function = "rsvd1";
  551. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  552. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  553. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  554. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  555. };
  556. pk0 {
  557. nvidia,pins = "pk0";
  558. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  559. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  560. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  561. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  562. };
  563. pk1 {
  564. nvidia,pins = "pk1";
  565. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  566. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  567. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  568. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  569. };
  570. pk2 {
  571. nvidia,pins = "pk2";
  572. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  573. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  574. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  575. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  576. };
  577. pk3 {
  578. nvidia,pins = "pk3";
  579. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  580. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  581. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  582. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  583. };
  584. pk4 {
  585. nvidia,pins = "pk4";
  586. nvidia,function = "rsvd1";
  587. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  588. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  589. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  590. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  591. };
  592. pk5 {
  593. nvidia,pins = "pk5";
  594. nvidia,function = "rsvd1";
  595. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  596. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  597. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  598. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  599. };
  600. pk6 {
  601. nvidia,pins = "pk6";
  602. nvidia,function = "rsvd1";
  603. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  604. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  605. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  606. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  607. };
  608. pk7 {
  609. nvidia,pins = "pk7";
  610. nvidia,function = "rsvd1";
  611. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  612. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  613. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  614. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  615. };
  616. pl0 {
  617. nvidia,pins = "pl0";
  618. nvidia,function = "rsvd0";
  619. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  620. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  621. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  622. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  623. };
  624. pl1 {
  625. nvidia,pins = "pl1";
  626. nvidia,function = "rsvd1";
  627. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  628. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  629. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  630. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  631. };
  632. sdmmc1_clk_pm0 {
  633. nvidia,pins = "sdmmc1_clk_pm0";
  634. nvidia,function = "rsvd1";
  635. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  636. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  637. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  638. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  639. };
  640. sdmmc1_cmd_pm1 {
  641. nvidia,pins = "sdmmc1_cmd_pm1";
  642. nvidia,function = "rsvd2";
  643. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  644. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  645. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  646. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  647. };
  648. sdmmc1_dat3_pm2 {
  649. nvidia,pins = "sdmmc1_dat3_pm2";
  650. nvidia,function = "rsvd2";
  651. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  652. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  653. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  654. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  655. };
  656. sdmmc1_dat2_pm3 {
  657. nvidia,pins = "sdmmc1_dat2_pm3";
  658. nvidia,function = "rsvd2";
  659. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  660. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  661. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  662. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  663. };
  664. sdmmc1_dat1_pm4 {
  665. nvidia,pins = "sdmmc1_dat1_pm4";
  666. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  667. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  668. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  669. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  670. };
  671. sdmmc1_dat0_pm5 {
  672. nvidia,pins = "sdmmc1_dat0_pm5";
  673. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  674. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  675. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  676. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  677. };
  678. sdmmc3_clk_pp0 {
  679. nvidia,pins = "sdmmc3_clk_pp0";
  680. nvidia,function = "rsvd1";
  681. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  682. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  683. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  684. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  685. };
  686. sdmmc3_cmd_pp1 {
  687. nvidia,pins = "sdmmc3_cmd_pp1";
  688. nvidia,function = "rsvd1";
  689. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  690. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  691. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  692. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  693. };
  694. sdmmc3_dat3_pp2 {
  695. nvidia,pins = "sdmmc3_dat3_pp2";
  696. nvidia,function = "rsvd1";
  697. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  698. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  699. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  700. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  701. };
  702. sdmmc3_dat2_pp3 {
  703. nvidia,pins = "sdmmc3_dat2_pp3";
  704. nvidia,function = "rsvd1";
  705. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  706. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  707. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  708. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  709. };
  710. sdmmc3_dat1_pp4 {
  711. nvidia,pins = "sdmmc3_dat1_pp4";
  712. nvidia,function = "rsvd1";
  713. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  714. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  715. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  716. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  717. };
  718. sdmmc3_dat0_pp5 {
  719. nvidia,pins = "sdmmc3_dat0_pp5";
  720. nvidia,function = "rsvd1";
  721. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  722. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  723. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  724. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  725. };
  726. cam1_mclk_ps0 {
  727. nvidia,pins = "cam1_mclk_ps0";
  728. nvidia,function = "extperiph3";
  729. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  730. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  731. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  732. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  733. };
  734. cam2_mclk_ps1 {
  735. nvidia,pins = "cam2_mclk_ps1";
  736. nvidia,function = "extperiph3";
  737. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  738. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  739. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  740. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  741. };
  742. cam_i2c_scl_ps2 {
  743. nvidia,pins = "cam_i2c_scl_ps2";
  744. nvidia,function = "i2cvi";
  745. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  746. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  747. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  748. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  749. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  750. };
  751. cam_i2c_sda_ps3 {
  752. nvidia,pins = "cam_i2c_sda_ps3";
  753. nvidia,function = "i2cvi";
  754. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  755. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  756. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  757. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  758. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  759. };
  760. cam_rst_ps4 {
  761. nvidia,pins = "cam_rst_ps4";
  762. nvidia,function = "rsvd1";
  763. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  764. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  765. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  766. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  767. };
  768. cam_af_en_ps5 {
  769. nvidia,pins = "cam_af_en_ps5";
  770. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  771. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  772. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  773. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  774. };
  775. cam_flash_en_ps6 {
  776. nvidia,pins = "cam_flash_en_ps6";
  777. nvidia,function = "rsvd2";
  778. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  779. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  780. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  781. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  782. };
  783. cam1_pwdn_ps7 {
  784. nvidia,pins = "cam1_pwdn_ps7";
  785. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  786. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  787. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  788. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  789. };
  790. cam2_pwdn_pt0 {
  791. nvidia,pins = "cam2_pwdn_pt0";
  792. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  793. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  794. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  795. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  796. };
  797. cam1_strobe_pt1 {
  798. nvidia,pins = "cam1_strobe_pt1";
  799. nvidia,function = "rsvd1";
  800. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  801. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  802. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  803. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  804. };
  805. uart1_tx_pu0 {
  806. nvidia,pins = "uart1_tx_pu0";
  807. nvidia,function = "uarta";
  808. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  809. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  810. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  811. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  812. };
  813. uart1_rx_pu1 {
  814. nvidia,pins = "uart1_rx_pu1";
  815. nvidia,function = "uarta";
  816. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  817. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  818. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  819. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  820. };
  821. uart1_rts_pu2 {
  822. nvidia,pins = "uart1_rts_pu2";
  823. nvidia,function = "rsvd1";
  824. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  825. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  826. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  827. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  828. };
  829. uart1_cts_pu3 {
  830. nvidia,pins = "uart1_cts_pu3";
  831. nvidia,function = "rsvd1";
  832. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  833. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  834. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  835. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  836. };
  837. lcd_bl_pwm_pv0 {
  838. nvidia,pins = "lcd_bl_pwm_pv0";
  839. nvidia,function = "rsvd3";
  840. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  841. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  842. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  843. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  844. };
  845. lcd_bl_en_pv1 {
  846. nvidia,pins = "lcd_bl_en_pv1";
  847. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  848. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  849. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  850. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  851. };
  852. lcd_rst_pv2 {
  853. nvidia,pins = "lcd_rst_pv2";
  854. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  855. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  856. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  857. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  858. };
  859. lcd_gpio1_pv3 {
  860. nvidia,pins = "lcd_gpio1_pv3";
  861. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  862. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  863. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  864. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  865. };
  866. lcd_gpio2_pv4 {
  867. nvidia,pins = "lcd_gpio2_pv4";
  868. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  869. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  870. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  871. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  872. };
  873. ap_ready_pv5 {
  874. nvidia,pins = "ap_ready_pv5";
  875. nvidia,function = "rsvd0";
  876. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  877. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  878. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  879. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  880. };
  881. touch_rst_pv6 {
  882. nvidia,pins = "touch_rst_pv6";
  883. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  884. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  885. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  886. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  887. };
  888. touch_clk_pv7 {
  889. nvidia,pins = "touch_clk_pv7";
  890. nvidia,function = "touch";
  891. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  892. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  893. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  894. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  895. };
  896. modem_wake_ap_px0 {
  897. nvidia,pins = "modem_wake_ap_px0";
  898. nvidia,function = "rsvd0";
  899. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  900. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  901. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  902. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  903. };
  904. touch_int_px1 {
  905. nvidia,pins = "touch_int_px1";
  906. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  907. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  908. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  909. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  910. };
  911. motion_int_px2 {
  912. nvidia,pins = "motion_int_px2";
  913. nvidia,function = "rsvd0";
  914. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  915. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  916. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  917. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  918. };
  919. als_prox_int_px3 {
  920. nvidia,pins = "als_prox_int_px3";
  921. nvidia,function = "rsvd0";
  922. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  923. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  924. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  925. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  926. };
  927. temp_alert_px4 {
  928. nvidia,pins = "temp_alert_px4";
  929. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  930. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  931. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  932. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  933. };
  934. button_power_on_px5 {
  935. nvidia,pins = "button_power_on_px5";
  936. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  937. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  938. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  939. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  940. };
  941. button_vol_up_px6 {
  942. nvidia,pins = "button_vol_up_px6";
  943. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  944. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  945. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  946. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  947. };
  948. button_vol_down_px7 {
  949. nvidia,pins = "button_vol_down_px7";
  950. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  951. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  952. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  953. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  954. };
  955. button_slide_sw_py0 {
  956. nvidia,pins = "button_slide_sw_py0";
  957. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  958. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  959. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  960. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  961. };
  962. button_home_py1 {
  963. nvidia,pins = "button_home_py1";
  964. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  965. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  966. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  967. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  968. };
  969. lcd_te_py2 {
  970. nvidia,pins = "lcd_te_py2";
  971. nvidia,function = "displaya";
  972. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  973. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  974. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  975. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  976. };
  977. pwr_i2c_scl_py3 {
  978. nvidia,pins = "pwr_i2c_scl_py3";
  979. nvidia,function = "i2cpmu";
  980. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  981. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  982. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  983. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  984. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  985. };
  986. pwr_i2c_sda_py4 {
  987. nvidia,pins = "pwr_i2c_sda_py4";
  988. nvidia,function = "i2cpmu";
  989. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  990. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  991. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  992. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  993. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  994. };
  995. clk_32k_out_py5 {
  996. nvidia,pins = "clk_32k_out_py5";
  997. nvidia,function = "soc";
  998. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  999. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1000. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1001. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1002. };
  1003. pz0 {
  1004. nvidia,pins = "pz0";
  1005. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1006. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1007. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1008. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1009. };
  1010. pz1 {
  1011. nvidia,pins = "pz1";
  1012. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1013. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1014. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1015. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1016. };
  1017. pz2 {
  1018. nvidia,pins = "pz2";
  1019. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1020. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1021. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1022. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1023. };
  1024. pz3 {
  1025. nvidia,pins = "pz3";
  1026. nvidia,function = "rsvd1";
  1027. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1028. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1029. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1030. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1031. };
  1032. pz4 {
  1033. nvidia,pins = "pz4";
  1034. nvidia,function = "rsvd1";
  1035. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1036. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1037. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1038. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1039. };
  1040. pz5 {
  1041. nvidia,pins = "pz5";
  1042. nvidia,function = "soc";
  1043. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1044. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1045. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1046. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1047. };
  1048. dap2_fs_paa0 {
  1049. nvidia,pins = "dap2_fs_paa0";
  1050. nvidia,function = "i2s2";
  1051. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1052. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1053. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1054. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1055. };
  1056. dap2_sclk_paa1 {
  1057. nvidia,pins = "dap2_sclk_paa1";
  1058. nvidia,function = "i2s2";
  1059. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1060. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1061. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1062. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1063. };
  1064. dap2_din_paa2 {
  1065. nvidia,pins = "dap2_din_paa2";
  1066. nvidia,function = "i2s2";
  1067. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1068. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1069. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1070. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1071. };
  1072. dap2_dout_paa3 {
  1073. nvidia,pins = "dap2_dout_paa3";
  1074. nvidia,function = "i2s2";
  1075. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1076. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1077. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1078. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1079. };
  1080. aud_mclk_pbb0 {
  1081. nvidia,pins = "aud_mclk_pbb0";
  1082. nvidia,function = "aud";
  1083. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1084. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1085. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1086. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1087. };
  1088. dvfs_pwm_pbb1 {
  1089. nvidia,pins = "dvfs_pwm_pbb1";
  1090. nvidia,function = "rsvd0";
  1091. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1092. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1093. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1094. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1095. };
  1096. dvfs_clk_pbb2 {
  1097. nvidia,pins = "dvfs_clk_pbb2";
  1098. nvidia,function = "rsvd0";
  1099. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1100. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1101. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1102. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1103. };
  1104. gpio_x1_aud_pbb3 {
  1105. nvidia,pins = "gpio_x1_aud_pbb3";
  1106. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1107. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1108. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1109. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1110. };
  1111. gpio_x3_aud_pbb4 {
  1112. nvidia,pins = "gpio_x3_aud_pbb4";
  1113. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1114. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1115. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1116. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1117. };
  1118. hdmi_cec_pcc0 {
  1119. nvidia,pins = "hdmi_cec_pcc0";
  1120. nvidia,function = "rsvd1";
  1121. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1122. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1123. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1124. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1125. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1126. };
  1127. hdmi_int_dp_hpd_pcc1 {
  1128. nvidia,pins = "hdmi_int_dp_hpd_pcc1";
  1129. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1130. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1131. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1132. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1133. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1134. };
  1135. spdif_out_pcc2 {
  1136. nvidia,pins = "spdif_out_pcc2";
  1137. nvidia,function = "rsvd1";
  1138. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1139. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1140. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1141. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1142. };
  1143. spdif_in_pcc3 {
  1144. nvidia,pins = "spdif_in_pcc3";
  1145. nvidia,function = "rsvd1";
  1146. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1147. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1148. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1149. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1150. };
  1151. usb_vbus_en0_pcc4 {
  1152. nvidia,pins = "usb_vbus_en0_pcc4";
  1153. nvidia,function = "rsvd1";
  1154. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1155. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1156. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1157. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1158. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1159. };
  1160. usb_vbus_en1_pcc5 {
  1161. nvidia,pins = "usb_vbus_en1_pcc5";
  1162. nvidia,function = "rsvd1";
  1163. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1164. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1165. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1166. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1167. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1168. };
  1169. dp_hpd0_pcc6 {
  1170. nvidia,pins = "dp_hpd0_pcc6";
  1171. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1172. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1173. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1174. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1175. };
  1176. pcc7 {
  1177. nvidia,pins = "pcc7";
  1178. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1179. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1180. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1181. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1182. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1183. };
  1184. spi2_cs1_pdd0 {
  1185. nvidia,pins = "spi2_cs1_pdd0";
  1186. nvidia,function = "rsvd1";
  1187. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1188. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1189. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1190. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1191. };
  1192. qspi_sck_pee0 {
  1193. nvidia,pins = "qspi_sck_pee0";
  1194. nvidia,function = "qspi";
  1195. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1196. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1197. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1198. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1199. };
  1200. qspi_cs_n_pee1 {
  1201. nvidia,pins = "qspi_cs_n_pee1";
  1202. nvidia,function = "qspi";
  1203. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1204. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1205. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1206. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1207. };
  1208. qspi_io0_pee2 {
  1209. nvidia,pins = "qspi_io0_pee2";
  1210. nvidia,function = "qspi";
  1211. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1212. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1213. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1214. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1215. };
  1216. qspi_io1_pee3 {
  1217. nvidia,pins = "qspi_io1_pee3";
  1218. nvidia,function = "qspi";
  1219. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1220. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1221. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1222. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1223. };
  1224. qspi_io2_pee4 {
  1225. nvidia,pins = "qspi_io2_pee4";
  1226. nvidia,function = "rsvd1";
  1227. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1228. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1229. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1230. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1231. };
  1232. qspi_io3_pee5 {
  1233. nvidia,pins = "qspi_io3_pee5";
  1234. nvidia,function = "rsvd1";
  1235. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1236. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1237. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1238. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1239. };
  1240. core_pwr_req {
  1241. nvidia,pins = "core_pwr_req";
  1242. nvidia,function = "core";
  1243. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1244. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1245. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1246. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1247. };
  1248. cpu_pwr_req {
  1249. nvidia,pins = "cpu_pwr_req";
  1250. nvidia,function = "cpu";
  1251. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1252. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1253. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1254. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1255. };
  1256. pwr_int_n {
  1257. nvidia,pins = "pwr_int_n";
  1258. nvidia,function = "pmi";
  1259. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1260. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1261. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1262. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1263. };
  1264. clk_32k_in {
  1265. nvidia,pins = "clk_32k_in";
  1266. nvidia,function = "clk";
  1267. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1268. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1269. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1270. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1271. };
  1272. jtag_rtck {
  1273. nvidia,pins = "jtag_rtck";
  1274. nvidia,function = "jtag";
  1275. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1276. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1277. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1278. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1279. };
  1280. clk_req {
  1281. nvidia,pins = "clk_req";
  1282. nvidia,function = "rsvd1";
  1283. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1284. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1285. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1286. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1287. };
  1288. shutdown {
  1289. nvidia,pins = "shutdown";
  1290. nvidia,function = "shutdown";
  1291. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1292. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1293. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1294. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1295. };
  1296. };
  1297. };
  1298. serial@70006000 {
  1299. status = "okay";
  1300. };
  1301. i2c@7000c400 {
  1302. status = "okay";
  1303. clock-frequency = <1000000>;
  1304. ec@1e {
  1305. compatible = "google,cros-ec-i2c";
  1306. reg = <0x1e>;
  1307. interrupt-parent = <&gpio>;
  1308. interrupts = <TEGRA_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>;
  1309. wakeup-source;
  1310. ec_i2c_0: i2c-tunnel {
  1311. compatible = "google,cros-ec-i2c-tunnel";
  1312. #address-cells = <1>;
  1313. #size-cells = <0>;
  1314. google,remote-bus = <0>;
  1315. battery: bq27742@55 {
  1316. compatible = "ti,bq27742";
  1317. reg = <0x55>;
  1318. battery-name = "battery";
  1319. };
  1320. };
  1321. };
  1322. };
  1323. i2c@7000d000 {
  1324. status = "okay";
  1325. clock-frequency = <1000000>;
  1326. max77620: max77620@3c {
  1327. compatible = "maxim,max77620";
  1328. reg = <0x3c>;
  1329. interrupts = <0 86 IRQ_TYPE_NONE>;
  1330. #interrupt-cells = <2>;
  1331. interrupt-controller;
  1332. gpio-controller;
  1333. #gpio-cells = <2>;
  1334. pinctrl-names = "default";
  1335. pinctrl-0 = <&max77620_default>;
  1336. max77620_default: pinmux@0 {
  1337. pin_gpio {
  1338. pins = "gpio0", "gpio1", "gpio2", "gpio7";
  1339. function = "gpio";
  1340. };
  1341. /*
  1342. * GPIO3 is used to en_pp3300, and it is part of power
  1343. * sequence, So it must be sequenced up (automatically
  1344. * set by OTP) and down properly.
  1345. */
  1346. pin_gpio3 {
  1347. pins = "gpio3";
  1348. function = "fps-out";
  1349. drive-open-drain = <1>;
  1350. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1351. maxim,active-fps-power-up-slot = <4>;
  1352. maxim,active-fps-power-down-slot = <2>;
  1353. };
  1354. pin_gpio5_6 {
  1355. pins = "gpio5", "gpio6";
  1356. function = "gpio";
  1357. drive-push-pull = <1>;
  1358. };
  1359. pin_32k {
  1360. pins = "gpio4";
  1361. function = "32k-out1";
  1362. };
  1363. };
  1364. fps {
  1365. fps0 {
  1366. maxim,shutdown-fps-time-period-us = <5120>;
  1367. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
  1368. };
  1369. fps1 {
  1370. maxim,shutdown-fps-time-period-us = <5120>;
  1371. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
  1372. maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
  1373. };
  1374. fps2 {
  1375. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
  1376. };
  1377. };
  1378. regulators {
  1379. in-ldo0-1-supply = <&pp1350>;
  1380. in-ldo2-supply = <&pp3300>;
  1381. in-ldo3-5-supply = <&pp3300>;
  1382. in-ldo7-8-supply = <&pp1350>;
  1383. ppvar_soc: sd0 {
  1384. regulator-name = "PPVAR_SOC";
  1385. regulator-min-microvolt = <825000>;
  1386. regulator-max-microvolt = <1125000>;
  1387. regulator-always-on;
  1388. regulator-boot-on;
  1389. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  1390. maxim,active-fps-power-up-slot = <1>;
  1391. maxim,active-fps-power-down-slot = <7>;
  1392. };
  1393. pp1100_sd1: sd1 {
  1394. regulator-name = "PP1100";
  1395. regulator-min-microvolt = <1125000>;
  1396. regulator-max-microvolt = <1125000>;
  1397. regulator-always-on;
  1398. regulator-boot-on;
  1399. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1400. maxim,active-fps-power-up-slot = <5>;
  1401. maxim,active-fps-power-down-slot = <1>;
  1402. };
  1403. pp1350: sd2 {
  1404. regulator-name = "PP1350";
  1405. regulator-min-microvolt = <1350000>;
  1406. regulator-max-microvolt = <1350000>;
  1407. regulator-always-on;
  1408. regulator-boot-on;
  1409. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1410. maxim,active-fps-power-up-slot = <2>;
  1411. maxim,active-fps-power-down-slot = <5>;
  1412. };
  1413. pp1800: sd3 {
  1414. regulator-name = "PP1800";
  1415. regulator-min-microvolt = <1800000>;
  1416. regulator-max-microvolt = <1800000>;
  1417. regulator-always-on;
  1418. regulator-boot-on;
  1419. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1420. maxim,active-fps-power-up-slot = <3>;
  1421. maxim,active-fps-power-down-slot = <3>;
  1422. };
  1423. pp1200_avdd: ldo0 {
  1424. regulator-name = "PP1200_AVDD";
  1425. regulator-min-microvolt = <1200000>;
  1426. regulator-max-microvolt = <1200000>;
  1427. regulator-enable-ramp-delay = <26>;
  1428. regulator-ramp-delay = <100000>;
  1429. regulator-boot-on;
  1430. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1431. maxim,active-fps-power-up-slot = <0>;
  1432. maxim,active-fps-power-down-slot = <7>;
  1433. };
  1434. pp1200_rcam: ldo1 {
  1435. regulator-name = "PP1200_RCAM";
  1436. regulator-min-microvolt = <1200000>;
  1437. regulator-max-microvolt = <1200000>;
  1438. regulator-enable-ramp-delay = <22>;
  1439. regulator-ramp-delay = <100000>;
  1440. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1441. maxim,active-fps-power-up-slot = <0>;
  1442. maxim,active-fps-power-down-slot = <7>;
  1443. };
  1444. pp_ldo2: ldo2 {
  1445. regulator-name = "PP_LDO2";
  1446. regulator-min-microvolt = <1800000>;
  1447. regulator-max-microvolt = <1800000>;
  1448. regulator-enable-ramp-delay = <62>;
  1449. regulator-ramp-delay = <11000>;
  1450. regulator-always-on;
  1451. regulator-boot-on;
  1452. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1453. maxim,active-fps-power-up-slot = <0>;
  1454. maxim,active-fps-power-down-slot = <7>;
  1455. };
  1456. pp2800l_rcam: ldo3 {
  1457. regulator-name = "PP2800L_RCAM";
  1458. regulator-min-microvolt = <2800000>;
  1459. regulator-max-microvolt = <2800000>;
  1460. regulator-enable-ramp-delay = <50>;
  1461. regulator-ramp-delay = <100000>;
  1462. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1463. maxim,active-fps-power-up-slot = <0>;
  1464. maxim,active-fps-power-down-slot = <7>;
  1465. };
  1466. pp100_soc_rtc: ldo4 {
  1467. regulator-name = "PP1100_SOC_RTC";
  1468. regulator-min-microvolt = <850000>;
  1469. regulator-max-microvolt = <850000>;
  1470. regulator-enable-ramp-delay = <22>;
  1471. regulator-ramp-delay = <100000>;
  1472. regulator-always-on; /* Check this */
  1473. regulator-boot-on;
  1474. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1475. maxim,active-fps-power-up-slot = <1>;
  1476. maxim,active-fps-power-down-slot = <7>;
  1477. };
  1478. pp2800l_fcam: ldo5 {
  1479. regulator-name = "PP2800L_FCAM";
  1480. regulator-min-microvolt = <2800000>;
  1481. regulator-max-microvolt = <2800000>;
  1482. regulator-enable-ramp-delay = <62>;
  1483. regulator-ramp-delay = <100000>;
  1484. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1485. maxim,active-fps-power-up-slot = <0>;
  1486. maxim,active-fps-power-down-slot = <7>;
  1487. };
  1488. ldo6 {
  1489. /* Unused. */
  1490. regulator-name = "PP_LDO6";
  1491. regulator-min-microvolt = <1800000>;
  1492. regulator-max-microvolt = <1800000>;
  1493. regulator-enable-ramp-delay = <36>;
  1494. regulator-ramp-delay = <100000>;
  1495. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1496. maxim,active-fps-power-up-slot = <0>;
  1497. maxim,active-fps-power-down-slot = <7>;
  1498. };
  1499. pp1050_avdd: ldo7 {
  1500. regulator-name = "PP1050_AVDD";
  1501. regulator-min-microvolt = <1050000>;
  1502. regulator-max-microvolt = <1050000>;
  1503. regulator-enable-ramp-delay = <24>;
  1504. regulator-ramp-delay = <100000>;
  1505. regulator-always-on;
  1506. regulator-boot-on;
  1507. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  1508. maxim,active-fps-power-up-slot = <3>;
  1509. maxim,active-fps-power-down-slot = <4>;
  1510. };
  1511. avddio_1v05: ldo8 {
  1512. regulator-name = "AVDDIO_1V05";
  1513. regulator-min-microvolt = <1050000>;
  1514. regulator-max-microvolt = <1050000>;
  1515. regulator-enable-ramp-delay = <22>;
  1516. regulator-ramp-delay = <100000>;
  1517. regulator-boot-on;
  1518. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1519. maxim,active-fps-power-up-slot = <0>;
  1520. maxim,active-fps-power-down-slot = <7>;
  1521. };
  1522. };
  1523. };
  1524. };
  1525. i2c@7000d100 {
  1526. status = "okay";
  1527. clock-frequency = <400000>;
  1528. nau8825@1a {
  1529. compatible = "nuvoton,nau8825";
  1530. reg = <0x1a>;
  1531. interrupt-parent = <&gpio>;
  1532. interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>;
  1533. clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
  1534. clock-names = "mclk";
  1535. nuvoton,jkdet-enable;
  1536. nuvoton,jkdet-polarity = <GPIO_ACTIVE_LOW>;
  1537. nuvoton,vref-impedance = <2>;
  1538. nuvoton,micbias-voltage = <6>;
  1539. nuvoton,sar-threshold-num = <4>;
  1540. nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>;
  1541. nuvoton,sar-hysteresis = <1>;
  1542. nuvoton,sar-voltage = <0>;
  1543. nuvoton,sar-compare-time = <0>;
  1544. nuvoton,sar-sampling-time = <0>;
  1545. nuvoton,short-key-debounce = <2>;
  1546. nuvoton,jack-insert-debounce = <7>;
  1547. nuvoton,jack-eject-debounce = <7>;
  1548. status = "okay";
  1549. };
  1550. audio-codec@2d {
  1551. compatible = "realtek,rt5677";
  1552. reg = <0x2d>;
  1553. interrupt-parent = <&gpio>;
  1554. interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_LEVEL_HIGH>;
  1555. realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>;
  1556. gpio-controller;
  1557. #gpio-cells = <2>;
  1558. status = "okay";
  1559. };
  1560. };
  1561. pmc@7000e400 {
  1562. nvidia,invert-interrupt;
  1563. nvidia,suspend-mode = <0>;
  1564. nvidia,cpu-pwr-good-time = <0>;
  1565. nvidia,cpu-pwr-off-time = <0>;
  1566. nvidia,core-pwr-good-time = <12000 6000>;
  1567. nvidia,core-pwr-off-time = <39053>;
  1568. nvidia,core-power-req-active-high;
  1569. nvidia,sys-clock-req-active-high;
  1570. status = "okay";
  1571. };
  1572. usb@70090000 {
  1573. phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
  1574. <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
  1575. phy-names = "usb2-0", "usb3-0";
  1576. dvddio-pex-supply = <&avddio_1v05>;
  1577. hvddio-pex-supply = <&pp1800>;
  1578. avdd-usb-supply = <&pp3300>;
  1579. avdd-pll-utmip-supply = <&pp1800>;
  1580. avdd-pll-uerefe-supply = <&pp1050_avdd>;
  1581. dvdd-pex-pll-supply = <&avddio_1v05>;
  1582. hvdd-pex-pll-e-supply = <&pp1800>;
  1583. status = "okay";
  1584. };
  1585. padctl@7009f000 {
  1586. status = "okay";
  1587. pads {
  1588. usb2 {
  1589. status = "okay";
  1590. lanes {
  1591. usb2-0 {
  1592. nvidia,function = "xusb";
  1593. status = "okay";
  1594. };
  1595. };
  1596. };
  1597. pcie {
  1598. status = "okay";
  1599. lanes {
  1600. pcie-6 {
  1601. nvidia,function = "usb3-ss";
  1602. status = "okay";
  1603. };
  1604. };
  1605. };
  1606. };
  1607. ports {
  1608. usb2-0 {
  1609. status = "okay";
  1610. vbus-supply = <&usbc_vbus>;
  1611. mode = "otg";
  1612. };
  1613. usb3-0 {
  1614. nvidia,usb2-companion = <0>;
  1615. status = "okay";
  1616. };
  1617. };
  1618. };
  1619. sdhci@700b0600 {
  1620. bus-width = <8>;
  1621. non-removable;
  1622. status = "okay";
  1623. };
  1624. aconnect@702c0000 {
  1625. status = "okay";
  1626. dma@702e2000 {
  1627. status = "okay";
  1628. };
  1629. agic@702f9000 {
  1630. status = "okay";
  1631. };
  1632. };
  1633. clocks {
  1634. compatible = "simple-bus";
  1635. #address-cells = <1>;
  1636. #size-cells = <0>;
  1637. clk32k_in: clock@0 {
  1638. compatible = "fixed-clock";
  1639. reg = <0>;
  1640. #clock-cells = <0>;
  1641. clock-frequency = <32768>;
  1642. };
  1643. };
  1644. cpus {
  1645. cpu@0 {
  1646. enable-method = "psci";
  1647. };
  1648. cpu@1 {
  1649. enable-method = "psci";
  1650. };
  1651. cpu@2 {
  1652. enable-method = "psci";
  1653. };
  1654. cpu@3 {
  1655. enable-method = "psci";
  1656. };
  1657. };
  1658. gpio-keys {
  1659. compatible = "gpio-keys";
  1660. gpio-keys,name = "gpio-keys";
  1661. power {
  1662. label = "Power";
  1663. gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
  1664. linux,code = <KEY_POWER>;
  1665. debounce-interval = <30>;
  1666. wakeup-source;
  1667. };
  1668. lid {
  1669. label = "Lid";
  1670. gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>;
  1671. linux,input-type = <EV_SW>;
  1672. linux,code = <SW_LID>;
  1673. wakeup-source;
  1674. };
  1675. tablet_mode {
  1676. label = "Tablet Mode";
  1677. gpios = <&gpio TEGRA_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
  1678. linux,input-type = <EV_SW>;
  1679. linux,code = <SW_TABLET_MODE>;
  1680. wakeup-source;
  1681. };
  1682. volume_down {
  1683. label = "Volume Down";
  1684. gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
  1685. linux,code = <KEY_VOLUMEDOWN>;
  1686. };
  1687. volume_up {
  1688. label = "Volume Up";
  1689. gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>;
  1690. linux,code = <KEY_VOLUMEUP>;
  1691. };
  1692. };
  1693. max98357a {
  1694. compatible = "maxim,max98357a";
  1695. status = "okay";
  1696. };
  1697. psci {
  1698. compatible = "arm,psci-1.0";
  1699. method = "smc";
  1700. };
  1701. regulators {
  1702. compatible = "simple-bus";
  1703. device_type = "fixed-regulators";
  1704. #address-cells = <1>;
  1705. #size-cells = <0>;
  1706. ppvar_sys: regulator@0 {
  1707. compatible = "regulator-fixed";
  1708. reg = <0>;
  1709. regulator-name = "PPVAR_SYS";
  1710. regulator-min-microvolt = <4400000>;
  1711. regulator-max-microvolt = <4400000>;
  1712. regulator-always-on;
  1713. };
  1714. pplcd_vdd: regulator@1 {
  1715. compatible = "regulator-fixed";
  1716. reg = <1>;
  1717. regulator-name = "PPLCD_VDD";
  1718. regulator-min-microvolt = <4400000>;
  1719. regulator-max-microvolt = <4400000>;
  1720. gpio = <&gpio TEGRA_GPIO(V, 4) 0>;
  1721. enable-active-high;
  1722. regulator-boot-on;
  1723. };
  1724. pp3000_always: regulator@2 {
  1725. compatible = "regulator-fixed";
  1726. reg = <2>;
  1727. regulator-name = "PP3000_ALWAYS";
  1728. regulator-min-microvolt = <3000000>;
  1729. regulator-max-microvolt = <3000000>;
  1730. regulator-always-on;
  1731. };
  1732. pp3300: regulator@3 {
  1733. compatible = "regulator-fixed";
  1734. reg = <3>;
  1735. regulator-name = "PP3300";
  1736. regulator-min-microvolt = <3300000>;
  1737. regulator-max-microvolt = <3300000>;
  1738. regulator-boot-on;
  1739. regulator-always-on;
  1740. enable-active-high;
  1741. };
  1742. pp5000: regulator@4 {
  1743. compatible = "regulator-fixed";
  1744. reg = <4>;
  1745. regulator-name = "PP5000";
  1746. regulator-min-microvolt = <5000000>;
  1747. regulator-max-microvolt = <5000000>;
  1748. regulator-always-on;
  1749. };
  1750. pp1800_lcdio: regulator@5 {
  1751. compatible = "regulator-fixed";
  1752. reg = <5>;
  1753. regulator-name = "PP1800_LCDIO";
  1754. regulator-min-microvolt = <1800000>;
  1755. regulator-max-microvolt = <1800000>;
  1756. gpio = <&gpio TEGRA_GPIO(V, 3) 0>;
  1757. enable-active-high;
  1758. regulator-boot-on;
  1759. };
  1760. pp1800_cam: regulator@6 {
  1761. compatible = "regulator-fixed";
  1762. reg= <6>;
  1763. regulator-name = "PP1800_CAM";
  1764. regulator-min-microvolt = <1800000>;
  1765. regulator-max-microvolt = <1800000>;
  1766. gpio = <&gpio TEGRA_GPIO(K, 3) 0>;
  1767. enable-active-high;
  1768. };
  1769. usbc_vbus: regulator@7 {
  1770. compatible = "regulator-fixed";
  1771. reg = <7>;
  1772. regulator-name = "USBC_VBUS";
  1773. regulator-min-microvolt = <5000000>;
  1774. regulator-max-microvolt = <5000000>;
  1775. };
  1776. };
  1777. };