cpufeature.c 61 KB

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  1. /*
  2. * Contains CPU feature definitions
  3. *
  4. * Copyright (C) 2015 ARM Ltd.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "CPU features: " fmt
  19. #include <linux/bsearch.h>
  20. #include <linux/cpumask.h>
  21. #include <linux/sort.h>
  22. #include <linux/stop_machine.h>
  23. #include <linux/types.h>
  24. #include <linux/mm.h>
  25. #include <linux/cpu.h>
  26. #include <asm/cpu.h>
  27. #include <asm/cpufeature.h>
  28. #include <asm/cpu_ops.h>
  29. #include <asm/fpsimd.h>
  30. #include <asm/mmu_context.h>
  31. #include <asm/processor.h>
  32. #include <asm/sysreg.h>
  33. #include <asm/traps.h>
  34. #include <asm/virt.h>
  35. unsigned long elf_hwcap __read_mostly;
  36. EXPORT_SYMBOL_GPL(elf_hwcap);
  37. #ifdef CONFIG_COMPAT
  38. #define COMPAT_ELF_HWCAP_DEFAULT \
  39. (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  40. COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  41. COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
  42. COMPAT_HWCAP_LPAE)
  43. unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  44. unsigned int compat_elf_hwcap2 __read_mostly;
  45. #endif
  46. DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  47. EXPORT_SYMBOL(cpu_hwcaps);
  48. /*
  49. * Flag to indicate if we have computed the system wide
  50. * capabilities based on the boot time active CPUs. This
  51. * will be used to determine if a new booting CPU should
  52. * go through the verification process to make sure that it
  53. * supports the system capabilities, without using a hotplug
  54. * notifier.
  55. */
  56. static bool sys_caps_initialised;
  57. static inline void set_sys_caps_initialised(void)
  58. {
  59. sys_caps_initialised = true;
  60. }
  61. static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  62. {
  63. /* file-wide pr_fmt adds "CPU features: " prefix */
  64. pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  65. return 0;
  66. }
  67. static struct notifier_block cpu_hwcaps_notifier = {
  68. .notifier_call = dump_cpu_hwcaps
  69. };
  70. static int __init register_cpu_hwcaps_dumper(void)
  71. {
  72. atomic_notifier_chain_register(&panic_notifier_list,
  73. &cpu_hwcaps_notifier);
  74. return 0;
  75. }
  76. __initcall(register_cpu_hwcaps_dumper);
  77. DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  78. EXPORT_SYMBOL(cpu_hwcap_keys);
  79. #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  80. { \
  81. .sign = SIGNED, \
  82. .visible = VISIBLE, \
  83. .strict = STRICT, \
  84. .type = TYPE, \
  85. .shift = SHIFT, \
  86. .width = WIDTH, \
  87. .safe_val = SAFE_VAL, \
  88. }
  89. /* Define a feature with unsigned values */
  90. #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  91. __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  92. /* Define a feature with a signed value */
  93. #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  94. __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  95. #define ARM64_FTR_END \
  96. { \
  97. .width = 0, \
  98. }
  99. /* meta feature for alternatives */
  100. static bool __maybe_unused
  101. cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
  102. /*
  103. * NOTE: Any changes to the visibility of features should be kept in
  104. * sync with the documentation of the CPU feature register ABI.
  105. */
  106. static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
  107. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
  108. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
  109. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
  110. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
  111. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
  112. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
  113. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
  114. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
  115. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
  116. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
  117. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
  118. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
  119. ARM64_FTR_END,
  120. };
  121. static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
  122. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
  123. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
  124. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
  125. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
  126. ARM64_FTR_END,
  127. };
  128. static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
  129. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
  130. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
  131. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
  132. ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
  133. FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
  134. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
  135. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
  136. S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
  137. S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
  138. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
  139. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
  140. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
  141. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
  142. ARM64_FTR_END,
  143. };
  144. static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
  145. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
  146. ARM64_FTR_END,
  147. };
  148. static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
  149. /*
  150. * We already refuse to boot CPUs that don't support our configured
  151. * page size, so we can only detect mismatches for a page size other
  152. * than the one we're currently using. Unfortunately, SoCs like this
  153. * exist in the wild so, even though we don't like it, we'll have to go
  154. * along with it and treat them as non-strict.
  155. */
  156. S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
  157. S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
  158. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
  159. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
  160. /* Linux shouldn't care about secure memory */
  161. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
  162. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
  163. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
  164. /*
  165. * Differing PARange is fine as long as all peripherals and memory are mapped
  166. * within the minimum PARange of all CPUs
  167. */
  168. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
  169. ARM64_FTR_END,
  170. };
  171. static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
  172. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
  173. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
  174. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
  175. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
  176. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
  177. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
  178. ARM64_FTR_END,
  179. };
  180. static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
  181. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
  182. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
  183. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
  184. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
  185. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
  186. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
  187. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
  188. ARM64_FTR_END,
  189. };
  190. static const struct arm64_ftr_bits ftr_ctr[] = {
  191. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
  192. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
  193. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
  194. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
  195. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
  196. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
  197. /*
  198. * Linux can handle differing I-cache policies. Userspace JITs will
  199. * make use of *minLine.
  200. * If we have differing I-cache policies, report it as the weakest - VIPT.
  201. */
  202. ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
  203. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
  204. ARM64_FTR_END,
  205. };
  206. struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
  207. .name = "SYS_CTR_EL0",
  208. .ftr_bits = ftr_ctr
  209. };
  210. static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
  211. S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
  212. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
  213. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
  214. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
  215. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
  216. S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
  217. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
  218. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
  219. ARM64_FTR_END,
  220. };
  221. static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
  222. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
  223. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
  224. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
  225. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
  226. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
  227. /*
  228. * We can instantiate multiple PMU instances with different levels
  229. * of support.
  230. */
  231. S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
  232. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
  233. ARM64_FTR_END,
  234. };
  235. static const struct arm64_ftr_bits ftr_mvfr2[] = {
  236. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
  237. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
  238. ARM64_FTR_END,
  239. };
  240. static const struct arm64_ftr_bits ftr_dczid[] = {
  241. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
  242. ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
  243. ARM64_FTR_END,
  244. };
  245. static const struct arm64_ftr_bits ftr_id_isar5[] = {
  246. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
  247. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
  248. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
  249. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
  250. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
  251. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
  252. ARM64_FTR_END,
  253. };
  254. static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
  255. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
  256. ARM64_FTR_END,
  257. };
  258. static const struct arm64_ftr_bits ftr_id_pfr0[] = {
  259. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
  260. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
  261. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
  262. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
  263. ARM64_FTR_END,
  264. };
  265. static const struct arm64_ftr_bits ftr_id_dfr0[] = {
  266. /* [31:28] TraceFilt */
  267. S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
  268. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
  269. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
  270. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
  271. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
  272. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
  273. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
  274. ARM64_FTR_END,
  275. };
  276. static const struct arm64_ftr_bits ftr_zcr[] = {
  277. ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
  278. ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
  279. ARM64_FTR_END,
  280. };
  281. /*
  282. * Common ftr bits for a 32bit register with all hidden, strict
  283. * attributes, with 4bit feature fields and a default safe value of
  284. * 0. Covers the following 32bit registers:
  285. * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
  286. */
  287. static const struct arm64_ftr_bits ftr_generic_32bits[] = {
  288. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
  289. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
  290. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
  291. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
  292. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
  293. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
  294. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
  295. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
  296. ARM64_FTR_END,
  297. };
  298. /* Table for a single 32bit feature value */
  299. static const struct arm64_ftr_bits ftr_single32[] = {
  300. ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
  301. ARM64_FTR_END,
  302. };
  303. static const struct arm64_ftr_bits ftr_raz[] = {
  304. ARM64_FTR_END,
  305. };
  306. #define ARM64_FTR_REG(id, table) { \
  307. .sys_id = id, \
  308. .reg = &(struct arm64_ftr_reg){ \
  309. .name = #id, \
  310. .ftr_bits = &((table)[0]), \
  311. }}
  312. static const struct __ftr_reg_entry {
  313. u32 sys_id;
  314. struct arm64_ftr_reg *reg;
  315. } arm64_ftr_regs[] = {
  316. /* Op1 = 0, CRn = 0, CRm = 1 */
  317. ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
  318. ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
  319. ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
  320. ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
  321. ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
  322. ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
  323. ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
  324. /* Op1 = 0, CRn = 0, CRm = 2 */
  325. ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
  326. ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
  327. ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
  328. ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
  329. ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
  330. ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
  331. ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
  332. /* Op1 = 0, CRn = 0, CRm = 3 */
  333. ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
  334. ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
  335. ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
  336. /* Op1 = 0, CRn = 0, CRm = 4 */
  337. ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
  338. ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
  339. ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
  340. /* Op1 = 0, CRn = 0, CRm = 5 */
  341. ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
  342. ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
  343. /* Op1 = 0, CRn = 0, CRm = 6 */
  344. ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
  345. ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
  346. /* Op1 = 0, CRn = 0, CRm = 7 */
  347. ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
  348. ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
  349. ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
  350. /* Op1 = 0, CRn = 1, CRm = 2 */
  351. ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
  352. /* Op1 = 3, CRn = 0, CRm = 0 */
  353. { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
  354. ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
  355. /* Op1 = 3, CRn = 14, CRm = 0 */
  356. ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
  357. };
  358. static int search_cmp_ftr_reg(const void *id, const void *regp)
  359. {
  360. return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
  361. }
  362. /*
  363. * get_arm64_ftr_reg - Lookup a feature register entry using its
  364. * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
  365. * ascending order of sys_id , we use binary search to find a matching
  366. * entry.
  367. *
  368. * returns - Upon success, matching ftr_reg entry for id.
  369. * - NULL on failure. It is upto the caller to decide
  370. * the impact of a failure.
  371. */
  372. static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
  373. {
  374. const struct __ftr_reg_entry *ret;
  375. ret = bsearch((const void *)(unsigned long)sys_id,
  376. arm64_ftr_regs,
  377. ARRAY_SIZE(arm64_ftr_regs),
  378. sizeof(arm64_ftr_regs[0]),
  379. search_cmp_ftr_reg);
  380. if (ret)
  381. return ret->reg;
  382. return NULL;
  383. }
  384. static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
  385. s64 ftr_val)
  386. {
  387. u64 mask = arm64_ftr_mask(ftrp);
  388. reg &= ~mask;
  389. reg |= (ftr_val << ftrp->shift) & mask;
  390. return reg;
  391. }
  392. static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
  393. s64 cur)
  394. {
  395. s64 ret = 0;
  396. switch (ftrp->type) {
  397. case FTR_EXACT:
  398. ret = ftrp->safe_val;
  399. break;
  400. case FTR_LOWER_SAFE:
  401. ret = new < cur ? new : cur;
  402. break;
  403. case FTR_HIGHER_OR_ZERO_SAFE:
  404. if (!cur || !new)
  405. break;
  406. /* Fallthrough */
  407. case FTR_HIGHER_SAFE:
  408. ret = new > cur ? new : cur;
  409. break;
  410. default:
  411. BUG();
  412. }
  413. return ret;
  414. }
  415. static void __init sort_ftr_regs(void)
  416. {
  417. int i;
  418. /* Check that the array is sorted so that we can do the binary search */
  419. for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
  420. BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
  421. }
  422. /*
  423. * Initialise the CPU feature register from Boot CPU values.
  424. * Also initiliases the strict_mask for the register.
  425. * Any bits that are not covered by an arm64_ftr_bits entry are considered
  426. * RES0 for the system-wide value, and must strictly match.
  427. */
  428. static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
  429. {
  430. u64 val = 0;
  431. u64 strict_mask = ~0x0ULL;
  432. u64 user_mask = 0;
  433. u64 valid_mask = 0;
  434. const struct arm64_ftr_bits *ftrp;
  435. struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
  436. BUG_ON(!reg);
  437. for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
  438. u64 ftr_mask = arm64_ftr_mask(ftrp);
  439. s64 ftr_new = arm64_ftr_value(ftrp, new);
  440. val = arm64_ftr_set_value(ftrp, val, ftr_new);
  441. valid_mask |= ftr_mask;
  442. if (!ftrp->strict)
  443. strict_mask &= ~ftr_mask;
  444. if (ftrp->visible)
  445. user_mask |= ftr_mask;
  446. else
  447. reg->user_val = arm64_ftr_set_value(ftrp,
  448. reg->user_val,
  449. ftrp->safe_val);
  450. }
  451. val &= valid_mask;
  452. reg->sys_val = val;
  453. reg->strict_mask = strict_mask;
  454. reg->user_mask = user_mask;
  455. }
  456. extern const struct arm64_cpu_capabilities arm64_errata[];
  457. static void __init setup_boot_cpu_capabilities(void);
  458. void __init init_cpu_features(struct cpuinfo_arm64 *info)
  459. {
  460. /* Before we start using the tables, make sure it is sorted */
  461. sort_ftr_regs();
  462. init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
  463. init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
  464. init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
  465. init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
  466. init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
  467. init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
  468. init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
  469. init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
  470. init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
  471. init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
  472. init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
  473. init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
  474. init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
  475. if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
  476. init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
  477. init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
  478. init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
  479. init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
  480. init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
  481. init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
  482. init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
  483. init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
  484. init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
  485. init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
  486. init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
  487. init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
  488. init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
  489. init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
  490. init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
  491. init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
  492. }
  493. if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
  494. init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
  495. sve_init_vq_map();
  496. }
  497. /*
  498. * Detect and enable early CPU capabilities based on the boot CPU,
  499. * after we have initialised the CPU feature infrastructure.
  500. */
  501. setup_boot_cpu_capabilities();
  502. }
  503. static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
  504. {
  505. const struct arm64_ftr_bits *ftrp;
  506. for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
  507. s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
  508. s64 ftr_new = arm64_ftr_value(ftrp, new);
  509. if (ftr_cur == ftr_new)
  510. continue;
  511. /* Find a safe value */
  512. ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
  513. reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
  514. }
  515. }
  516. static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
  517. {
  518. struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
  519. BUG_ON(!regp);
  520. update_cpu_ftr_reg(regp, val);
  521. if ((boot & regp->strict_mask) == (val & regp->strict_mask))
  522. return 0;
  523. pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
  524. regp->name, boot, cpu, val);
  525. return 1;
  526. }
  527. /*
  528. * Update system wide CPU feature registers with the values from a
  529. * non-boot CPU. Also performs SANITY checks to make sure that there
  530. * aren't any insane variations from that of the boot CPU.
  531. */
  532. void update_cpu_features(int cpu,
  533. struct cpuinfo_arm64 *info,
  534. struct cpuinfo_arm64 *boot)
  535. {
  536. int taint = 0;
  537. /*
  538. * The kernel can handle differing I-cache policies, but otherwise
  539. * caches should look identical. Userspace JITs will make use of
  540. * *minLine.
  541. */
  542. taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
  543. info->reg_ctr, boot->reg_ctr);
  544. /*
  545. * Userspace may perform DC ZVA instructions. Mismatched block sizes
  546. * could result in too much or too little memory being zeroed if a
  547. * process is preempted and migrated between CPUs.
  548. */
  549. taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
  550. info->reg_dczid, boot->reg_dczid);
  551. /* If different, timekeeping will be broken (especially with KVM) */
  552. taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
  553. info->reg_cntfrq, boot->reg_cntfrq);
  554. /*
  555. * The kernel uses self-hosted debug features and expects CPUs to
  556. * support identical debug features. We presently need CTX_CMPs, WRPs,
  557. * and BRPs to be identical.
  558. * ID_AA64DFR1 is currently RES0.
  559. */
  560. taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
  561. info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
  562. taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
  563. info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
  564. /*
  565. * Even in big.LITTLE, processors should be identical instruction-set
  566. * wise.
  567. */
  568. taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
  569. info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
  570. taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
  571. info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
  572. /*
  573. * Differing PARange support is fine as long as all peripherals and
  574. * memory are mapped within the minimum PARange of all CPUs.
  575. * Linux should not care about secure memory.
  576. */
  577. taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
  578. info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
  579. taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
  580. info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
  581. taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
  582. info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
  583. taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
  584. info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
  585. taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
  586. info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
  587. taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
  588. info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
  589. /*
  590. * If we have AArch32, we care about 32-bit features for compat.
  591. * If the system doesn't support AArch32, don't update them.
  592. */
  593. if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
  594. id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
  595. taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
  596. info->reg_id_dfr0, boot->reg_id_dfr0);
  597. taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
  598. info->reg_id_isar0, boot->reg_id_isar0);
  599. taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
  600. info->reg_id_isar1, boot->reg_id_isar1);
  601. taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
  602. info->reg_id_isar2, boot->reg_id_isar2);
  603. taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
  604. info->reg_id_isar3, boot->reg_id_isar3);
  605. taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
  606. info->reg_id_isar4, boot->reg_id_isar4);
  607. taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
  608. info->reg_id_isar5, boot->reg_id_isar5);
  609. /*
  610. * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
  611. * ACTLR formats could differ across CPUs and therefore would have to
  612. * be trapped for virtualization anyway.
  613. */
  614. taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
  615. info->reg_id_mmfr0, boot->reg_id_mmfr0);
  616. taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
  617. info->reg_id_mmfr1, boot->reg_id_mmfr1);
  618. taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
  619. info->reg_id_mmfr2, boot->reg_id_mmfr2);
  620. taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
  621. info->reg_id_mmfr3, boot->reg_id_mmfr3);
  622. taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
  623. info->reg_id_pfr0, boot->reg_id_pfr0);
  624. taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
  625. info->reg_id_pfr1, boot->reg_id_pfr1);
  626. taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
  627. info->reg_mvfr0, boot->reg_mvfr0);
  628. taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
  629. info->reg_mvfr1, boot->reg_mvfr1);
  630. taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
  631. info->reg_mvfr2, boot->reg_mvfr2);
  632. }
  633. if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
  634. taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
  635. info->reg_zcr, boot->reg_zcr);
  636. /* Probe vector lengths, unless we already gave up on SVE */
  637. if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
  638. !sys_caps_initialised)
  639. sve_update_vq_map();
  640. }
  641. /*
  642. * Mismatched CPU features are a recipe for disaster. Don't even
  643. * pretend to support them.
  644. */
  645. if (taint) {
  646. pr_warn_once("Unsupported CPU feature variation detected.\n");
  647. add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
  648. }
  649. }
  650. u64 read_sanitised_ftr_reg(u32 id)
  651. {
  652. struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
  653. /* We shouldn't get a request for an unsupported register */
  654. BUG_ON(!regp);
  655. return regp->sys_val;
  656. }
  657. #define read_sysreg_case(r) \
  658. case r: return read_sysreg_s(r)
  659. /*
  660. * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
  661. * Read the system register on the current CPU
  662. */
  663. static u64 __read_sysreg_by_encoding(u32 sys_id)
  664. {
  665. switch (sys_id) {
  666. read_sysreg_case(SYS_ID_PFR0_EL1);
  667. read_sysreg_case(SYS_ID_PFR1_EL1);
  668. read_sysreg_case(SYS_ID_DFR0_EL1);
  669. read_sysreg_case(SYS_ID_MMFR0_EL1);
  670. read_sysreg_case(SYS_ID_MMFR1_EL1);
  671. read_sysreg_case(SYS_ID_MMFR2_EL1);
  672. read_sysreg_case(SYS_ID_MMFR3_EL1);
  673. read_sysreg_case(SYS_ID_ISAR0_EL1);
  674. read_sysreg_case(SYS_ID_ISAR1_EL1);
  675. read_sysreg_case(SYS_ID_ISAR2_EL1);
  676. read_sysreg_case(SYS_ID_ISAR3_EL1);
  677. read_sysreg_case(SYS_ID_ISAR4_EL1);
  678. read_sysreg_case(SYS_ID_ISAR5_EL1);
  679. read_sysreg_case(SYS_MVFR0_EL1);
  680. read_sysreg_case(SYS_MVFR1_EL1);
  681. read_sysreg_case(SYS_MVFR2_EL1);
  682. read_sysreg_case(SYS_ID_AA64PFR0_EL1);
  683. read_sysreg_case(SYS_ID_AA64PFR1_EL1);
  684. read_sysreg_case(SYS_ID_AA64DFR0_EL1);
  685. read_sysreg_case(SYS_ID_AA64DFR1_EL1);
  686. read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
  687. read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
  688. read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
  689. read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
  690. read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
  691. read_sysreg_case(SYS_CNTFRQ_EL0);
  692. read_sysreg_case(SYS_CTR_EL0);
  693. read_sysreg_case(SYS_DCZID_EL0);
  694. default:
  695. BUG();
  696. return 0;
  697. }
  698. }
  699. #include <linux/irqchip/arm-gic-v3.h>
  700. static bool
  701. feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
  702. {
  703. int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
  704. return val >= entry->min_field_value;
  705. }
  706. static bool
  707. has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
  708. {
  709. u64 val;
  710. WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
  711. if (scope == SCOPE_SYSTEM)
  712. val = read_sanitised_ftr_reg(entry->sys_reg);
  713. else
  714. val = __read_sysreg_by_encoding(entry->sys_reg);
  715. return feature_matches(val, entry);
  716. }
  717. static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
  718. {
  719. bool has_sre;
  720. if (!has_cpuid_feature(entry, scope))
  721. return false;
  722. has_sre = gic_enable_sre();
  723. if (!has_sre)
  724. pr_warn_once("%s present but disabled by higher exception level\n",
  725. entry->desc);
  726. return has_sre;
  727. }
  728. static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
  729. {
  730. u32 midr = read_cpuid_id();
  731. /* Cavium ThunderX pass 1.x and 2.x */
  732. return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
  733. MIDR_CPU_VAR_REV(0, 0),
  734. MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
  735. }
  736. static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
  737. {
  738. u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
  739. return cpuid_feature_extract_signed_field(pfr0,
  740. ID_AA64PFR0_FP_SHIFT) < 0;
  741. }
  742. static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
  743. int scope)
  744. {
  745. u64 ctr;
  746. if (scope == SCOPE_SYSTEM)
  747. ctr = arm64_ftr_reg_ctrel0.sys_val;
  748. else
  749. ctr = read_cpuid_cachetype();
  750. return ctr & BIT(CTR_IDC_SHIFT);
  751. }
  752. static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
  753. int scope)
  754. {
  755. u64 ctr;
  756. if (scope == SCOPE_SYSTEM)
  757. ctr = arm64_ftr_reg_ctrel0.sys_val;
  758. else
  759. ctr = read_cpuid_cachetype();
  760. return ctr & BIT(CTR_DIC_SHIFT);
  761. }
  762. static bool __meltdown_safe = true;
  763. static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
  764. static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
  765. int scope)
  766. {
  767. /* List of CPUs that are not vulnerable and don't need KPTI */
  768. static const struct midr_range kpti_safe_list[] = {
  769. MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
  770. MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
  771. MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
  772. MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
  773. MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
  774. MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
  775. MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
  776. MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
  777. MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
  778. { /* sentinel */ }
  779. };
  780. char const *str = "kpti command line option";
  781. bool meltdown_safe;
  782. meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
  783. /* Defer to CPU feature registers */
  784. if (has_cpuid_feature(entry, scope))
  785. meltdown_safe = true;
  786. if (!meltdown_safe)
  787. __meltdown_safe = false;
  788. /*
  789. * For reasons that aren't entirely clear, enabling KPTI on Cavium
  790. * ThunderX leads to apparent I-cache corruption of kernel text, which
  791. * ends as well as you might imagine. Don't even try.
  792. */
  793. if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
  794. str = "ARM64_WORKAROUND_CAVIUM_27456";
  795. __kpti_forced = -1;
  796. }
  797. /* Useful for KASLR robustness */
  798. if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
  799. if (!__kpti_forced) {
  800. str = "KASLR";
  801. __kpti_forced = 1;
  802. }
  803. }
  804. if (cpu_mitigations_off() && !__kpti_forced) {
  805. str = "mitigations=off";
  806. __kpti_forced = -1;
  807. }
  808. if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
  809. pr_info_once("kernel page table isolation disabled by kernel configuration\n");
  810. return false;
  811. }
  812. /* Forced? */
  813. if (__kpti_forced) {
  814. pr_info_once("kernel page table isolation forced %s by %s\n",
  815. __kpti_forced > 0 ? "ON" : "OFF", str);
  816. return __kpti_forced > 0;
  817. }
  818. return !meltdown_safe;
  819. }
  820. #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
  821. static void
  822. kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
  823. {
  824. typedef void (kpti_remap_fn)(int, int, phys_addr_t);
  825. extern kpti_remap_fn idmap_kpti_install_ng_mappings;
  826. kpti_remap_fn *remap_fn;
  827. static bool kpti_applied = false;
  828. int cpu = smp_processor_id();
  829. if (kpti_applied)
  830. return;
  831. remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
  832. cpu_install_idmap();
  833. remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
  834. cpu_uninstall_idmap();
  835. if (!cpu)
  836. kpti_applied = true;
  837. return;
  838. }
  839. #else
  840. static void
  841. kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
  842. {
  843. }
  844. #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
  845. static int __init parse_kpti(char *str)
  846. {
  847. bool enabled;
  848. int ret = strtobool(str, &enabled);
  849. if (ret)
  850. return ret;
  851. __kpti_forced = enabled ? 1 : -1;
  852. return 0;
  853. }
  854. early_param("kpti", parse_kpti);
  855. #ifdef CONFIG_ARM64_HW_AFDBM
  856. static inline void __cpu_enable_hw_dbm(void)
  857. {
  858. u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
  859. write_sysreg(tcr, tcr_el1);
  860. isb();
  861. }
  862. static bool cpu_has_broken_dbm(void)
  863. {
  864. /* List of CPUs which have broken DBM support. */
  865. static const struct midr_range cpus[] = {
  866. #ifdef CONFIG_ARM64_ERRATUM_1024718
  867. MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
  868. #endif
  869. {},
  870. };
  871. return is_midr_in_range_list(read_cpuid_id(), cpus);
  872. }
  873. static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
  874. {
  875. return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
  876. !cpu_has_broken_dbm();
  877. }
  878. static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
  879. {
  880. if (cpu_can_use_dbm(cap))
  881. __cpu_enable_hw_dbm();
  882. }
  883. static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
  884. int __unused)
  885. {
  886. static bool detected = false;
  887. /*
  888. * DBM is a non-conflicting feature. i.e, the kernel can safely
  889. * run a mix of CPUs with and without the feature. So, we
  890. * unconditionally enable the capability to allow any late CPU
  891. * to use the feature. We only enable the control bits on the
  892. * CPU, if it actually supports.
  893. *
  894. * We have to make sure we print the "feature" detection only
  895. * when at least one CPU actually uses it. So check if this CPU
  896. * can actually use it and print the message exactly once.
  897. *
  898. * This is safe as all CPUs (including secondary CPUs - due to the
  899. * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
  900. * goes through the "matches" check exactly once. Also if a CPU
  901. * matches the criteria, it is guaranteed that the CPU will turn
  902. * the DBM on, as the capability is unconditionally enabled.
  903. */
  904. if (!detected && cpu_can_use_dbm(cap)) {
  905. detected = true;
  906. pr_info("detected: Hardware dirty bit management\n");
  907. }
  908. return true;
  909. }
  910. #endif
  911. #ifdef CONFIG_ARM64_VHE
  912. static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
  913. {
  914. return is_kernel_in_hyp_mode();
  915. }
  916. static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
  917. {
  918. /*
  919. * Copy register values that aren't redirected by hardware.
  920. *
  921. * Before code patching, we only set tpidr_el1, all CPUs need to copy
  922. * this value to tpidr_el2 before we patch the code. Once we've done
  923. * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
  924. * do anything here.
  925. */
  926. if (!alternatives_applied)
  927. write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
  928. }
  929. #endif
  930. static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
  931. {
  932. u64 val = read_sysreg_s(SYS_CLIDR_EL1);
  933. /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
  934. WARN_ON(val & (7 << 27 | 7 << 21));
  935. }
  936. #ifdef CONFIG_ARM64_SSBD
  937. static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
  938. {
  939. if (user_mode(regs))
  940. return 1;
  941. if (instr & BIT(CRm_shift))
  942. regs->pstate |= PSR_SSBS_BIT;
  943. else
  944. regs->pstate &= ~PSR_SSBS_BIT;
  945. arm64_skip_faulting_instruction(regs, 4);
  946. return 0;
  947. }
  948. static struct undef_hook ssbs_emulation_hook = {
  949. .instr_mask = ~(1U << CRm_shift),
  950. .instr_val = 0xd500001f | REG_PSTATE_SSBS_IMM,
  951. .fn = ssbs_emulation_handler,
  952. };
  953. static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
  954. {
  955. static bool undef_hook_registered = false;
  956. static DEFINE_SPINLOCK(hook_lock);
  957. spin_lock(&hook_lock);
  958. if (!undef_hook_registered) {
  959. register_undef_hook(&ssbs_emulation_hook);
  960. undef_hook_registered = true;
  961. }
  962. spin_unlock(&hook_lock);
  963. if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
  964. sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
  965. arm64_set_ssbd_mitigation(false);
  966. } else {
  967. arm64_set_ssbd_mitigation(true);
  968. }
  969. }
  970. #endif /* CONFIG_ARM64_SSBD */
  971. static const struct arm64_cpu_capabilities arm64_features[] = {
  972. {
  973. .desc = "GIC system register CPU interface",
  974. .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
  975. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  976. .matches = has_useable_gicv3_cpuif,
  977. .sys_reg = SYS_ID_AA64PFR0_EL1,
  978. .field_pos = ID_AA64PFR0_GIC_SHIFT,
  979. .sign = FTR_UNSIGNED,
  980. .min_field_value = 1,
  981. },
  982. #ifdef CONFIG_ARM64_PAN
  983. {
  984. .desc = "Privileged Access Never",
  985. .capability = ARM64_HAS_PAN,
  986. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  987. .matches = has_cpuid_feature,
  988. .sys_reg = SYS_ID_AA64MMFR1_EL1,
  989. .field_pos = ID_AA64MMFR1_PAN_SHIFT,
  990. .sign = FTR_UNSIGNED,
  991. .min_field_value = 1,
  992. .cpu_enable = cpu_enable_pan,
  993. },
  994. #endif /* CONFIG_ARM64_PAN */
  995. #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
  996. {
  997. .desc = "LSE atomic instructions",
  998. .capability = ARM64_HAS_LSE_ATOMICS,
  999. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  1000. .matches = has_cpuid_feature,
  1001. .sys_reg = SYS_ID_AA64ISAR0_EL1,
  1002. .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
  1003. .sign = FTR_UNSIGNED,
  1004. .min_field_value = 2,
  1005. },
  1006. #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
  1007. {
  1008. .desc = "Software prefetching using PRFM",
  1009. .capability = ARM64_HAS_NO_HW_PREFETCH,
  1010. .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
  1011. .matches = has_no_hw_prefetch,
  1012. },
  1013. #ifdef CONFIG_ARM64_UAO
  1014. {
  1015. .desc = "User Access Override",
  1016. .capability = ARM64_HAS_UAO,
  1017. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  1018. .matches = has_cpuid_feature,
  1019. .sys_reg = SYS_ID_AA64MMFR2_EL1,
  1020. .field_pos = ID_AA64MMFR2_UAO_SHIFT,
  1021. .min_field_value = 1,
  1022. /*
  1023. * We rely on stop_machine() calling uao_thread_switch() to set
  1024. * UAO immediately after patching.
  1025. */
  1026. },
  1027. #endif /* CONFIG_ARM64_UAO */
  1028. #ifdef CONFIG_ARM64_PAN
  1029. {
  1030. .capability = ARM64_ALT_PAN_NOT_UAO,
  1031. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  1032. .matches = cpufeature_pan_not_uao,
  1033. },
  1034. #endif /* CONFIG_ARM64_PAN */
  1035. #ifdef CONFIG_ARM64_VHE
  1036. {
  1037. .desc = "Virtualization Host Extensions",
  1038. .capability = ARM64_HAS_VIRT_HOST_EXTN,
  1039. .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
  1040. .matches = runs_at_el2,
  1041. .cpu_enable = cpu_copy_el2regs,
  1042. },
  1043. #endif /* CONFIG_ARM64_VHE */
  1044. {
  1045. .desc = "32-bit EL0 Support",
  1046. .capability = ARM64_HAS_32BIT_EL0,
  1047. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  1048. .matches = has_cpuid_feature,
  1049. .sys_reg = SYS_ID_AA64PFR0_EL1,
  1050. .sign = FTR_UNSIGNED,
  1051. .field_pos = ID_AA64PFR0_EL0_SHIFT,
  1052. .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
  1053. },
  1054. {
  1055. .desc = "Kernel page table isolation (KPTI)",
  1056. .capability = ARM64_UNMAP_KERNEL_AT_EL0,
  1057. .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
  1058. /*
  1059. * The ID feature fields below are used to indicate that
  1060. * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
  1061. * more details.
  1062. */
  1063. .sys_reg = SYS_ID_AA64PFR0_EL1,
  1064. .field_pos = ID_AA64PFR0_CSV3_SHIFT,
  1065. .min_field_value = 1,
  1066. .matches = unmap_kernel_at_el0,
  1067. .cpu_enable = kpti_install_ng_mappings,
  1068. },
  1069. {
  1070. /* FP/SIMD is not implemented */
  1071. .capability = ARM64_HAS_NO_FPSIMD,
  1072. .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
  1073. .min_field_value = 0,
  1074. .matches = has_no_fpsimd,
  1075. },
  1076. #ifdef CONFIG_ARM64_PMEM
  1077. {
  1078. .desc = "Data cache clean to Point of Persistence",
  1079. .capability = ARM64_HAS_DCPOP,
  1080. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  1081. .matches = has_cpuid_feature,
  1082. .sys_reg = SYS_ID_AA64ISAR1_EL1,
  1083. .field_pos = ID_AA64ISAR1_DPB_SHIFT,
  1084. .min_field_value = 1,
  1085. },
  1086. #endif
  1087. #ifdef CONFIG_ARM64_SVE
  1088. {
  1089. .desc = "Scalable Vector Extension",
  1090. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  1091. .capability = ARM64_SVE,
  1092. .sys_reg = SYS_ID_AA64PFR0_EL1,
  1093. .sign = FTR_UNSIGNED,
  1094. .field_pos = ID_AA64PFR0_SVE_SHIFT,
  1095. .min_field_value = ID_AA64PFR0_SVE,
  1096. .matches = has_cpuid_feature,
  1097. .cpu_enable = sve_kernel_enable,
  1098. },
  1099. #endif /* CONFIG_ARM64_SVE */
  1100. #ifdef CONFIG_ARM64_RAS_EXTN
  1101. {
  1102. .desc = "RAS Extension Support",
  1103. .capability = ARM64_HAS_RAS_EXTN,
  1104. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  1105. .matches = has_cpuid_feature,
  1106. .sys_reg = SYS_ID_AA64PFR0_EL1,
  1107. .sign = FTR_UNSIGNED,
  1108. .field_pos = ID_AA64PFR0_RAS_SHIFT,
  1109. .min_field_value = ID_AA64PFR0_RAS_V1,
  1110. .cpu_enable = cpu_clear_disr,
  1111. },
  1112. #endif /* CONFIG_ARM64_RAS_EXTN */
  1113. {
  1114. .desc = "Data cache clean to the PoU not required for I/D coherence",
  1115. .capability = ARM64_HAS_CACHE_IDC,
  1116. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  1117. .matches = has_cache_idc,
  1118. },
  1119. {
  1120. .desc = "Instruction cache invalidation not required for I/D coherence",
  1121. .capability = ARM64_HAS_CACHE_DIC,
  1122. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  1123. .matches = has_cache_dic,
  1124. },
  1125. {
  1126. .desc = "Stage-2 Force Write-Back",
  1127. .type = ARM64_CPUCAP_SYSTEM_FEATURE,
  1128. .capability = ARM64_HAS_STAGE2_FWB,
  1129. .sys_reg = SYS_ID_AA64MMFR2_EL1,
  1130. .sign = FTR_UNSIGNED,
  1131. .field_pos = ID_AA64MMFR2_FWB_SHIFT,
  1132. .min_field_value = 1,
  1133. .matches = has_cpuid_feature,
  1134. .cpu_enable = cpu_has_fwb,
  1135. },
  1136. #ifdef CONFIG_ARM64_HW_AFDBM
  1137. {
  1138. /*
  1139. * Since we turn this on always, we don't want the user to
  1140. * think that the feature is available when it may not be.
  1141. * So hide the description.
  1142. *
  1143. * .desc = "Hardware pagetable Dirty Bit Management",
  1144. *
  1145. */
  1146. .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
  1147. .capability = ARM64_HW_DBM,
  1148. .sys_reg = SYS_ID_AA64MMFR1_EL1,
  1149. .sign = FTR_UNSIGNED,
  1150. .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
  1151. .min_field_value = 2,
  1152. .matches = has_hw_dbm,
  1153. .cpu_enable = cpu_enable_hw_dbm,
  1154. },
  1155. #endif
  1156. #ifdef CONFIG_ARM64_SSBD
  1157. {
  1158. .desc = "Speculative Store Bypassing Safe (SSBS)",
  1159. .capability = ARM64_SSBS,
  1160. .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
  1161. .matches = has_cpuid_feature,
  1162. .sys_reg = SYS_ID_AA64PFR1_EL1,
  1163. .field_pos = ID_AA64PFR1_SSBS_SHIFT,
  1164. .sign = FTR_UNSIGNED,
  1165. .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
  1166. .cpu_enable = cpu_enable_ssbs,
  1167. },
  1168. #endif
  1169. {},
  1170. };
  1171. #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
  1172. .matches = has_cpuid_feature, \
  1173. .sys_reg = reg, \
  1174. .field_pos = field, \
  1175. .sign = s, \
  1176. .min_field_value = min_value, \
  1177. #define __HWCAP_CAP(name, cap_type, cap) \
  1178. .desc = name, \
  1179. .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
  1180. .hwcap_type = cap_type, \
  1181. .hwcap = cap, \
  1182. #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
  1183. { \
  1184. __HWCAP_CAP(#cap, cap_type, cap) \
  1185. HWCAP_CPUID_MATCH(reg, field, s, min_value) \
  1186. }
  1187. #define HWCAP_CAP_MATCH(match, cap_type, cap) \
  1188. { \
  1189. __HWCAP_CAP(#cap, cap_type, cap) \
  1190. .matches = match, \
  1191. }
  1192. static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
  1193. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
  1194. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
  1195. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
  1196. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
  1197. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
  1198. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
  1199. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
  1200. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
  1201. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
  1202. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
  1203. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
  1204. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
  1205. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
  1206. HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
  1207. HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
  1208. HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
  1209. HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
  1210. HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
  1211. HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
  1212. HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
  1213. HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
  1214. HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
  1215. HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
  1216. HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
  1217. HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
  1218. #ifdef CONFIG_ARM64_SVE
  1219. HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
  1220. #endif
  1221. HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
  1222. {},
  1223. };
  1224. #ifdef CONFIG_COMPAT
  1225. static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
  1226. {
  1227. /*
  1228. * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
  1229. * in line with that of arm32 as in vfp_init(). We make sure that the
  1230. * check is future proof, by making sure value is non-zero.
  1231. */
  1232. u32 mvfr1;
  1233. WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
  1234. if (scope == SCOPE_SYSTEM)
  1235. mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
  1236. else
  1237. mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
  1238. return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
  1239. cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
  1240. cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
  1241. }
  1242. #endif
  1243. static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
  1244. #ifdef CONFIG_COMPAT
  1245. HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
  1246. HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
  1247. /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
  1248. HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
  1249. HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
  1250. HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
  1251. HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
  1252. HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
  1253. HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
  1254. HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
  1255. #endif
  1256. {},
  1257. };
  1258. static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
  1259. {
  1260. switch (cap->hwcap_type) {
  1261. case CAP_HWCAP:
  1262. elf_hwcap |= cap->hwcap;
  1263. break;
  1264. #ifdef CONFIG_COMPAT
  1265. case CAP_COMPAT_HWCAP:
  1266. compat_elf_hwcap |= (u32)cap->hwcap;
  1267. break;
  1268. case CAP_COMPAT_HWCAP2:
  1269. compat_elf_hwcap2 |= (u32)cap->hwcap;
  1270. break;
  1271. #endif
  1272. default:
  1273. WARN_ON(1);
  1274. break;
  1275. }
  1276. }
  1277. /* Check if we have a particular HWCAP enabled */
  1278. static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
  1279. {
  1280. bool rc;
  1281. switch (cap->hwcap_type) {
  1282. case CAP_HWCAP:
  1283. rc = (elf_hwcap & cap->hwcap) != 0;
  1284. break;
  1285. #ifdef CONFIG_COMPAT
  1286. case CAP_COMPAT_HWCAP:
  1287. rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
  1288. break;
  1289. case CAP_COMPAT_HWCAP2:
  1290. rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
  1291. break;
  1292. #endif
  1293. default:
  1294. WARN_ON(1);
  1295. rc = false;
  1296. }
  1297. return rc;
  1298. }
  1299. static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
  1300. {
  1301. /* We support emulation of accesses to CPU ID feature registers */
  1302. elf_hwcap |= HWCAP_CPUID;
  1303. for (; hwcaps->matches; hwcaps++)
  1304. if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
  1305. cap_set_elf_hwcap(hwcaps);
  1306. }
  1307. /*
  1308. * Check if the current CPU has a given feature capability.
  1309. * Should be called from non-preemptible context.
  1310. */
  1311. static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
  1312. unsigned int cap)
  1313. {
  1314. const struct arm64_cpu_capabilities *caps;
  1315. if (WARN_ON(preemptible()))
  1316. return false;
  1317. for (caps = cap_array; caps->matches; caps++)
  1318. if (caps->capability == cap)
  1319. return caps->matches(caps, SCOPE_LOCAL_CPU);
  1320. return false;
  1321. }
  1322. static void __update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
  1323. u16 scope_mask, const char *info)
  1324. {
  1325. scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
  1326. for (; caps->matches; caps++) {
  1327. if (!(caps->type & scope_mask) ||
  1328. !caps->matches(caps, cpucap_default_scope(caps)))
  1329. continue;
  1330. if (!cpus_have_cap(caps->capability) && caps->desc)
  1331. pr_info("%s %s\n", info, caps->desc);
  1332. cpus_set_cap(caps->capability);
  1333. }
  1334. }
  1335. static void update_cpu_capabilities(u16 scope_mask)
  1336. {
  1337. __update_cpu_capabilities(arm64_errata, scope_mask,
  1338. "enabling workaround for");
  1339. __update_cpu_capabilities(arm64_features, scope_mask, "detected:");
  1340. }
  1341. static int __enable_cpu_capability(void *arg)
  1342. {
  1343. const struct arm64_cpu_capabilities *cap = arg;
  1344. cap->cpu_enable(cap);
  1345. return 0;
  1346. }
  1347. /*
  1348. * Run through the enabled capabilities and enable() it on all active
  1349. * CPUs
  1350. */
  1351. static void __init
  1352. __enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
  1353. u16 scope_mask)
  1354. {
  1355. scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
  1356. for (; caps->matches; caps++) {
  1357. unsigned int num = caps->capability;
  1358. if (!(caps->type & scope_mask) || !cpus_have_cap(num))
  1359. continue;
  1360. /* Ensure cpus_have_const_cap(num) works */
  1361. static_branch_enable(&cpu_hwcap_keys[num]);
  1362. if (caps->cpu_enable) {
  1363. /*
  1364. * Capabilities with SCOPE_BOOT_CPU scope are finalised
  1365. * before any secondary CPU boots. Thus, each secondary
  1366. * will enable the capability as appropriate via
  1367. * check_local_cpu_capabilities(). The only exception is
  1368. * the boot CPU, for which the capability must be
  1369. * enabled here. This approach avoids costly
  1370. * stop_machine() calls for this case.
  1371. *
  1372. * Otherwise, use stop_machine() as it schedules the
  1373. * work allowing us to modify PSTATE, instead of
  1374. * on_each_cpu() which uses an IPI, giving us a PSTATE
  1375. * that disappears when we return.
  1376. */
  1377. if (scope_mask & SCOPE_BOOT_CPU)
  1378. caps->cpu_enable(caps);
  1379. else
  1380. stop_machine(__enable_cpu_capability,
  1381. (void *)caps, cpu_online_mask);
  1382. }
  1383. }
  1384. }
  1385. static void __init enable_cpu_capabilities(u16 scope_mask)
  1386. {
  1387. __enable_cpu_capabilities(arm64_errata, scope_mask);
  1388. __enable_cpu_capabilities(arm64_features, scope_mask);
  1389. }
  1390. /*
  1391. * Run through the list of capabilities to check for conflicts.
  1392. * If the system has already detected a capability, take necessary
  1393. * action on this CPU.
  1394. *
  1395. * Returns "false" on conflicts.
  1396. */
  1397. static bool
  1398. __verify_local_cpu_caps(const struct arm64_cpu_capabilities *caps,
  1399. u16 scope_mask)
  1400. {
  1401. bool cpu_has_cap, system_has_cap;
  1402. scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
  1403. for (; caps->matches; caps++) {
  1404. if (!(caps->type & scope_mask))
  1405. continue;
  1406. cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
  1407. system_has_cap = cpus_have_cap(caps->capability);
  1408. if (system_has_cap) {
  1409. /*
  1410. * Check if the new CPU misses an advertised feature,
  1411. * which is not safe to miss.
  1412. */
  1413. if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
  1414. break;
  1415. /*
  1416. * We have to issue cpu_enable() irrespective of
  1417. * whether the CPU has it or not, as it is enabeld
  1418. * system wide. It is upto the call back to take
  1419. * appropriate action on this CPU.
  1420. */
  1421. if (caps->cpu_enable)
  1422. caps->cpu_enable(caps);
  1423. } else {
  1424. /*
  1425. * Check if the CPU has this capability if it isn't
  1426. * safe to have when the system doesn't.
  1427. */
  1428. if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
  1429. break;
  1430. }
  1431. }
  1432. if (caps->matches) {
  1433. pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
  1434. smp_processor_id(), caps->capability,
  1435. caps->desc, system_has_cap, cpu_has_cap);
  1436. return false;
  1437. }
  1438. return true;
  1439. }
  1440. static bool verify_local_cpu_caps(u16 scope_mask)
  1441. {
  1442. return __verify_local_cpu_caps(arm64_errata, scope_mask) &&
  1443. __verify_local_cpu_caps(arm64_features, scope_mask);
  1444. }
  1445. /*
  1446. * Check for CPU features that are used in early boot
  1447. * based on the Boot CPU value.
  1448. */
  1449. static void check_early_cpu_features(void)
  1450. {
  1451. verify_cpu_asid_bits();
  1452. /*
  1453. * Early features are used by the kernel already. If there
  1454. * is a conflict, we cannot proceed further.
  1455. */
  1456. if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
  1457. cpu_panic_kernel();
  1458. }
  1459. static void
  1460. verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
  1461. {
  1462. for (; caps->matches; caps++)
  1463. if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
  1464. pr_crit("CPU%d: missing HWCAP: %s\n",
  1465. smp_processor_id(), caps->desc);
  1466. cpu_die_early();
  1467. }
  1468. }
  1469. static void verify_sve_features(void)
  1470. {
  1471. u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
  1472. u64 zcr = read_zcr_features();
  1473. unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
  1474. unsigned int len = zcr & ZCR_ELx_LEN_MASK;
  1475. if (len < safe_len || sve_verify_vq_map()) {
  1476. pr_crit("CPU%d: SVE: required vector length(s) missing\n",
  1477. smp_processor_id());
  1478. cpu_die_early();
  1479. }
  1480. /* Add checks on other ZCR bits here if necessary */
  1481. }
  1482. /*
  1483. * Run through the enabled system capabilities and enable() it on this CPU.
  1484. * The capabilities were decided based on the available CPUs at the boot time.
  1485. * Any new CPU should match the system wide status of the capability. If the
  1486. * new CPU doesn't have a capability which the system now has enabled, we
  1487. * cannot do anything to fix it up and could cause unexpected failures. So
  1488. * we park the CPU.
  1489. */
  1490. static void verify_local_cpu_capabilities(void)
  1491. {
  1492. /*
  1493. * The capabilities with SCOPE_BOOT_CPU are checked from
  1494. * check_early_cpu_features(), as they need to be verified
  1495. * on all secondary CPUs.
  1496. */
  1497. if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
  1498. cpu_die_early();
  1499. verify_local_elf_hwcaps(arm64_elf_hwcaps);
  1500. if (system_supports_32bit_el0())
  1501. verify_local_elf_hwcaps(compat_elf_hwcaps);
  1502. if (system_supports_sve())
  1503. verify_sve_features();
  1504. }
  1505. void check_local_cpu_capabilities(void)
  1506. {
  1507. /*
  1508. * All secondary CPUs should conform to the early CPU features
  1509. * in use by the kernel based on boot CPU.
  1510. */
  1511. check_early_cpu_features();
  1512. /*
  1513. * If we haven't finalised the system capabilities, this CPU gets
  1514. * a chance to update the errata work arounds and local features.
  1515. * Otherwise, this CPU should verify that it has all the system
  1516. * advertised capabilities.
  1517. */
  1518. if (!sys_caps_initialised)
  1519. update_cpu_capabilities(SCOPE_LOCAL_CPU);
  1520. else
  1521. verify_local_cpu_capabilities();
  1522. }
  1523. static void __init setup_boot_cpu_capabilities(void)
  1524. {
  1525. /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
  1526. update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
  1527. /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
  1528. enable_cpu_capabilities(SCOPE_BOOT_CPU);
  1529. }
  1530. DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
  1531. EXPORT_SYMBOL(arm64_const_caps_ready);
  1532. static void __init mark_const_caps_ready(void)
  1533. {
  1534. static_branch_enable(&arm64_const_caps_ready);
  1535. }
  1536. extern const struct arm64_cpu_capabilities arm64_errata[];
  1537. bool this_cpu_has_cap(unsigned int cap)
  1538. {
  1539. return (__this_cpu_has_cap(arm64_features, cap) ||
  1540. __this_cpu_has_cap(arm64_errata, cap));
  1541. }
  1542. static void __init setup_system_capabilities(void)
  1543. {
  1544. /*
  1545. * We have finalised the system-wide safe feature
  1546. * registers, finalise the capabilities that depend
  1547. * on it. Also enable all the available capabilities,
  1548. * that are not enabled already.
  1549. */
  1550. update_cpu_capabilities(SCOPE_SYSTEM);
  1551. enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
  1552. }
  1553. void __init setup_cpu_features(void)
  1554. {
  1555. u32 cwg;
  1556. setup_system_capabilities();
  1557. mark_const_caps_ready();
  1558. setup_elf_hwcaps(arm64_elf_hwcaps);
  1559. if (system_supports_32bit_el0())
  1560. setup_elf_hwcaps(compat_elf_hwcaps);
  1561. if (system_uses_ttbr0_pan())
  1562. pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
  1563. sve_setup();
  1564. minsigstksz_setup();
  1565. /* Advertise that we have computed the system capabilities */
  1566. set_sys_caps_initialised();
  1567. /*
  1568. * Check for sane CTR_EL0.CWG value.
  1569. */
  1570. cwg = cache_type_cwg();
  1571. if (!cwg)
  1572. pr_warn("No Cache Writeback Granule information, assuming %d\n",
  1573. ARCH_DMA_MINALIGN);
  1574. }
  1575. static bool __maybe_unused
  1576. cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
  1577. {
  1578. return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
  1579. }
  1580. /*
  1581. * We emulate only the following system register space.
  1582. * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
  1583. * See Table C5-6 System instruction encodings for System register accesses,
  1584. * ARMv8 ARM(ARM DDI 0487A.f) for more details.
  1585. */
  1586. static inline bool __attribute_const__ is_emulated(u32 id)
  1587. {
  1588. return (sys_reg_Op0(id) == 0x3 &&
  1589. sys_reg_CRn(id) == 0x0 &&
  1590. sys_reg_Op1(id) == 0x0 &&
  1591. (sys_reg_CRm(id) == 0 ||
  1592. ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
  1593. }
  1594. /*
  1595. * With CRm == 0, reg should be one of :
  1596. * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
  1597. */
  1598. static inline int emulate_id_reg(u32 id, u64 *valp)
  1599. {
  1600. switch (id) {
  1601. case SYS_MIDR_EL1:
  1602. *valp = read_cpuid_id();
  1603. break;
  1604. case SYS_MPIDR_EL1:
  1605. *valp = SYS_MPIDR_SAFE_VAL;
  1606. break;
  1607. case SYS_REVIDR_EL1:
  1608. /* IMPLEMENTATION DEFINED values are emulated with 0 */
  1609. *valp = 0;
  1610. break;
  1611. default:
  1612. return -EINVAL;
  1613. }
  1614. return 0;
  1615. }
  1616. static int emulate_sys_reg(u32 id, u64 *valp)
  1617. {
  1618. struct arm64_ftr_reg *regp;
  1619. if (!is_emulated(id))
  1620. return -EINVAL;
  1621. if (sys_reg_CRm(id) == 0)
  1622. return emulate_id_reg(id, valp);
  1623. regp = get_arm64_ftr_reg(id);
  1624. if (regp)
  1625. *valp = arm64_ftr_reg_user_value(regp);
  1626. else
  1627. /*
  1628. * The untracked registers are either IMPLEMENTATION DEFINED
  1629. * (e.g, ID_AFR0_EL1) or reserved RAZ.
  1630. */
  1631. *valp = 0;
  1632. return 0;
  1633. }
  1634. static int emulate_mrs(struct pt_regs *regs, u32 insn)
  1635. {
  1636. int rc;
  1637. u32 sys_reg, dst;
  1638. u64 val;
  1639. /*
  1640. * sys_reg values are defined as used in mrs/msr instruction.
  1641. * shift the imm value to get the encoding.
  1642. */
  1643. sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
  1644. rc = emulate_sys_reg(sys_reg, &val);
  1645. if (!rc) {
  1646. dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
  1647. pt_regs_write_reg(regs, dst, val);
  1648. arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
  1649. }
  1650. return rc;
  1651. }
  1652. static struct undef_hook mrs_hook = {
  1653. .instr_mask = 0xfff00000,
  1654. .instr_val = 0xd5300000,
  1655. .pstate_mask = PSR_AA32_MODE_MASK,
  1656. .pstate_val = PSR_MODE_EL0t,
  1657. .fn = emulate_mrs,
  1658. };
  1659. static int __init enable_mrs_emulation(void)
  1660. {
  1661. register_undef_hook(&mrs_hook);
  1662. return 0;
  1663. }
  1664. core_initcall(enable_mrs_emulation);
  1665. void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
  1666. {
  1667. /* Firmware may have left a deferred SError in this register. */
  1668. write_sysreg_s(0, SYS_DISR_EL1);
  1669. }
  1670. ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
  1671. char *buf)
  1672. {
  1673. if (__meltdown_safe)
  1674. return sprintf(buf, "Not affected\n");
  1675. if (arm64_kernel_unmapped_at_el0())
  1676. return sprintf(buf, "Mitigation: PTI\n");
  1677. return sprintf(buf, "Vulnerable\n");
  1678. }