entry.S 29 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255
  1. /*
  2. * Low-level exception handling code
  3. *
  4. * Copyright (C) 2012 ARM Ltd.
  5. * Authors: Catalin Marinas <catalin.marinas@arm.com>
  6. * Will Deacon <will.deacon@arm.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #include <linux/arm-smccc.h>
  21. #include <linux/init.h>
  22. #include <linux/linkage.h>
  23. #include <asm/alternative.h>
  24. #include <asm/assembler.h>
  25. #include <asm/asm-offsets.h>
  26. #include <asm/cpufeature.h>
  27. #include <asm/errno.h>
  28. #include <asm/esr.h>
  29. #include <asm/irq.h>
  30. #include <asm/memory.h>
  31. #include <asm/mmu.h>
  32. #include <asm/processor.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/thread_info.h>
  35. #include <asm/asm-uaccess.h>
  36. #include <asm/unistd.h>
  37. /*
  38. * Context tracking subsystem. Used to instrument transitions
  39. * between user and kernel mode.
  40. */
  41. .macro ct_user_exit
  42. #ifdef CONFIG_CONTEXT_TRACKING
  43. bl context_tracking_user_exit
  44. #endif
  45. .endm
  46. .macro ct_user_enter
  47. #ifdef CONFIG_CONTEXT_TRACKING
  48. bl context_tracking_user_enter
  49. #endif
  50. .endm
  51. .macro clear_gp_regs
  52. .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
  53. mov x\n, xzr
  54. .endr
  55. .endm
  56. /*
  57. * Bad Abort numbers
  58. *-----------------
  59. */
  60. #define BAD_SYNC 0
  61. #define BAD_IRQ 1
  62. #define BAD_FIQ 2
  63. #define BAD_ERROR 3
  64. .macro kernel_ventry, el, label, regsize = 64
  65. .align 7
  66. #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
  67. alternative_if ARM64_UNMAP_KERNEL_AT_EL0
  68. .if \el == 0
  69. .if \regsize == 64
  70. mrs x30, tpidrro_el0
  71. msr tpidrro_el0, xzr
  72. .else
  73. mov x30, xzr
  74. .endif
  75. .endif
  76. alternative_else_nop_endif
  77. #endif
  78. sub sp, sp, #S_FRAME_SIZE
  79. #ifdef CONFIG_VMAP_STACK
  80. /*
  81. * Test whether the SP has overflowed, without corrupting a GPR.
  82. * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT).
  83. */
  84. add sp, sp, x0 // sp' = sp + x0
  85. sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
  86. tbnz x0, #THREAD_SHIFT, 0f
  87. sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
  88. sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
  89. b el\()\el\()_\label
  90. 0:
  91. /*
  92. * Either we've just detected an overflow, or we've taken an exception
  93. * while on the overflow stack. Either way, we won't return to
  94. * userspace, and can clobber EL0 registers to free up GPRs.
  95. */
  96. /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
  97. msr tpidr_el0, x0
  98. /* Recover the original x0 value and stash it in tpidrro_el0 */
  99. sub x0, sp, x0
  100. msr tpidrro_el0, x0
  101. /* Switch to the overflow stack */
  102. adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
  103. /*
  104. * Check whether we were already on the overflow stack. This may happen
  105. * after panic() re-enables interrupts.
  106. */
  107. mrs x0, tpidr_el0 // sp of interrupted context
  108. sub x0, sp, x0 // delta with top of overflow stack
  109. tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
  110. b.ne __bad_stack // no? -> bad stack pointer
  111. /* We were already on the overflow stack. Restore sp/x0 and carry on. */
  112. sub sp, sp, x0
  113. mrs x0, tpidrro_el0
  114. #endif
  115. b el\()\el\()_\label
  116. .endm
  117. .macro tramp_alias, dst, sym
  118. mov_q \dst, TRAMP_VALIAS
  119. add \dst, \dst, #(\sym - .entry.tramp.text)
  120. .endm
  121. // This macro corrupts x0-x3. It is the caller's duty
  122. // to save/restore them if required.
  123. .macro apply_ssbd, state, tmp1, tmp2
  124. #ifdef CONFIG_ARM64_SSBD
  125. alternative_cb arm64_enable_wa2_handling
  126. b .L__asm_ssbd_skip\@
  127. alternative_cb_end
  128. ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
  129. cbz \tmp2, .L__asm_ssbd_skip\@
  130. ldr \tmp2, [tsk, #TSK_TI_FLAGS]
  131. tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
  132. mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
  133. mov w1, #\state
  134. alternative_cb arm64_update_smccc_conduit
  135. nop // Patched to SMC/HVC #0
  136. alternative_cb_end
  137. .L__asm_ssbd_skip\@:
  138. #endif
  139. .endm
  140. .macro kernel_entry, el, regsize = 64
  141. .if \regsize == 32
  142. mov w0, w0 // zero upper 32 bits of x0
  143. .endif
  144. stp x0, x1, [sp, #16 * 0]
  145. stp x2, x3, [sp, #16 * 1]
  146. stp x4, x5, [sp, #16 * 2]
  147. stp x6, x7, [sp, #16 * 3]
  148. stp x8, x9, [sp, #16 * 4]
  149. stp x10, x11, [sp, #16 * 5]
  150. stp x12, x13, [sp, #16 * 6]
  151. stp x14, x15, [sp, #16 * 7]
  152. stp x16, x17, [sp, #16 * 8]
  153. stp x18, x19, [sp, #16 * 9]
  154. stp x20, x21, [sp, #16 * 10]
  155. stp x22, x23, [sp, #16 * 11]
  156. stp x24, x25, [sp, #16 * 12]
  157. stp x26, x27, [sp, #16 * 13]
  158. stp x28, x29, [sp, #16 * 14]
  159. .if \el == 0
  160. clear_gp_regs
  161. mrs x21, sp_el0
  162. ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
  163. ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug
  164. disable_step_tsk x19, x20 // exceptions when scheduling.
  165. apply_ssbd 1, x22, x23
  166. .else
  167. add x21, sp, #S_FRAME_SIZE
  168. get_thread_info tsk
  169. /* Save the task's original addr_limit and set USER_DS */
  170. ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
  171. str x20, [sp, #S_ORIG_ADDR_LIMIT]
  172. mov x20, #USER_DS
  173. str x20, [tsk, #TSK_TI_ADDR_LIMIT]
  174. /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
  175. .endif /* \el == 0 */
  176. mrs x22, elr_el1
  177. mrs x23, spsr_el1
  178. stp lr, x21, [sp, #S_LR]
  179. /*
  180. * In order to be able to dump the contents of struct pt_regs at the
  181. * time the exception was taken (in case we attempt to walk the call
  182. * stack later), chain it together with the stack frames.
  183. */
  184. .if \el == 0
  185. stp xzr, xzr, [sp, #S_STACKFRAME]
  186. .else
  187. stp x29, x22, [sp, #S_STACKFRAME]
  188. .endif
  189. add x29, sp, #S_STACKFRAME
  190. #ifdef CONFIG_ARM64_SW_TTBR0_PAN
  191. /*
  192. * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
  193. * EL0, there is no need to check the state of TTBR0_EL1 since
  194. * accesses are always enabled.
  195. * Note that the meaning of this bit differs from the ARMv8.1 PAN
  196. * feature as all TTBR0_EL1 accesses are disabled, not just those to
  197. * user mappings.
  198. */
  199. alternative_if ARM64_HAS_PAN
  200. b 1f // skip TTBR0 PAN
  201. alternative_else_nop_endif
  202. .if \el != 0
  203. mrs x21, ttbr0_el1
  204. tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
  205. orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
  206. b.eq 1f // TTBR0 access already disabled
  207. and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
  208. .endif
  209. __uaccess_ttbr0_disable x21
  210. 1:
  211. #endif
  212. stp x22, x23, [sp, #S_PC]
  213. /* Not in a syscall by default (el0_svc overwrites for real syscall) */
  214. .if \el == 0
  215. mov w21, #NO_SYSCALL
  216. str w21, [sp, #S_SYSCALLNO]
  217. .endif
  218. /*
  219. * Set sp_el0 to current thread_info.
  220. */
  221. .if \el == 0
  222. msr sp_el0, tsk
  223. .endif
  224. /*
  225. * Registers that may be useful after this macro is invoked:
  226. *
  227. * x21 - aborted SP
  228. * x22 - aborted PC
  229. * x23 - aborted PSTATE
  230. */
  231. .endm
  232. .macro kernel_exit, el
  233. .if \el != 0
  234. disable_daif
  235. /* Restore the task's original addr_limit. */
  236. ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
  237. str x20, [tsk, #TSK_TI_ADDR_LIMIT]
  238. /* No need to restore UAO, it will be restored from SPSR_EL1 */
  239. .endif
  240. ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
  241. .if \el == 0
  242. ct_user_enter
  243. .endif
  244. #ifdef CONFIG_ARM64_SW_TTBR0_PAN
  245. /*
  246. * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
  247. * PAN bit checking.
  248. */
  249. alternative_if ARM64_HAS_PAN
  250. b 2f // skip TTBR0 PAN
  251. alternative_else_nop_endif
  252. .if \el != 0
  253. tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
  254. .endif
  255. __uaccess_ttbr0_enable x0, x1
  256. .if \el == 0
  257. /*
  258. * Enable errata workarounds only if returning to user. The only
  259. * workaround currently required for TTBR0_EL1 changes are for the
  260. * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
  261. * corruption).
  262. */
  263. bl post_ttbr_update_workaround
  264. .endif
  265. 1:
  266. .if \el != 0
  267. and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
  268. .endif
  269. 2:
  270. #endif
  271. .if \el == 0
  272. ldr x23, [sp, #S_SP] // load return stack pointer
  273. msr sp_el0, x23
  274. tst x22, #PSR_MODE32_BIT // native task?
  275. b.eq 3f
  276. #ifdef CONFIG_ARM64_ERRATUM_845719
  277. alternative_if ARM64_WORKAROUND_845719
  278. #ifdef CONFIG_PID_IN_CONTEXTIDR
  279. mrs x29, contextidr_el1
  280. msr contextidr_el1, x29
  281. #else
  282. msr contextidr_el1, xzr
  283. #endif
  284. alternative_else_nop_endif
  285. #endif
  286. 3:
  287. apply_ssbd 0, x0, x1
  288. .endif
  289. msr elr_el1, x21 // set up the return data
  290. msr spsr_el1, x22
  291. ldp x0, x1, [sp, #16 * 0]
  292. ldp x2, x3, [sp, #16 * 1]
  293. ldp x4, x5, [sp, #16 * 2]
  294. ldp x6, x7, [sp, #16 * 3]
  295. ldp x8, x9, [sp, #16 * 4]
  296. ldp x10, x11, [sp, #16 * 5]
  297. ldp x12, x13, [sp, #16 * 6]
  298. ldp x14, x15, [sp, #16 * 7]
  299. ldp x16, x17, [sp, #16 * 8]
  300. ldp x18, x19, [sp, #16 * 9]
  301. ldp x20, x21, [sp, #16 * 10]
  302. ldp x22, x23, [sp, #16 * 11]
  303. ldp x24, x25, [sp, #16 * 12]
  304. ldp x26, x27, [sp, #16 * 13]
  305. ldp x28, x29, [sp, #16 * 14]
  306. ldr lr, [sp, #S_LR]
  307. add sp, sp, #S_FRAME_SIZE // restore sp
  308. /*
  309. * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on eret context synchronization
  310. * when returning from IPI handler, and when returning to user-space.
  311. */
  312. .if \el == 0
  313. alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
  314. #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
  315. bne 4f
  316. msr far_el1, x30
  317. tramp_alias x30, tramp_exit_native
  318. br x30
  319. 4:
  320. tramp_alias x30, tramp_exit_compat
  321. br x30
  322. #endif
  323. .else
  324. eret
  325. .endif
  326. .endm
  327. .macro irq_stack_entry
  328. mov x19, sp // preserve the original sp
  329. /*
  330. * Compare sp with the base of the task stack.
  331. * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
  332. * and should switch to the irq stack.
  333. */
  334. ldr x25, [tsk, TSK_STACK]
  335. eor x25, x25, x19
  336. and x25, x25, #~(THREAD_SIZE - 1)
  337. cbnz x25, 9998f
  338. ldr_this_cpu x25, irq_stack_ptr, x26
  339. mov x26, #IRQ_STACK_SIZE
  340. add x26, x25, x26
  341. /* switch to the irq stack */
  342. mov sp, x26
  343. 9998:
  344. .endm
  345. /*
  346. * x19 should be preserved between irq_stack_entry and
  347. * irq_stack_exit.
  348. */
  349. .macro irq_stack_exit
  350. mov sp, x19
  351. .endm
  352. /*
  353. * These are the registers used in the syscall handler, and allow us to
  354. * have in theory up to 7 arguments to a function - x0 to x6.
  355. *
  356. * x7 is reserved for the system call number in 32-bit mode.
  357. */
  358. wsc_nr .req w25 // number of system calls
  359. xsc_nr .req x25 // number of system calls (zero-extended)
  360. wscno .req w26 // syscall number
  361. xscno .req x26 // syscall number (zero-extended)
  362. stbl .req x27 // syscall table pointer
  363. tsk .req x28 // current thread_info
  364. /*
  365. * Interrupt handling.
  366. */
  367. .macro irq_handler
  368. ldr_l x1, handle_arch_irq
  369. mov x0, sp
  370. irq_stack_entry
  371. blr x1
  372. irq_stack_exit
  373. .endm
  374. .text
  375. /*
  376. * Exception vectors.
  377. */
  378. .pushsection ".entry.text", "ax"
  379. .align 11
  380. ENTRY(vectors)
  381. kernel_ventry 1, sync_invalid // Synchronous EL1t
  382. kernel_ventry 1, irq_invalid // IRQ EL1t
  383. kernel_ventry 1, fiq_invalid // FIQ EL1t
  384. kernel_ventry 1, error_invalid // Error EL1t
  385. kernel_ventry 1, sync // Synchronous EL1h
  386. kernel_ventry 1, irq // IRQ EL1h
  387. kernel_ventry 1, fiq_invalid // FIQ EL1h
  388. kernel_ventry 1, error // Error EL1h
  389. kernel_ventry 0, sync // Synchronous 64-bit EL0
  390. kernel_ventry 0, irq // IRQ 64-bit EL0
  391. kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0
  392. kernel_ventry 0, error // Error 64-bit EL0
  393. #ifdef CONFIG_COMPAT
  394. kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
  395. kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
  396. kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0
  397. kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
  398. #else
  399. kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
  400. kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
  401. kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
  402. kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
  403. #endif
  404. END(vectors)
  405. #ifdef CONFIG_VMAP_STACK
  406. /*
  407. * We detected an overflow in kernel_ventry, which switched to the
  408. * overflow stack. Stash the exception regs, and head to our overflow
  409. * handler.
  410. */
  411. __bad_stack:
  412. /* Restore the original x0 value */
  413. mrs x0, tpidrro_el0
  414. /*
  415. * Store the original GPRs to the new stack. The orginal SP (minus
  416. * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
  417. */
  418. sub sp, sp, #S_FRAME_SIZE
  419. kernel_entry 1
  420. mrs x0, tpidr_el0
  421. add x0, x0, #S_FRAME_SIZE
  422. str x0, [sp, #S_SP]
  423. /* Stash the regs for handle_bad_stack */
  424. mov x0, sp
  425. /* Time to die */
  426. bl handle_bad_stack
  427. ASM_BUG()
  428. #endif /* CONFIG_VMAP_STACK */
  429. /*
  430. * Invalid mode handlers
  431. */
  432. .macro inv_entry, el, reason, regsize = 64
  433. kernel_entry \el, \regsize
  434. mov x0, sp
  435. mov x1, #\reason
  436. mrs x2, esr_el1
  437. bl bad_mode
  438. ASM_BUG()
  439. .endm
  440. el0_sync_invalid:
  441. inv_entry 0, BAD_SYNC
  442. ENDPROC(el0_sync_invalid)
  443. el0_irq_invalid:
  444. inv_entry 0, BAD_IRQ
  445. ENDPROC(el0_irq_invalid)
  446. el0_fiq_invalid:
  447. inv_entry 0, BAD_FIQ
  448. ENDPROC(el0_fiq_invalid)
  449. el0_error_invalid:
  450. inv_entry 0, BAD_ERROR
  451. ENDPROC(el0_error_invalid)
  452. #ifdef CONFIG_COMPAT
  453. el0_fiq_invalid_compat:
  454. inv_entry 0, BAD_FIQ, 32
  455. ENDPROC(el0_fiq_invalid_compat)
  456. #endif
  457. el1_sync_invalid:
  458. inv_entry 1, BAD_SYNC
  459. ENDPROC(el1_sync_invalid)
  460. el1_irq_invalid:
  461. inv_entry 1, BAD_IRQ
  462. ENDPROC(el1_irq_invalid)
  463. el1_fiq_invalid:
  464. inv_entry 1, BAD_FIQ
  465. ENDPROC(el1_fiq_invalid)
  466. el1_error_invalid:
  467. inv_entry 1, BAD_ERROR
  468. ENDPROC(el1_error_invalid)
  469. /*
  470. * EL1 mode handlers.
  471. */
  472. .align 6
  473. el1_sync:
  474. kernel_entry 1
  475. mrs x1, esr_el1 // read the syndrome register
  476. lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
  477. cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
  478. b.eq el1_da
  479. cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
  480. b.eq el1_ia
  481. cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
  482. b.eq el1_undef
  483. cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
  484. b.eq el1_sp_pc
  485. cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
  486. b.eq el1_sp_pc
  487. cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
  488. b.eq el1_undef
  489. cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
  490. b.ge el1_dbg
  491. b el1_inv
  492. el1_ia:
  493. /*
  494. * Fall through to the Data abort case
  495. */
  496. el1_da:
  497. /*
  498. * Data abort handling
  499. */
  500. mrs x3, far_el1
  501. inherit_daif pstate=x23, tmp=x2
  502. clear_address_tag x0, x3
  503. mov x2, sp // struct pt_regs
  504. bl do_mem_abort
  505. kernel_exit 1
  506. el1_sp_pc:
  507. /*
  508. * Stack or PC alignment exception handling
  509. */
  510. mrs x0, far_el1
  511. inherit_daif pstate=x23, tmp=x2
  512. mov x2, sp
  513. bl do_sp_pc_abort
  514. ASM_BUG()
  515. el1_undef:
  516. /*
  517. * Undefined instruction
  518. */
  519. inherit_daif pstate=x23, tmp=x2
  520. mov x0, sp
  521. bl do_undefinstr
  522. kernel_exit 1
  523. el1_dbg:
  524. /*
  525. * Debug exception handling
  526. */
  527. cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
  528. cinc x24, x24, eq // set bit '0'
  529. tbz x24, #0, el1_inv // EL1 only
  530. mrs x0, far_el1
  531. mov x2, sp // struct pt_regs
  532. bl do_debug_exception
  533. kernel_exit 1
  534. el1_inv:
  535. // TODO: add support for undefined instructions in kernel mode
  536. inherit_daif pstate=x23, tmp=x2
  537. mov x0, sp
  538. mov x2, x1
  539. mov x1, #BAD_SYNC
  540. bl bad_mode
  541. ASM_BUG()
  542. ENDPROC(el1_sync)
  543. .align 6
  544. el1_irq:
  545. kernel_entry 1
  546. enable_da_f
  547. #ifdef CONFIG_TRACE_IRQFLAGS
  548. bl trace_hardirqs_off
  549. #endif
  550. irq_handler
  551. #ifdef CONFIG_PREEMPT
  552. ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count
  553. cbnz w24, 1f // preempt count != 0
  554. ldr x0, [tsk, #TSK_TI_FLAGS] // get flags
  555. tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
  556. bl el1_preempt
  557. 1:
  558. #endif
  559. #ifdef CONFIG_TRACE_IRQFLAGS
  560. bl trace_hardirqs_on
  561. #endif
  562. kernel_exit 1
  563. ENDPROC(el1_irq)
  564. #ifdef CONFIG_PREEMPT
  565. el1_preempt:
  566. mov x24, lr
  567. 1: bl preempt_schedule_irq // irq en/disable is done inside
  568. ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS
  569. tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
  570. ret x24
  571. #endif
  572. /*
  573. * EL0 mode handlers.
  574. */
  575. .align 6
  576. el0_sync:
  577. kernel_entry 0
  578. mrs x25, esr_el1 // read the syndrome register
  579. lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
  580. cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
  581. b.eq el0_svc
  582. cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
  583. b.eq el0_da
  584. cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
  585. b.eq el0_ia
  586. cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
  587. b.eq el0_fpsimd_acc
  588. cmp x24, #ESR_ELx_EC_SVE // SVE access
  589. b.eq el0_sve_acc
  590. cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
  591. b.eq el0_fpsimd_exc
  592. cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
  593. b.eq el0_sys
  594. cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
  595. b.eq el0_sp_pc
  596. cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
  597. b.eq el0_sp_pc
  598. cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
  599. b.eq el0_undef
  600. cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
  601. b.ge el0_dbg
  602. b el0_inv
  603. #ifdef CONFIG_COMPAT
  604. .align 6
  605. el0_sync_compat:
  606. kernel_entry 0, 32
  607. mrs x25, esr_el1 // read the syndrome register
  608. lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
  609. cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
  610. b.eq el0_svc_compat
  611. cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
  612. b.eq el0_da
  613. cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
  614. b.eq el0_ia
  615. cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
  616. b.eq el0_fpsimd_acc
  617. cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
  618. b.eq el0_fpsimd_exc
  619. cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
  620. b.eq el0_sp_pc
  621. cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
  622. b.eq el0_undef
  623. cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
  624. b.eq el0_undef
  625. cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
  626. b.eq el0_undef
  627. cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
  628. b.eq el0_undef
  629. cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
  630. b.eq el0_undef
  631. cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
  632. b.eq el0_undef
  633. cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
  634. b.ge el0_dbg
  635. b el0_inv
  636. el0_svc_compat:
  637. mov x0, sp
  638. bl el0_svc_compat_handler
  639. b ret_to_user
  640. .align 6
  641. el0_irq_compat:
  642. kernel_entry 0, 32
  643. b el0_irq_naked
  644. el0_error_compat:
  645. kernel_entry 0, 32
  646. b el0_error_naked
  647. #endif
  648. el0_da:
  649. /*
  650. * Data abort handling
  651. */
  652. mrs x26, far_el1
  653. enable_daif
  654. ct_user_exit
  655. clear_address_tag x0, x26
  656. mov x1, x25
  657. mov x2, sp
  658. bl do_mem_abort
  659. b ret_to_user
  660. el0_ia:
  661. /*
  662. * Instruction abort handling
  663. */
  664. mrs x26, far_el1
  665. enable_da_f
  666. #ifdef CONFIG_TRACE_IRQFLAGS
  667. bl trace_hardirqs_off
  668. #endif
  669. ct_user_exit
  670. mov x0, x26
  671. mov x1, x25
  672. mov x2, sp
  673. bl do_el0_ia_bp_hardening
  674. b ret_to_user
  675. el0_fpsimd_acc:
  676. /*
  677. * Floating Point or Advanced SIMD access
  678. */
  679. enable_daif
  680. ct_user_exit
  681. mov x0, x25
  682. mov x1, sp
  683. bl do_fpsimd_acc
  684. b ret_to_user
  685. el0_sve_acc:
  686. /*
  687. * Scalable Vector Extension access
  688. */
  689. enable_daif
  690. ct_user_exit
  691. mov x0, x25
  692. mov x1, sp
  693. bl do_sve_acc
  694. b ret_to_user
  695. el0_fpsimd_exc:
  696. /*
  697. * Floating Point, Advanced SIMD or SVE exception
  698. */
  699. enable_daif
  700. ct_user_exit
  701. mov x0, x25
  702. mov x1, sp
  703. bl do_fpsimd_exc
  704. b ret_to_user
  705. el0_sp_pc:
  706. /*
  707. * Stack or PC alignment exception handling
  708. */
  709. mrs x26, far_el1
  710. enable_da_f
  711. #ifdef CONFIG_TRACE_IRQFLAGS
  712. bl trace_hardirqs_off
  713. #endif
  714. ct_user_exit
  715. mov x0, x26
  716. mov x1, x25
  717. mov x2, sp
  718. bl do_sp_pc_abort
  719. b ret_to_user
  720. el0_undef:
  721. /*
  722. * Undefined instruction
  723. */
  724. enable_daif
  725. ct_user_exit
  726. mov x0, sp
  727. bl do_undefinstr
  728. b ret_to_user
  729. el0_sys:
  730. /*
  731. * System instructions, for trapped cache maintenance instructions
  732. */
  733. enable_daif
  734. ct_user_exit
  735. mov x0, x25
  736. mov x1, sp
  737. bl do_sysinstr
  738. b ret_to_user
  739. el0_dbg:
  740. /*
  741. * Debug exception handling
  742. */
  743. tbnz x24, #0, el0_inv // EL0 only
  744. mrs x0, far_el1
  745. mov x1, x25
  746. mov x2, sp
  747. bl do_debug_exception
  748. enable_da_f
  749. ct_user_exit
  750. b ret_to_user
  751. el0_inv:
  752. enable_daif
  753. ct_user_exit
  754. mov x0, sp
  755. mov x1, #BAD_SYNC
  756. mov x2, x25
  757. bl bad_el0_sync
  758. b ret_to_user
  759. ENDPROC(el0_sync)
  760. .align 6
  761. el0_irq:
  762. kernel_entry 0
  763. el0_irq_naked:
  764. enable_da_f
  765. #ifdef CONFIG_TRACE_IRQFLAGS
  766. bl trace_hardirqs_off
  767. #endif
  768. ct_user_exit
  769. #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
  770. tbz x22, #55, 1f
  771. bl do_el0_irq_bp_hardening
  772. 1:
  773. #endif
  774. irq_handler
  775. #ifdef CONFIG_TRACE_IRQFLAGS
  776. bl trace_hardirqs_on
  777. #endif
  778. b ret_to_user
  779. ENDPROC(el0_irq)
  780. el1_error:
  781. kernel_entry 1
  782. mrs x1, esr_el1
  783. enable_dbg
  784. mov x0, sp
  785. bl do_serror
  786. kernel_exit 1
  787. ENDPROC(el1_error)
  788. el0_error:
  789. kernel_entry 0
  790. el0_error_naked:
  791. mrs x1, esr_el1
  792. enable_dbg
  793. mov x0, sp
  794. bl do_serror
  795. enable_da_f
  796. ct_user_exit
  797. b ret_to_user
  798. ENDPROC(el0_error)
  799. /*
  800. * Ok, we need to do extra processing, enter the slow path.
  801. */
  802. work_pending:
  803. mov x0, sp // 'regs'
  804. bl do_notify_resume
  805. #ifdef CONFIG_TRACE_IRQFLAGS
  806. bl trace_hardirqs_on // enabled while in userspace
  807. #endif
  808. ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
  809. b finish_ret_to_user
  810. /*
  811. * "slow" syscall return path.
  812. */
  813. ret_to_user:
  814. disable_daif
  815. ldr x1, [tsk, #TSK_TI_FLAGS]
  816. and x2, x1, #_TIF_WORK_MASK
  817. cbnz x2, work_pending
  818. finish_ret_to_user:
  819. enable_step_tsk x1, x2
  820. #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
  821. bl stackleak_erase
  822. #endif
  823. kernel_exit 0
  824. ENDPROC(ret_to_user)
  825. /*
  826. * SVC handler.
  827. */
  828. .align 6
  829. el0_svc:
  830. mov x0, sp
  831. bl el0_svc_handler
  832. b ret_to_user
  833. ENDPROC(el0_svc)
  834. .popsection // .entry.text
  835. #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
  836. /*
  837. * Exception vectors trampoline.
  838. */
  839. .pushsection ".entry.tramp.text", "ax"
  840. .macro tramp_map_kernel, tmp
  841. mrs \tmp, ttbr1_el1
  842. add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
  843. bic \tmp, \tmp, #USER_ASID_FLAG
  844. msr ttbr1_el1, \tmp
  845. #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
  846. alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
  847. /* ASID already in \tmp[63:48] */
  848. movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
  849. movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
  850. /* 2MB boundary containing the vectors, so we nobble the walk cache */
  851. movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
  852. isb
  853. tlbi vae1, \tmp
  854. dsb nsh
  855. alternative_else_nop_endif
  856. #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
  857. .endm
  858. .macro tramp_unmap_kernel, tmp
  859. mrs \tmp, ttbr1_el1
  860. sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
  861. orr \tmp, \tmp, #USER_ASID_FLAG
  862. msr ttbr1_el1, \tmp
  863. /*
  864. * We avoid running the post_ttbr_update_workaround here because
  865. * it's only needed by Cavium ThunderX, which requires KPTI to be
  866. * disabled.
  867. */
  868. .endm
  869. .macro tramp_ventry, regsize = 64
  870. .align 7
  871. 1:
  872. .if \regsize == 64
  873. msr tpidrro_el0, x30 // Restored in kernel_ventry
  874. .endif
  875. /*
  876. * Defend against branch aliasing attacks by pushing a dummy
  877. * entry onto the return stack and using a RET instruction to
  878. * enter the full-fat kernel vectors.
  879. */
  880. bl 2f
  881. b .
  882. 2:
  883. tramp_map_kernel x30
  884. #ifdef CONFIG_RANDOMIZE_BASE
  885. adr x30, tramp_vectors + PAGE_SIZE
  886. alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
  887. ldr x30, [x30]
  888. #else
  889. ldr x30, =vectors
  890. #endif
  891. prfm plil1strm, [x30, #(1b - tramp_vectors)]
  892. msr vbar_el1, x30
  893. add x30, x30, #(1b - tramp_vectors)
  894. isb
  895. ret
  896. .endm
  897. .macro tramp_exit, regsize = 64
  898. adr x30, tramp_vectors
  899. msr vbar_el1, x30
  900. tramp_unmap_kernel x30
  901. .if \regsize == 64
  902. mrs x30, far_el1
  903. .endif
  904. eret
  905. .endm
  906. .align 11
  907. ENTRY(tramp_vectors)
  908. .space 0x400
  909. tramp_ventry
  910. tramp_ventry
  911. tramp_ventry
  912. tramp_ventry
  913. tramp_ventry 32
  914. tramp_ventry 32
  915. tramp_ventry 32
  916. tramp_ventry 32
  917. END(tramp_vectors)
  918. ENTRY(tramp_exit_native)
  919. tramp_exit
  920. END(tramp_exit_native)
  921. ENTRY(tramp_exit_compat)
  922. tramp_exit 32
  923. END(tramp_exit_compat)
  924. .ltorg
  925. .popsection // .entry.tramp.text
  926. #ifdef CONFIG_RANDOMIZE_BASE
  927. .pushsection ".rodata", "a"
  928. .align PAGE_SHIFT
  929. .globl __entry_tramp_data_start
  930. __entry_tramp_data_start:
  931. .quad vectors
  932. .popsection // .rodata
  933. #endif /* CONFIG_RANDOMIZE_BASE */
  934. #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
  935. /*
  936. * Register switch for AArch64. The callee-saved registers need to be saved
  937. * and restored. On entry:
  938. * x0 = previous task_struct (must be preserved across the switch)
  939. * x1 = next task_struct
  940. * Previous and next are guaranteed not to be the same.
  941. *
  942. */
  943. ENTRY(cpu_switch_to)
  944. mov x10, #THREAD_CPU_CONTEXT
  945. add x8, x0, x10
  946. mov x9, sp
  947. stp x19, x20, [x8], #16 // store callee-saved registers
  948. stp x21, x22, [x8], #16
  949. stp x23, x24, [x8], #16
  950. stp x25, x26, [x8], #16
  951. stp x27, x28, [x8], #16
  952. stp x29, x9, [x8], #16
  953. str lr, [x8]
  954. add x8, x1, x10
  955. ldp x19, x20, [x8], #16 // restore callee-saved registers
  956. ldp x21, x22, [x8], #16
  957. ldp x23, x24, [x8], #16
  958. ldp x25, x26, [x8], #16
  959. ldp x27, x28, [x8], #16
  960. ldp x29, x9, [x8], #16
  961. ldr lr, [x8]
  962. mov sp, x9
  963. msr sp_el0, x1
  964. ret
  965. ENDPROC(cpu_switch_to)
  966. NOKPROBE(cpu_switch_to)
  967. /*
  968. * This is how we return from a fork.
  969. */
  970. ENTRY(ret_from_fork)
  971. bl schedule_tail
  972. cbz x19, 1f // not a kernel thread
  973. mov x0, x20
  974. blr x19
  975. 1: get_thread_info tsk
  976. b ret_to_user
  977. ENDPROC(ret_from_fork)
  978. NOKPROBE(ret_from_fork)
  979. #ifdef CONFIG_ARM_SDE_INTERFACE
  980. #include <asm/sdei.h>
  981. #include <uapi/linux/arm_sdei.h>
  982. .macro sdei_handler_exit exit_mode
  983. /* On success, this call never returns... */
  984. cmp \exit_mode, #SDEI_EXIT_SMC
  985. b.ne 99f
  986. smc #0
  987. b .
  988. 99: hvc #0
  989. b .
  990. .endm
  991. #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
  992. /*
  993. * The regular SDEI entry point may have been unmapped along with the rest of
  994. * the kernel. This trampoline restores the kernel mapping to make the x1 memory
  995. * argument accessible.
  996. *
  997. * This clobbers x4, __sdei_handler() will restore this from firmware's
  998. * copy.
  999. */
  1000. .ltorg
  1001. .pushsection ".entry.tramp.text", "ax"
  1002. ENTRY(__sdei_asm_entry_trampoline)
  1003. mrs x4, ttbr1_el1
  1004. tbz x4, #USER_ASID_BIT, 1f
  1005. tramp_map_kernel tmp=x4
  1006. isb
  1007. mov x4, xzr
  1008. /*
  1009. * Use reg->interrupted_regs.addr_limit to remember whether to unmap
  1010. * the kernel on exit.
  1011. */
  1012. 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
  1013. #ifdef CONFIG_RANDOMIZE_BASE
  1014. adr x4, tramp_vectors + PAGE_SIZE
  1015. add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
  1016. ldr x4, [x4]
  1017. #else
  1018. ldr x4, =__sdei_asm_handler
  1019. #endif
  1020. br x4
  1021. ENDPROC(__sdei_asm_entry_trampoline)
  1022. NOKPROBE(__sdei_asm_entry_trampoline)
  1023. /*
  1024. * Make the exit call and restore the original ttbr1_el1
  1025. *
  1026. * x0 & x1: setup for the exit API call
  1027. * x2: exit_mode
  1028. * x4: struct sdei_registered_event argument from registration time.
  1029. */
  1030. ENTRY(__sdei_asm_exit_trampoline)
  1031. ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
  1032. cbnz x4, 1f
  1033. tramp_unmap_kernel tmp=x4
  1034. 1: sdei_handler_exit exit_mode=x2
  1035. ENDPROC(__sdei_asm_exit_trampoline)
  1036. NOKPROBE(__sdei_asm_exit_trampoline)
  1037. .ltorg
  1038. .popsection // .entry.tramp.text
  1039. #ifdef CONFIG_RANDOMIZE_BASE
  1040. .pushsection ".rodata", "a"
  1041. __sdei_asm_trampoline_next_handler:
  1042. .quad __sdei_asm_handler
  1043. .popsection // .rodata
  1044. #endif /* CONFIG_RANDOMIZE_BASE */
  1045. #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
  1046. /*
  1047. * Software Delegated Exception entry point.
  1048. *
  1049. * x0: Event number
  1050. * x1: struct sdei_registered_event argument from registration time.
  1051. * x2: interrupted PC
  1052. * x3: interrupted PSTATE
  1053. * x4: maybe clobbered by the trampoline
  1054. *
  1055. * Firmware has preserved x0->x17 for us, we must save/restore the rest to
  1056. * follow SMC-CC. We save (or retrieve) all the registers as the handler may
  1057. * want them.
  1058. */
  1059. ENTRY(__sdei_asm_handler)
  1060. stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
  1061. stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
  1062. stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
  1063. stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
  1064. stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
  1065. stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
  1066. stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
  1067. stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
  1068. stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
  1069. stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
  1070. stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
  1071. stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
  1072. stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
  1073. stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
  1074. mov x4, sp
  1075. stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
  1076. mov x19, x1
  1077. #ifdef CONFIG_VMAP_STACK
  1078. /*
  1079. * entry.S may have been using sp as a scratch register, find whether
  1080. * this is a normal or critical event and switch to the appropriate
  1081. * stack for this CPU.
  1082. */
  1083. ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
  1084. cbnz w4, 1f
  1085. ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
  1086. b 2f
  1087. 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
  1088. 2: mov x6, #SDEI_STACK_SIZE
  1089. add x5, x5, x6
  1090. mov sp, x5
  1091. #endif
  1092. /*
  1093. * We may have interrupted userspace, or a guest, or exit-from or
  1094. * return-to either of these. We can't trust sp_el0, restore it.
  1095. */
  1096. mrs x28, sp_el0
  1097. ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
  1098. msr sp_el0, x0
  1099. /* If we interrupted the kernel point to the previous stack/frame. */
  1100. and x0, x3, #0xc
  1101. mrs x1, CurrentEL
  1102. cmp x0, x1
  1103. csel x29, x29, xzr, eq // fp, or zero
  1104. csel x4, x2, xzr, eq // elr, or zero
  1105. stp x29, x4, [sp, #-16]!
  1106. mov x29, sp
  1107. add x0, x19, #SDEI_EVENT_INTREGS
  1108. mov x1, x19
  1109. bl __sdei_handler
  1110. msr sp_el0, x28
  1111. /* restore regs >x17 that we clobbered */
  1112. mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
  1113. ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
  1114. ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
  1115. ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
  1116. mov sp, x1
  1117. mov x1, x0 // address to complete_and_resume
  1118. /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
  1119. cmp x0, #1
  1120. mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
  1121. mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
  1122. csel x0, x2, x3, ls
  1123. ldr_l x2, sdei_exit_mode
  1124. alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
  1125. sdei_handler_exit exit_mode=x2
  1126. alternative_else_nop_endif
  1127. #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
  1128. tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
  1129. br x5
  1130. #endif
  1131. ENDPROC(__sdei_asm_handler)
  1132. NOKPROBE(__sdei_asm_handler)
  1133. #endif /* CONFIG_ARM_SDE_INTERFACE */