setup-sh7750.c 9.8 KB

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  1. /*
  2. * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup
  3. *
  4. * Copyright (C) 2006 Paul Mundt
  5. * Copyright (C) 2006 Jamie Lenehan
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/platform_device.h>
  12. #include <linux/init.h>
  13. #include <linux/serial.h>
  14. #include <linux/io.h>
  15. #include <linux/sh_timer.h>
  16. #include <linux/sh_intc.h>
  17. #include <linux/serial_sci.h>
  18. #include <generated/machtypes.h>
  19. static struct resource rtc_resources[] = {
  20. [0] = {
  21. .start = 0xffc80000,
  22. .end = 0xffc80000 + 0x58 - 1,
  23. .flags = IORESOURCE_IO,
  24. },
  25. [1] = {
  26. /* Shared Period/Carry/Alarm IRQ */
  27. .start = evt2irq(0x480),
  28. .flags = IORESOURCE_IRQ,
  29. },
  30. };
  31. static struct platform_device rtc_device = {
  32. .name = "sh-rtc",
  33. .id = -1,
  34. .num_resources = ARRAY_SIZE(rtc_resources),
  35. .resource = rtc_resources,
  36. };
  37. static struct plat_sci_port sci_platform_data = {
  38. .type = PORT_SCI,
  39. };
  40. static struct resource sci_resources[] = {
  41. DEFINE_RES_MEM(0xffe00000, 0x20),
  42. DEFINE_RES_IRQ(evt2irq(0x4e0)),
  43. };
  44. static struct platform_device sci_device = {
  45. .name = "sh-sci",
  46. .id = 0,
  47. .resource = sci_resources,
  48. .num_resources = ARRAY_SIZE(sci_resources),
  49. .dev = {
  50. .platform_data = &sci_platform_data,
  51. },
  52. };
  53. static struct plat_sci_port scif_platform_data = {
  54. .scscr = SCSCR_REIE,
  55. .type = PORT_SCIF,
  56. };
  57. static struct resource scif_resources[] = {
  58. DEFINE_RES_MEM(0xffe80000, 0x100),
  59. DEFINE_RES_IRQ(evt2irq(0x700)),
  60. };
  61. static struct platform_device scif_device = {
  62. .name = "sh-sci",
  63. .id = 1,
  64. .resource = scif_resources,
  65. .num_resources = ARRAY_SIZE(scif_resources),
  66. .dev = {
  67. .platform_data = &scif_platform_data,
  68. },
  69. };
  70. static struct sh_timer_config tmu0_platform_data = {
  71. .channels_mask = 7,
  72. };
  73. static struct resource tmu0_resources[] = {
  74. DEFINE_RES_MEM(0xffd80000, 0x30),
  75. DEFINE_RES_IRQ(evt2irq(0x400)),
  76. DEFINE_RES_IRQ(evt2irq(0x420)),
  77. DEFINE_RES_IRQ(evt2irq(0x440)),
  78. };
  79. static struct platform_device tmu0_device = {
  80. .name = "sh-tmu",
  81. .id = 0,
  82. .dev = {
  83. .platform_data = &tmu0_platform_data,
  84. },
  85. .resource = tmu0_resources,
  86. .num_resources = ARRAY_SIZE(tmu0_resources),
  87. };
  88. /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
  89. #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  90. defined(CONFIG_CPU_SUBTYPE_SH7751) || \
  91. defined(CONFIG_CPU_SUBTYPE_SH7751R)
  92. static struct sh_timer_config tmu1_platform_data = {
  93. .channels_mask = 3,
  94. };
  95. static struct resource tmu1_resources[] = {
  96. DEFINE_RES_MEM(0xfe100000, 0x20),
  97. DEFINE_RES_IRQ(evt2irq(0xb00)),
  98. DEFINE_RES_IRQ(evt2irq(0xb80)),
  99. };
  100. static struct platform_device tmu1_device = {
  101. .name = "sh-tmu",
  102. .id = 1,
  103. .dev = {
  104. .platform_data = &tmu1_platform_data,
  105. },
  106. .resource = tmu1_resources,
  107. .num_resources = ARRAY_SIZE(tmu1_resources),
  108. };
  109. #endif
  110. static struct platform_device *sh7750_devices[] __initdata = {
  111. &rtc_device,
  112. &tmu0_device,
  113. #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  114. defined(CONFIG_CPU_SUBTYPE_SH7751) || \
  115. defined(CONFIG_CPU_SUBTYPE_SH7751R)
  116. &tmu1_device,
  117. #endif
  118. };
  119. static int __init sh7750_devices_setup(void)
  120. {
  121. if (mach_is_rts7751r2d()) {
  122. platform_device_register(&scif_device);
  123. } else {
  124. platform_device_register(&sci_device);
  125. platform_device_register(&scif_device);
  126. }
  127. return platform_add_devices(sh7750_devices,
  128. ARRAY_SIZE(sh7750_devices));
  129. }
  130. arch_initcall(sh7750_devices_setup);
  131. static struct platform_device *sh7750_early_devices[] __initdata = {
  132. &tmu0_device,
  133. #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  134. defined(CONFIG_CPU_SUBTYPE_SH7751) || \
  135. defined(CONFIG_CPU_SUBTYPE_SH7751R)
  136. &tmu1_device,
  137. #endif
  138. };
  139. void __init plat_early_device_setup(void)
  140. {
  141. struct platform_device *dev[1];
  142. if (mach_is_rts7751r2d()) {
  143. scif_platform_data.scscr |= SCSCR_CKE1;
  144. dev[0] = &scif_device;
  145. early_platform_add_devices(dev, 1);
  146. } else {
  147. dev[0] = &sci_device;
  148. early_platform_add_devices(dev, 1);
  149. dev[0] = &scif_device;
  150. early_platform_add_devices(dev, 1);
  151. }
  152. early_platform_add_devices(sh7750_early_devices,
  153. ARRAY_SIZE(sh7750_early_devices));
  154. }
  155. enum {
  156. UNUSED = 0,
  157. /* interrupt sources */
  158. IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
  159. HUDI, GPIOI, DMAC,
  160. PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
  161. PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
  162. TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
  163. /* interrupt groups */
  164. PCIC1,
  165. };
  166. static struct intc_vect vectors[] __initdata = {
  167. INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
  168. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  169. INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
  170. INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
  171. INTC_VECT(RTC, 0x4c0),
  172. INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
  173. INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
  174. INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
  175. INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
  176. INTC_VECT(WDT, 0x560),
  177. INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
  178. };
  179. static struct intc_prio_reg prio_registers[] __initdata = {
  180. { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
  181. { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
  182. { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
  183. { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
  184. { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
  185. TMU4, TMU3,
  186. PCIC1, PCIC0_PCISERR } },
  187. };
  188. static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
  189. NULL, prio_registers, NULL);
  190. /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
  191. #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
  192. defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
  193. defined(CONFIG_CPU_SUBTYPE_SH7751) || \
  194. defined(CONFIG_CPU_SUBTYPE_SH7091)
  195. static struct intc_vect vectors_dma4[] __initdata = {
  196. INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
  197. INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
  198. INTC_VECT(DMAC, 0x6c0),
  199. };
  200. static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
  201. vectors_dma4, NULL,
  202. NULL, prio_registers, NULL);
  203. #endif
  204. /* SH7750R and SH7751R both have 8-channel DMA controllers */
  205. #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
  206. static struct intc_vect vectors_dma8[] __initdata = {
  207. INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
  208. INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
  209. INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
  210. INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
  211. INTC_VECT(DMAC, 0x6c0),
  212. };
  213. static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
  214. vectors_dma8, NULL,
  215. NULL, prio_registers, NULL);
  216. #endif
  217. /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
  218. #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  219. defined(CONFIG_CPU_SUBTYPE_SH7751) || \
  220. defined(CONFIG_CPU_SUBTYPE_SH7751R)
  221. static struct intc_vect vectors_tmu34[] __initdata = {
  222. INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
  223. };
  224. static struct intc_mask_reg mask_registers[] __initdata = {
  225. { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
  226. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  227. 0, 0, 0, 0, 0, 0, TMU4, TMU3,
  228. PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
  229. PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
  230. PCIC1_PCIDMA3, PCIC0_PCISERR } },
  231. };
  232. static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
  233. vectors_tmu34, NULL,
  234. mask_registers, prio_registers, NULL);
  235. #endif
  236. /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
  237. static struct intc_vect vectors_irlm[] __initdata = {
  238. INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
  239. INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
  240. };
  241. static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
  242. NULL, prio_registers, NULL);
  243. /* SH7751 and SH7751R both have PCI */
  244. #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
  245. static struct intc_vect vectors_pci[] __initdata = {
  246. INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
  247. INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
  248. INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
  249. INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
  250. };
  251. static struct intc_group groups_pci[] __initdata = {
  252. INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
  253. PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
  254. };
  255. static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
  256. mask_registers, prio_registers, NULL);
  257. #endif
  258. #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
  259. defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
  260. defined(CONFIG_CPU_SUBTYPE_SH7091)
  261. void __init plat_irq_setup(void)
  262. {
  263. /*
  264. * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
  265. * see below..
  266. */
  267. register_intc_controller(&intc_desc);
  268. register_intc_controller(&intc_desc_dma4);
  269. }
  270. #endif
  271. #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
  272. void __init plat_irq_setup(void)
  273. {
  274. register_intc_controller(&intc_desc);
  275. register_intc_controller(&intc_desc_dma8);
  276. register_intc_controller(&intc_desc_tmu34);
  277. }
  278. #endif
  279. #if defined(CONFIG_CPU_SUBTYPE_SH7751)
  280. void __init plat_irq_setup(void)
  281. {
  282. register_intc_controller(&intc_desc);
  283. register_intc_controller(&intc_desc_dma4);
  284. register_intc_controller(&intc_desc_tmu34);
  285. register_intc_controller(&intc_desc_pci);
  286. }
  287. #endif
  288. #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
  289. void __init plat_irq_setup(void)
  290. {
  291. register_intc_controller(&intc_desc);
  292. register_intc_controller(&intc_desc_dma8);
  293. register_intc_controller(&intc_desc_tmu34);
  294. register_intc_controller(&intc_desc_pci);
  295. }
  296. #endif
  297. #define INTC_ICR 0xffd00000UL
  298. #define INTC_ICR_IRLM (1<<7)
  299. void __init plat_irq_setup_pins(int mode)
  300. {
  301. #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
  302. BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
  303. return;
  304. #endif
  305. switch (mode) {
  306. case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
  307. __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
  308. register_intc_controller(&intc_desc_irlm);
  309. break;
  310. default:
  311. BUG();
  312. }
  313. }