s3c2410_udc.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * linux/drivers/usb/gadget/s3c2410_udc.c
  4. *
  5. * Samsung S3C24xx series on-chip full speed USB device controllers
  6. *
  7. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  8. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  9. */
  10. #define pr_fmt(fmt) "s3c2410_udc: " fmt
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/delay.h>
  14. #include <linux/ioport.h>
  15. #include <linux/sched.h>
  16. #include <linux/slab.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/timer.h>
  20. #include <linux/list.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/clk.h>
  24. #include <linux/gpio.h>
  25. #include <linux/prefetch.h>
  26. #include <linux/io.h>
  27. #include <linux/debugfs.h>
  28. #include <linux/seq_file.h>
  29. #include <linux/usb.h>
  30. #include <linux/usb/gadget.h>
  31. #include <asm/byteorder.h>
  32. #include <asm/irq.h>
  33. #include <asm/unaligned.h>
  34. #include <mach/irqs.h>
  35. #include <mach/hardware.h>
  36. #include <plat/regs-udc.h>
  37. #include <linux/platform_data/usb-s3c2410_udc.h>
  38. #include "s3c2410_udc.h"
  39. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  40. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  41. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  42. static const char gadget_name[] = "s3c2410_udc";
  43. static const char driver_desc[] = DRIVER_DESC;
  44. static struct s3c2410_udc *the_controller;
  45. static struct clk *udc_clock;
  46. static struct clk *usb_bus_clock;
  47. static void __iomem *base_addr;
  48. static u64 rsrc_start;
  49. static u64 rsrc_len;
  50. static struct dentry *s3c2410_udc_debugfs_root;
  51. static inline u32 udc_read(u32 reg)
  52. {
  53. return readb(base_addr + reg);
  54. }
  55. static inline void udc_write(u32 value, u32 reg)
  56. {
  57. writeb(value, base_addr + reg);
  58. }
  59. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  60. {
  61. writeb(value, base + reg);
  62. }
  63. static struct s3c2410_udc_mach_info *udc_info;
  64. /*************************** DEBUG FUNCTION ***************************/
  65. #define DEBUG_NORMAL 1
  66. #define DEBUG_VERBOSE 2
  67. #ifdef CONFIG_USB_S3C2410_DEBUG
  68. #define USB_S3C2410_DEBUG_LEVEL 0
  69. static uint32_t s3c2410_ticks = 0;
  70. __printf(2, 3)
  71. static void dprintk(int level, const char *fmt, ...)
  72. {
  73. static long prevticks;
  74. static int invocation;
  75. struct va_format vaf;
  76. va_list args;
  77. if (level > USB_S3C2410_DEBUG_LEVEL)
  78. return;
  79. va_start(args, fmt);
  80. vaf.fmt = fmt;
  81. vaf.va = &args;
  82. if (s3c2410_ticks != prevticks) {
  83. prevticks = s3c2410_ticks;
  84. invocation = 0;
  85. }
  86. pr_debug("%1lu.%02d USB: %pV", prevticks, invocation++, &vaf);
  87. va_end(args);
  88. }
  89. #else
  90. __printf(2, 3)
  91. static void dprintk(int level, const char *fmt, ...)
  92. {
  93. }
  94. #endif
  95. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  96. {
  97. u32 addr_reg, pwr_reg, ep_int_reg, usb_int_reg;
  98. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  99. u32 ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2;
  100. u32 ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2;
  101. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  102. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  103. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  104. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  105. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  106. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  107. udc_write(0, S3C2410_UDC_INDEX_REG);
  108. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  109. udc_write(1, S3C2410_UDC_INDEX_REG);
  110. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  111. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  112. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  113. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  114. udc_write(2, S3C2410_UDC_INDEX_REG);
  115. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  116. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  117. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  118. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  119. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  120. "PWR_REG : 0x%04X\n"
  121. "EP_INT_REG : 0x%04X\n"
  122. "USB_INT_REG : 0x%04X\n"
  123. "EP_INT_EN_REG : 0x%04X\n"
  124. "USB_INT_EN_REG : 0x%04X\n"
  125. "EP0_CSR : 0x%04X\n"
  126. "EP1_I_CSR1 : 0x%04X\n"
  127. "EP1_I_CSR2 : 0x%04X\n"
  128. "EP1_O_CSR1 : 0x%04X\n"
  129. "EP1_O_CSR2 : 0x%04X\n"
  130. "EP2_I_CSR1 : 0x%04X\n"
  131. "EP2_I_CSR2 : 0x%04X\n"
  132. "EP2_O_CSR1 : 0x%04X\n"
  133. "EP2_O_CSR2 : 0x%04X\n",
  134. addr_reg, pwr_reg, ep_int_reg, usb_int_reg,
  135. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  136. ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2,
  137. ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2
  138. );
  139. return 0;
  140. }
  141. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  142. struct file *file)
  143. {
  144. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  145. }
  146. static const struct file_operations s3c2410_udc_debugfs_fops = {
  147. .open = s3c2410_udc_debugfs_fops_open,
  148. .read = seq_read,
  149. .llseek = seq_lseek,
  150. .release = single_release,
  151. .owner = THIS_MODULE,
  152. };
  153. /* io macros */
  154. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  155. {
  156. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  157. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  158. S3C2410_UDC_EP0_CSR_REG);
  159. }
  160. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  161. {
  162. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  163. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  164. }
  165. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  166. {
  167. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  168. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  169. }
  170. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  171. {
  172. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  173. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  174. }
  175. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  176. {
  177. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  178. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  179. }
  180. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  181. {
  182. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  183. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  184. }
  185. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  186. {
  187. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  188. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  189. | S3C2410_UDC_EP0_CSR_DE),
  190. S3C2410_UDC_EP0_CSR_REG);
  191. }
  192. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  193. {
  194. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  195. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  196. | S3C2410_UDC_EP0_CSR_DE),
  197. S3C2410_UDC_EP0_CSR_REG);
  198. }
  199. /*------------------------- I/O ----------------------------------*/
  200. /*
  201. * s3c2410_udc_done
  202. */
  203. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  204. struct s3c2410_request *req, int status)
  205. {
  206. unsigned halted = ep->halted;
  207. list_del_init(&req->queue);
  208. if (likely(req->req.status == -EINPROGRESS))
  209. req->req.status = status;
  210. else
  211. status = req->req.status;
  212. ep->halted = 1;
  213. usb_gadget_giveback_request(&ep->ep, &req->req);
  214. ep->halted = halted;
  215. }
  216. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  217. struct s3c2410_ep *ep, int status)
  218. {
  219. while (!list_empty(&ep->queue)) {
  220. struct s3c2410_request *req;
  221. req = list_entry(ep->queue.next, struct s3c2410_request,
  222. queue);
  223. s3c2410_udc_done(ep, req, status);
  224. }
  225. }
  226. static inline int s3c2410_udc_fifo_count_out(void)
  227. {
  228. int tmp;
  229. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  230. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  231. return tmp;
  232. }
  233. /*
  234. * s3c2410_udc_write_packet
  235. */
  236. static inline int s3c2410_udc_write_packet(int fifo,
  237. struct s3c2410_request *req,
  238. unsigned max)
  239. {
  240. unsigned len = min(req->req.length - req->req.actual, max);
  241. u8 *buf = req->req.buf + req->req.actual;
  242. prefetch(buf);
  243. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  244. req->req.actual, req->req.length, len, req->req.actual + len);
  245. req->req.actual += len;
  246. udelay(5);
  247. writesb(base_addr + fifo, buf, len);
  248. return len;
  249. }
  250. /*
  251. * s3c2410_udc_write_fifo
  252. *
  253. * return: 0 = still running, 1 = completed, negative = errno
  254. */
  255. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  256. struct s3c2410_request *req)
  257. {
  258. unsigned count;
  259. int is_last;
  260. u32 idx;
  261. int fifo_reg;
  262. u32 ep_csr;
  263. idx = ep->bEndpointAddress & 0x7F;
  264. switch (idx) {
  265. default:
  266. idx = 0;
  267. case 0:
  268. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  269. break;
  270. case 1:
  271. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  272. break;
  273. case 2:
  274. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  275. break;
  276. case 3:
  277. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  278. break;
  279. case 4:
  280. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  281. break;
  282. }
  283. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  284. /* last packet is often short (sometimes a zlp) */
  285. if (count != ep->ep.maxpacket)
  286. is_last = 1;
  287. else if (req->req.length != req->req.actual || req->req.zero)
  288. is_last = 0;
  289. else
  290. is_last = 2;
  291. /* Only ep0 debug messages are interesting */
  292. if (idx == 0)
  293. dprintk(DEBUG_NORMAL,
  294. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  295. idx, count, req->req.actual, req->req.length,
  296. is_last, req->req.zero);
  297. if (is_last) {
  298. /* The order is important. It prevents sending 2 packets
  299. * at the same time */
  300. if (idx == 0) {
  301. /* Reset signal => no need to say 'data sent' */
  302. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  303. & S3C2410_UDC_USBINT_RESET))
  304. s3c2410_udc_set_ep0_de_in(base_addr);
  305. ep->dev->ep0state = EP0_IDLE;
  306. } else {
  307. udc_write(idx, S3C2410_UDC_INDEX_REG);
  308. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  309. udc_write(idx, S3C2410_UDC_INDEX_REG);
  310. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  311. S3C2410_UDC_IN_CSR1_REG);
  312. }
  313. s3c2410_udc_done(ep, req, 0);
  314. is_last = 1;
  315. } else {
  316. if (idx == 0) {
  317. /* Reset signal => no need to say 'data sent' */
  318. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  319. & S3C2410_UDC_USBINT_RESET))
  320. s3c2410_udc_set_ep0_ipr(base_addr);
  321. } else {
  322. udc_write(idx, S3C2410_UDC_INDEX_REG);
  323. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  324. udc_write(idx, S3C2410_UDC_INDEX_REG);
  325. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  326. S3C2410_UDC_IN_CSR1_REG);
  327. }
  328. }
  329. return is_last;
  330. }
  331. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  332. struct s3c2410_request *req, unsigned avail)
  333. {
  334. unsigned len;
  335. len = min(req->req.length - req->req.actual, avail);
  336. req->req.actual += len;
  337. readsb(fifo + base_addr, buf, len);
  338. return len;
  339. }
  340. /*
  341. * return: 0 = still running, 1 = queue empty, negative = errno
  342. */
  343. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  344. struct s3c2410_request *req)
  345. {
  346. u8 *buf;
  347. u32 ep_csr;
  348. unsigned bufferspace;
  349. int is_last = 1;
  350. unsigned avail;
  351. int fifo_count = 0;
  352. u32 idx;
  353. int fifo_reg;
  354. idx = ep->bEndpointAddress & 0x7F;
  355. switch (idx) {
  356. default:
  357. idx = 0;
  358. case 0:
  359. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  360. break;
  361. case 1:
  362. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  363. break;
  364. case 2:
  365. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  366. break;
  367. case 3:
  368. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  369. break;
  370. case 4:
  371. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  372. break;
  373. }
  374. if (!req->req.length)
  375. return 1;
  376. buf = req->req.buf + req->req.actual;
  377. bufferspace = req->req.length - req->req.actual;
  378. if (!bufferspace) {
  379. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  380. return -1;
  381. }
  382. udc_write(idx, S3C2410_UDC_INDEX_REG);
  383. fifo_count = s3c2410_udc_fifo_count_out();
  384. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  385. if (fifo_count > ep->ep.maxpacket)
  386. avail = ep->ep.maxpacket;
  387. else
  388. avail = fifo_count;
  389. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  390. /* checking this with ep0 is not accurate as we already
  391. * read a control request
  392. **/
  393. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  394. is_last = 1;
  395. /* overflowed this request? flush extra data */
  396. if (fifo_count != avail)
  397. req->req.status = -EOVERFLOW;
  398. } else {
  399. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  400. }
  401. udc_write(idx, S3C2410_UDC_INDEX_REG);
  402. fifo_count = s3c2410_udc_fifo_count_out();
  403. /* Only ep0 debug messages are interesting */
  404. if (idx == 0)
  405. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  406. __func__, fifo_count, is_last);
  407. if (is_last) {
  408. if (idx == 0) {
  409. s3c2410_udc_set_ep0_de_out(base_addr);
  410. ep->dev->ep0state = EP0_IDLE;
  411. } else {
  412. udc_write(idx, S3C2410_UDC_INDEX_REG);
  413. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  414. udc_write(idx, S3C2410_UDC_INDEX_REG);
  415. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  416. S3C2410_UDC_OUT_CSR1_REG);
  417. }
  418. s3c2410_udc_done(ep, req, 0);
  419. } else {
  420. if (idx == 0) {
  421. s3c2410_udc_clear_ep0_opr(base_addr);
  422. } else {
  423. udc_write(idx, S3C2410_UDC_INDEX_REG);
  424. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  425. udc_write(idx, S3C2410_UDC_INDEX_REG);
  426. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  427. S3C2410_UDC_OUT_CSR1_REG);
  428. }
  429. }
  430. return is_last;
  431. }
  432. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  433. {
  434. unsigned char *outbuf = (unsigned char *)crq;
  435. int bytes_read = 0;
  436. udc_write(0, S3C2410_UDC_INDEX_REG);
  437. bytes_read = s3c2410_udc_fifo_count_out();
  438. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  439. if (bytes_read > sizeof(struct usb_ctrlrequest))
  440. bytes_read = sizeof(struct usb_ctrlrequest);
  441. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  442. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  443. bytes_read, crq->bRequest, crq->bRequestType,
  444. crq->wValue, crq->wIndex, crq->wLength);
  445. return bytes_read;
  446. }
  447. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  448. struct usb_ctrlrequest *crq)
  449. {
  450. u16 status = 0;
  451. u8 ep_num = crq->wIndex & 0x7F;
  452. u8 is_in = crq->wIndex & USB_DIR_IN;
  453. switch (crq->bRequestType & USB_RECIP_MASK) {
  454. case USB_RECIP_INTERFACE:
  455. break;
  456. case USB_RECIP_DEVICE:
  457. status = dev->devstatus;
  458. break;
  459. case USB_RECIP_ENDPOINT:
  460. if (ep_num > 4 || crq->wLength > 2)
  461. return 1;
  462. if (ep_num == 0) {
  463. udc_write(0, S3C2410_UDC_INDEX_REG);
  464. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  465. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  466. } else {
  467. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  468. if (is_in) {
  469. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  470. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  471. } else {
  472. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  473. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  474. }
  475. }
  476. status = status ? 1 : 0;
  477. break;
  478. default:
  479. return 1;
  480. }
  481. /* Seems to be needed to get it working. ouch :( */
  482. udelay(5);
  483. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  484. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  485. s3c2410_udc_set_ep0_de_in(base_addr);
  486. return 0;
  487. }
  488. /*------------------------- usb state machine -------------------------------*/
  489. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  490. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  491. struct s3c2410_ep *ep,
  492. struct usb_ctrlrequest *crq,
  493. u32 ep0csr)
  494. {
  495. int len, ret, tmp;
  496. /* start control request? */
  497. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  498. return;
  499. s3c2410_udc_nuke(dev, ep, -EPROTO);
  500. len = s3c2410_udc_read_fifo_crq(crq);
  501. if (len != sizeof(*crq)) {
  502. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  503. " wanted %d bytes got %d. Stalling out...\n",
  504. sizeof(*crq), len);
  505. s3c2410_udc_set_ep0_ss(base_addr);
  506. return;
  507. }
  508. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  509. crq->bRequest, crq->bRequestType, crq->wLength);
  510. /* cope with automagic for some standard requests. */
  511. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  512. == USB_TYPE_STANDARD;
  513. dev->req_config = 0;
  514. dev->req_pending = 1;
  515. switch (crq->bRequest) {
  516. case USB_REQ_SET_CONFIGURATION:
  517. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ...\n");
  518. if (crq->bRequestType == USB_RECIP_DEVICE) {
  519. dev->req_config = 1;
  520. s3c2410_udc_set_ep0_de_out(base_addr);
  521. }
  522. break;
  523. case USB_REQ_SET_INTERFACE:
  524. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ...\n");
  525. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  526. dev->req_config = 1;
  527. s3c2410_udc_set_ep0_de_out(base_addr);
  528. }
  529. break;
  530. case USB_REQ_SET_ADDRESS:
  531. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ...\n");
  532. if (crq->bRequestType == USB_RECIP_DEVICE) {
  533. tmp = crq->wValue & 0x7F;
  534. dev->address = tmp;
  535. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  536. S3C2410_UDC_FUNC_ADDR_REG);
  537. s3c2410_udc_set_ep0_de_out(base_addr);
  538. return;
  539. }
  540. break;
  541. case USB_REQ_GET_STATUS:
  542. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ...\n");
  543. s3c2410_udc_clear_ep0_opr(base_addr);
  544. if (dev->req_std) {
  545. if (!s3c2410_udc_get_status(dev, crq))
  546. return;
  547. }
  548. break;
  549. case USB_REQ_CLEAR_FEATURE:
  550. s3c2410_udc_clear_ep0_opr(base_addr);
  551. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  552. break;
  553. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  554. break;
  555. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  556. s3c2410_udc_set_ep0_de_out(base_addr);
  557. return;
  558. case USB_REQ_SET_FEATURE:
  559. s3c2410_udc_clear_ep0_opr(base_addr);
  560. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  561. break;
  562. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  563. break;
  564. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  565. s3c2410_udc_set_ep0_de_out(base_addr);
  566. return;
  567. default:
  568. s3c2410_udc_clear_ep0_opr(base_addr);
  569. break;
  570. }
  571. if (crq->bRequestType & USB_DIR_IN)
  572. dev->ep0state = EP0_IN_DATA_PHASE;
  573. else
  574. dev->ep0state = EP0_OUT_DATA_PHASE;
  575. if (!dev->driver)
  576. return;
  577. /* deliver the request to the gadget driver */
  578. ret = dev->driver->setup(&dev->gadget, crq);
  579. if (ret < 0) {
  580. if (dev->req_config) {
  581. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  582. crq->bRequest, ret);
  583. return;
  584. }
  585. if (ret == -EOPNOTSUPP)
  586. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  587. else
  588. dprintk(DEBUG_NORMAL,
  589. "dev->driver->setup failed. (%d)\n", ret);
  590. udelay(5);
  591. s3c2410_udc_set_ep0_ss(base_addr);
  592. s3c2410_udc_set_ep0_de_out(base_addr);
  593. dev->ep0state = EP0_IDLE;
  594. /* deferred i/o == no response yet */
  595. } else if (dev->req_pending) {
  596. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  597. dev->req_pending = 0;
  598. }
  599. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  600. }
  601. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  602. {
  603. u32 ep0csr;
  604. struct s3c2410_ep *ep = &dev->ep[0];
  605. struct s3c2410_request *req;
  606. struct usb_ctrlrequest crq;
  607. if (list_empty(&ep->queue))
  608. req = NULL;
  609. else
  610. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  611. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  612. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  613. udc_write(0, S3C2410_UDC_INDEX_REG);
  614. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  615. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  616. ep0csr, ep0states[dev->ep0state]);
  617. /* clear stall status */
  618. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  619. s3c2410_udc_nuke(dev, ep, -EPIPE);
  620. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  621. s3c2410_udc_clear_ep0_sst(base_addr);
  622. dev->ep0state = EP0_IDLE;
  623. return;
  624. }
  625. /* clear setup end */
  626. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  627. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  628. s3c2410_udc_nuke(dev, ep, 0);
  629. s3c2410_udc_clear_ep0_se(base_addr);
  630. dev->ep0state = EP0_IDLE;
  631. }
  632. switch (dev->ep0state) {
  633. case EP0_IDLE:
  634. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  635. break;
  636. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  637. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  638. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req)
  639. s3c2410_udc_write_fifo(ep, req);
  640. break;
  641. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  642. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  643. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req)
  644. s3c2410_udc_read_fifo(ep, req);
  645. break;
  646. case EP0_END_XFER:
  647. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  648. dev->ep0state = EP0_IDLE;
  649. break;
  650. case EP0_STALL:
  651. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  652. dev->ep0state = EP0_IDLE;
  653. break;
  654. }
  655. }
  656. /*
  657. * handle_ep - Manage I/O endpoints
  658. */
  659. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  660. {
  661. struct s3c2410_request *req;
  662. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  663. u32 ep_csr1;
  664. u32 idx;
  665. if (likely(!list_empty(&ep->queue)))
  666. req = list_entry(ep->queue.next,
  667. struct s3c2410_request, queue);
  668. else
  669. req = NULL;
  670. idx = ep->bEndpointAddress & 0x7F;
  671. if (is_in) {
  672. udc_write(idx, S3C2410_UDC_INDEX_REG);
  673. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  674. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  675. idx, ep_csr1, req ? 1 : 0);
  676. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  677. dprintk(DEBUG_VERBOSE, "st\n");
  678. udc_write(idx, S3C2410_UDC_INDEX_REG);
  679. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  680. S3C2410_UDC_IN_CSR1_REG);
  681. return;
  682. }
  683. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req)
  684. s3c2410_udc_write_fifo(ep, req);
  685. } else {
  686. udc_write(idx, S3C2410_UDC_INDEX_REG);
  687. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  688. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  689. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  690. udc_write(idx, S3C2410_UDC_INDEX_REG);
  691. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  692. S3C2410_UDC_OUT_CSR1_REG);
  693. return;
  694. }
  695. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req)
  696. s3c2410_udc_read_fifo(ep, req);
  697. }
  698. }
  699. #include <mach/regs-irq.h>
  700. /*
  701. * s3c2410_udc_irq - interrupt handler
  702. */
  703. static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
  704. {
  705. struct s3c2410_udc *dev = _dev;
  706. int usb_status;
  707. int usbd_status;
  708. int pwr_reg;
  709. int ep0csr;
  710. int i;
  711. u32 idx, idx2;
  712. unsigned long flags;
  713. spin_lock_irqsave(&dev->lock, flags);
  714. /* Driver connected ? */
  715. if (!dev->driver) {
  716. /* Clear interrupts */
  717. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  718. S3C2410_UDC_USB_INT_REG);
  719. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  720. S3C2410_UDC_EP_INT_REG);
  721. }
  722. /* Save index */
  723. idx = udc_read(S3C2410_UDC_INDEX_REG);
  724. /* Read status registers */
  725. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  726. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  727. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  728. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  729. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  730. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  731. usb_status, usbd_status, pwr_reg, ep0csr);
  732. /*
  733. * Now, handle interrupts. There's two types :
  734. * - Reset, Resume, Suspend coming -> usb_int_reg
  735. * - EP -> ep_int_reg
  736. */
  737. /* RESET */
  738. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  739. /* two kind of reset :
  740. * - reset start -> pwr reg = 8
  741. * - reset end -> pwr reg = 0
  742. **/
  743. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  744. ep0csr, pwr_reg);
  745. dev->gadget.speed = USB_SPEED_UNKNOWN;
  746. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  747. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  748. S3C2410_UDC_MAXP_REG);
  749. dev->address = 0;
  750. dev->ep0state = EP0_IDLE;
  751. dev->gadget.speed = USB_SPEED_FULL;
  752. /* clear interrupt */
  753. udc_write(S3C2410_UDC_USBINT_RESET,
  754. S3C2410_UDC_USB_INT_REG);
  755. udc_write(idx, S3C2410_UDC_INDEX_REG);
  756. spin_unlock_irqrestore(&dev->lock, flags);
  757. return IRQ_HANDLED;
  758. }
  759. /* RESUME */
  760. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  761. dprintk(DEBUG_NORMAL, "USB resume\n");
  762. /* clear interrupt */
  763. udc_write(S3C2410_UDC_USBINT_RESUME,
  764. S3C2410_UDC_USB_INT_REG);
  765. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  766. && dev->driver
  767. && dev->driver->resume)
  768. dev->driver->resume(&dev->gadget);
  769. }
  770. /* SUSPEND */
  771. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  772. dprintk(DEBUG_NORMAL, "USB suspend\n");
  773. /* clear interrupt */
  774. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  775. S3C2410_UDC_USB_INT_REG);
  776. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  777. && dev->driver
  778. && dev->driver->suspend)
  779. dev->driver->suspend(&dev->gadget);
  780. dev->ep0state = EP0_IDLE;
  781. }
  782. /* EP */
  783. /* control traffic */
  784. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  785. * generate an interrupt
  786. */
  787. if (usbd_status & S3C2410_UDC_INT_EP0) {
  788. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  789. /* Clear the interrupt bit by setting it to 1 */
  790. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  791. s3c2410_udc_handle_ep0(dev);
  792. }
  793. /* endpoint data transfers */
  794. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  795. u32 tmp = 1 << i;
  796. if (usbd_status & tmp) {
  797. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  798. /* Clear the interrupt bit by setting it to 1 */
  799. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  800. s3c2410_udc_handle_ep(&dev->ep[i]);
  801. }
  802. }
  803. /* what else causes this interrupt? a receive! who is it? */
  804. if (!usb_status && !usbd_status && !pwr_reg && !ep0csr) {
  805. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  806. idx2 = udc_read(S3C2410_UDC_INDEX_REG);
  807. udc_write(i, S3C2410_UDC_INDEX_REG);
  808. if (udc_read(S3C2410_UDC_OUT_CSR1_REG) & 0x1)
  809. s3c2410_udc_handle_ep(&dev->ep[i]);
  810. /* restore index */
  811. udc_write(idx2, S3C2410_UDC_INDEX_REG);
  812. }
  813. }
  814. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD);
  815. /* Restore old index */
  816. udc_write(idx, S3C2410_UDC_INDEX_REG);
  817. spin_unlock_irqrestore(&dev->lock, flags);
  818. return IRQ_HANDLED;
  819. }
  820. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  821. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  822. {
  823. return container_of(ep, struct s3c2410_ep, ep);
  824. }
  825. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  826. {
  827. return container_of(gadget, struct s3c2410_udc, gadget);
  828. }
  829. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  830. {
  831. return container_of(req, struct s3c2410_request, req);
  832. }
  833. /*
  834. * s3c2410_udc_ep_enable
  835. */
  836. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  837. const struct usb_endpoint_descriptor *desc)
  838. {
  839. struct s3c2410_udc *dev;
  840. struct s3c2410_ep *ep;
  841. u32 max, tmp;
  842. unsigned long flags;
  843. u32 csr1, csr2;
  844. u32 int_en_reg;
  845. ep = to_s3c2410_ep(_ep);
  846. if (!_ep || !desc
  847. || _ep->name == ep0name
  848. || desc->bDescriptorType != USB_DT_ENDPOINT)
  849. return -EINVAL;
  850. dev = ep->dev;
  851. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  852. return -ESHUTDOWN;
  853. max = usb_endpoint_maxp(desc);
  854. local_irq_save(flags);
  855. _ep->maxpacket = max;
  856. ep->ep.desc = desc;
  857. ep->halted = 0;
  858. ep->bEndpointAddress = desc->bEndpointAddress;
  859. /* set max packet */
  860. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  861. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  862. /* set type, direction, address; reset fifo counters */
  863. if (desc->bEndpointAddress & USB_DIR_IN) {
  864. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  865. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  866. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  867. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  868. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  869. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  870. } else {
  871. /* don't flush in fifo or it will cause endpoint interrupt */
  872. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  873. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  874. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  875. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  876. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  877. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  878. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  879. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  880. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  881. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  882. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  883. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  884. }
  885. /* enable irqs */
  886. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  887. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  888. /* print some debug message */
  889. tmp = desc->bEndpointAddress;
  890. dprintk(DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  891. _ep->name, ep->num, tmp,
  892. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  893. local_irq_restore(flags);
  894. s3c2410_udc_set_halt(_ep, 0);
  895. return 0;
  896. }
  897. /*
  898. * s3c2410_udc_ep_disable
  899. */
  900. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  901. {
  902. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  903. unsigned long flags;
  904. u32 int_en_reg;
  905. if (!_ep || !ep->ep.desc) {
  906. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  907. _ep ? ep->ep.name : NULL);
  908. return -EINVAL;
  909. }
  910. local_irq_save(flags);
  911. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  912. ep->ep.desc = NULL;
  913. ep->halted = 1;
  914. s3c2410_udc_nuke(ep->dev, ep, -ESHUTDOWN);
  915. /* disable irqs */
  916. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  917. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  918. local_irq_restore(flags);
  919. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  920. return 0;
  921. }
  922. /*
  923. * s3c2410_udc_alloc_request
  924. */
  925. static struct usb_request *
  926. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  927. {
  928. struct s3c2410_request *req;
  929. dprintk(DEBUG_VERBOSE, "%s(%p,%d)\n", __func__, _ep, mem_flags);
  930. if (!_ep)
  931. return NULL;
  932. req = kzalloc(sizeof(struct s3c2410_request), mem_flags);
  933. if (!req)
  934. return NULL;
  935. INIT_LIST_HEAD(&req->queue);
  936. return &req->req;
  937. }
  938. /*
  939. * s3c2410_udc_free_request
  940. */
  941. static void
  942. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  943. {
  944. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  945. struct s3c2410_request *req = to_s3c2410_req(_req);
  946. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  947. if (!ep || !_req || (!ep->ep.desc && _ep->name != ep0name))
  948. return;
  949. WARN_ON(!list_empty(&req->queue));
  950. kfree(req);
  951. }
  952. /*
  953. * s3c2410_udc_queue
  954. */
  955. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  956. gfp_t gfp_flags)
  957. {
  958. struct s3c2410_request *req = to_s3c2410_req(_req);
  959. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  960. struct s3c2410_udc *dev;
  961. u32 ep_csr = 0;
  962. int fifo_count = 0;
  963. unsigned long flags;
  964. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  965. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  966. return -EINVAL;
  967. }
  968. dev = ep->dev;
  969. if (unlikely(!dev->driver
  970. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  971. return -ESHUTDOWN;
  972. }
  973. local_irq_save(flags);
  974. if (unlikely(!_req || !_req->complete
  975. || !_req->buf || !list_empty(&req->queue))) {
  976. if (!_req)
  977. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  978. else {
  979. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  980. __func__, !_req->complete, !_req->buf,
  981. !list_empty(&req->queue));
  982. }
  983. local_irq_restore(flags);
  984. return -EINVAL;
  985. }
  986. _req->status = -EINPROGRESS;
  987. _req->actual = 0;
  988. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  989. __func__, ep->bEndpointAddress, _req->length);
  990. if (ep->bEndpointAddress) {
  991. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  992. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  993. ? S3C2410_UDC_IN_CSR1_REG
  994. : S3C2410_UDC_OUT_CSR1_REG);
  995. fifo_count = s3c2410_udc_fifo_count_out();
  996. } else {
  997. udc_write(0, S3C2410_UDC_INDEX_REG);
  998. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  999. fifo_count = s3c2410_udc_fifo_count_out();
  1000. }
  1001. /* kickstart this i/o queue? */
  1002. if (list_empty(&ep->queue) && !ep->halted) {
  1003. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1004. switch (dev->ep0state) {
  1005. case EP0_IN_DATA_PHASE:
  1006. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1007. && s3c2410_udc_write_fifo(ep,
  1008. req)) {
  1009. dev->ep0state = EP0_IDLE;
  1010. req = NULL;
  1011. }
  1012. break;
  1013. case EP0_OUT_DATA_PHASE:
  1014. if ((!_req->length)
  1015. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1016. && s3c2410_udc_read_fifo(ep,
  1017. req))) {
  1018. dev->ep0state = EP0_IDLE;
  1019. req = NULL;
  1020. }
  1021. break;
  1022. default:
  1023. local_irq_restore(flags);
  1024. return -EL2HLT;
  1025. }
  1026. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1027. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1028. && s3c2410_udc_write_fifo(ep, req)) {
  1029. req = NULL;
  1030. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1031. && fifo_count
  1032. && s3c2410_udc_read_fifo(ep, req)) {
  1033. req = NULL;
  1034. }
  1035. }
  1036. /* pio or dma irq handler advances the queue. */
  1037. if (likely(req))
  1038. list_add_tail(&req->queue, &ep->queue);
  1039. local_irq_restore(flags);
  1040. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1041. return 0;
  1042. }
  1043. /*
  1044. * s3c2410_udc_dequeue
  1045. */
  1046. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1047. {
  1048. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1049. struct s3c2410_udc *udc;
  1050. int retval = -EINVAL;
  1051. unsigned long flags;
  1052. struct s3c2410_request *req = NULL;
  1053. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1054. if (!the_controller->driver)
  1055. return -ESHUTDOWN;
  1056. if (!_ep || !_req)
  1057. return retval;
  1058. udc = to_s3c2410_udc(ep->gadget);
  1059. local_irq_save(flags);
  1060. list_for_each_entry(req, &ep->queue, queue) {
  1061. if (&req->req == _req) {
  1062. list_del_init(&req->queue);
  1063. _req->status = -ECONNRESET;
  1064. retval = 0;
  1065. break;
  1066. }
  1067. }
  1068. if (retval == 0) {
  1069. dprintk(DEBUG_VERBOSE,
  1070. "dequeued req %p from %s, len %d buf %p\n",
  1071. req, _ep->name, _req->length, _req->buf);
  1072. s3c2410_udc_done(ep, req, -ECONNRESET);
  1073. }
  1074. local_irq_restore(flags);
  1075. return retval;
  1076. }
  1077. /*
  1078. * s3c2410_udc_set_halt
  1079. */
  1080. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1081. {
  1082. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1083. u32 ep_csr = 0;
  1084. unsigned long flags;
  1085. u32 idx;
  1086. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  1087. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1088. return -EINVAL;
  1089. }
  1090. local_irq_save(flags);
  1091. idx = ep->bEndpointAddress & 0x7F;
  1092. if (idx == 0) {
  1093. s3c2410_udc_set_ep0_ss(base_addr);
  1094. s3c2410_udc_set_ep0_de_out(base_addr);
  1095. } else {
  1096. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1097. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1098. ? S3C2410_UDC_IN_CSR1_REG
  1099. : S3C2410_UDC_OUT_CSR1_REG);
  1100. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1101. if (value)
  1102. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1103. S3C2410_UDC_IN_CSR1_REG);
  1104. else {
  1105. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1106. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1107. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1108. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1109. }
  1110. } else {
  1111. if (value)
  1112. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1113. S3C2410_UDC_OUT_CSR1_REG);
  1114. else {
  1115. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1116. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1117. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1118. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1119. }
  1120. }
  1121. }
  1122. ep->halted = value ? 1 : 0;
  1123. local_irq_restore(flags);
  1124. return 0;
  1125. }
  1126. static const struct usb_ep_ops s3c2410_ep_ops = {
  1127. .enable = s3c2410_udc_ep_enable,
  1128. .disable = s3c2410_udc_ep_disable,
  1129. .alloc_request = s3c2410_udc_alloc_request,
  1130. .free_request = s3c2410_udc_free_request,
  1131. .queue = s3c2410_udc_queue,
  1132. .dequeue = s3c2410_udc_dequeue,
  1133. .set_halt = s3c2410_udc_set_halt,
  1134. };
  1135. /*------------------------- usb_gadget_ops ----------------------------------*/
  1136. /*
  1137. * s3c2410_udc_get_frame
  1138. */
  1139. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1140. {
  1141. int tmp;
  1142. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1143. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1144. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1145. return tmp;
  1146. }
  1147. /*
  1148. * s3c2410_udc_wakeup
  1149. */
  1150. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1151. {
  1152. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1153. return 0;
  1154. }
  1155. /*
  1156. * s3c2410_udc_set_selfpowered
  1157. */
  1158. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1159. {
  1160. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1161. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1162. gadget->is_selfpowered = (value != 0);
  1163. if (value)
  1164. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1165. else
  1166. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1167. return 0;
  1168. }
  1169. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1170. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1171. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1172. {
  1173. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1174. if (udc_info && (udc_info->udc_command ||
  1175. gpio_is_valid(udc_info->pullup_pin))) {
  1176. if (is_on)
  1177. s3c2410_udc_enable(udc);
  1178. else {
  1179. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1180. if (udc->driver && udc->driver->disconnect)
  1181. udc->driver->disconnect(&udc->gadget);
  1182. }
  1183. s3c2410_udc_disable(udc);
  1184. }
  1185. } else {
  1186. return -EOPNOTSUPP;
  1187. }
  1188. return 0;
  1189. }
  1190. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1191. {
  1192. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1193. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1194. udc->vbus = (is_active != 0);
  1195. s3c2410_udc_set_pullup(udc, is_active);
  1196. return 0;
  1197. }
  1198. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1199. {
  1200. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1201. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1202. s3c2410_udc_set_pullup(udc, is_on);
  1203. return 0;
  1204. }
  1205. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1206. {
  1207. struct s3c2410_udc *dev = _dev;
  1208. unsigned int value;
  1209. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1210. value = gpio_get_value(udc_info->vbus_pin) ? 1 : 0;
  1211. if (udc_info->vbus_pin_inverted)
  1212. value = !value;
  1213. if (value != dev->vbus)
  1214. s3c2410_udc_vbus_session(&dev->gadget, value);
  1215. return IRQ_HANDLED;
  1216. }
  1217. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1218. {
  1219. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1220. if (udc_info && udc_info->vbus_draw) {
  1221. udc_info->vbus_draw(ma);
  1222. return 0;
  1223. }
  1224. return -ENOTSUPP;
  1225. }
  1226. static int s3c2410_udc_start(struct usb_gadget *g,
  1227. struct usb_gadget_driver *driver);
  1228. static int s3c2410_udc_stop(struct usb_gadget *g);
  1229. static const struct usb_gadget_ops s3c2410_ops = {
  1230. .get_frame = s3c2410_udc_get_frame,
  1231. .wakeup = s3c2410_udc_wakeup,
  1232. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1233. .pullup = s3c2410_udc_pullup,
  1234. .vbus_session = s3c2410_udc_vbus_session,
  1235. .vbus_draw = s3c2410_vbus_draw,
  1236. .udc_start = s3c2410_udc_start,
  1237. .udc_stop = s3c2410_udc_stop,
  1238. };
  1239. static void s3c2410_udc_command(enum s3c2410_udc_cmd_e cmd)
  1240. {
  1241. if (!udc_info)
  1242. return;
  1243. if (udc_info->udc_command) {
  1244. udc_info->udc_command(cmd);
  1245. } else if (gpio_is_valid(udc_info->pullup_pin)) {
  1246. int value;
  1247. switch (cmd) {
  1248. case S3C2410_UDC_P_ENABLE:
  1249. value = 1;
  1250. break;
  1251. case S3C2410_UDC_P_DISABLE:
  1252. value = 0;
  1253. break;
  1254. default:
  1255. return;
  1256. }
  1257. value ^= udc_info->pullup_pin_inverted;
  1258. gpio_set_value(udc_info->pullup_pin, value);
  1259. }
  1260. }
  1261. /*------------------------- gadget driver handling---------------------------*/
  1262. /*
  1263. * s3c2410_udc_disable
  1264. */
  1265. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1266. {
  1267. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1268. /* Disable all interrupts */
  1269. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1270. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1271. /* Clear the interrupt registers */
  1272. udc_write(S3C2410_UDC_USBINT_RESET
  1273. | S3C2410_UDC_USBINT_RESUME
  1274. | S3C2410_UDC_USBINT_SUSPEND,
  1275. S3C2410_UDC_USB_INT_REG);
  1276. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1277. /* Good bye, cruel world */
  1278. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1279. /* Set speed to unknown */
  1280. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1281. }
  1282. /*
  1283. * s3c2410_udc_reinit
  1284. */
  1285. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1286. {
  1287. u32 i;
  1288. /* device/ep0 records init */
  1289. INIT_LIST_HEAD(&dev->gadget.ep_list);
  1290. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  1291. dev->ep0state = EP0_IDLE;
  1292. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1293. struct s3c2410_ep *ep = &dev->ep[i];
  1294. if (i != 0)
  1295. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1296. ep->dev = dev;
  1297. ep->ep.desc = NULL;
  1298. ep->halted = 0;
  1299. INIT_LIST_HEAD(&ep->queue);
  1300. usb_ep_set_maxpacket_limit(&ep->ep, ep->ep.maxpacket);
  1301. }
  1302. }
  1303. /*
  1304. * s3c2410_udc_enable
  1305. */
  1306. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1307. {
  1308. int i;
  1309. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1310. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1311. dev->gadget.speed = USB_SPEED_FULL;
  1312. /* Set MAXP for all endpoints */
  1313. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1314. udc_write(i, S3C2410_UDC_INDEX_REG);
  1315. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1316. S3C2410_UDC_MAXP_REG);
  1317. }
  1318. /* Set default power state */
  1319. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1320. /* Enable reset and suspend interrupt interrupts */
  1321. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1322. S3C2410_UDC_USB_INT_EN_REG);
  1323. /* Enable ep0 interrupt */
  1324. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1325. /* time to say "hello, world" */
  1326. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1327. }
  1328. static int s3c2410_udc_start(struct usb_gadget *g,
  1329. struct usb_gadget_driver *driver)
  1330. {
  1331. struct s3c2410_udc *udc = to_s3c2410(g);
  1332. dprintk(DEBUG_NORMAL, "%s() '%s'\n", __func__, driver->driver.name);
  1333. /* Hook the driver */
  1334. udc->driver = driver;
  1335. /* Enable udc */
  1336. s3c2410_udc_enable(udc);
  1337. return 0;
  1338. }
  1339. static int s3c2410_udc_stop(struct usb_gadget *g)
  1340. {
  1341. struct s3c2410_udc *udc = to_s3c2410(g);
  1342. udc->driver = NULL;
  1343. /* Disable udc */
  1344. s3c2410_udc_disable(udc);
  1345. return 0;
  1346. }
  1347. /*---------------------------------------------------------------------------*/
  1348. static struct s3c2410_udc memory = {
  1349. .gadget = {
  1350. .ops = &s3c2410_ops,
  1351. .ep0 = &memory.ep[0].ep,
  1352. .name = gadget_name,
  1353. .dev = {
  1354. .init_name = "gadget",
  1355. },
  1356. },
  1357. /* control endpoint */
  1358. .ep[0] = {
  1359. .num = 0,
  1360. .ep = {
  1361. .name = ep0name,
  1362. .ops = &s3c2410_ep_ops,
  1363. .maxpacket = EP0_FIFO_SIZE,
  1364. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
  1365. USB_EP_CAPS_DIR_ALL),
  1366. },
  1367. .dev = &memory,
  1368. },
  1369. /* first group of endpoints */
  1370. .ep[1] = {
  1371. .num = 1,
  1372. .ep = {
  1373. .name = "ep1-bulk",
  1374. .ops = &s3c2410_ep_ops,
  1375. .maxpacket = EP_FIFO_SIZE,
  1376. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1377. USB_EP_CAPS_DIR_ALL),
  1378. },
  1379. .dev = &memory,
  1380. .fifo_size = EP_FIFO_SIZE,
  1381. .bEndpointAddress = 1,
  1382. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1383. },
  1384. .ep[2] = {
  1385. .num = 2,
  1386. .ep = {
  1387. .name = "ep2-bulk",
  1388. .ops = &s3c2410_ep_ops,
  1389. .maxpacket = EP_FIFO_SIZE,
  1390. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1391. USB_EP_CAPS_DIR_ALL),
  1392. },
  1393. .dev = &memory,
  1394. .fifo_size = EP_FIFO_SIZE,
  1395. .bEndpointAddress = 2,
  1396. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1397. },
  1398. .ep[3] = {
  1399. .num = 3,
  1400. .ep = {
  1401. .name = "ep3-bulk",
  1402. .ops = &s3c2410_ep_ops,
  1403. .maxpacket = EP_FIFO_SIZE,
  1404. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1405. USB_EP_CAPS_DIR_ALL),
  1406. },
  1407. .dev = &memory,
  1408. .fifo_size = EP_FIFO_SIZE,
  1409. .bEndpointAddress = 3,
  1410. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1411. },
  1412. .ep[4] = {
  1413. .num = 4,
  1414. .ep = {
  1415. .name = "ep4-bulk",
  1416. .ops = &s3c2410_ep_ops,
  1417. .maxpacket = EP_FIFO_SIZE,
  1418. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1419. USB_EP_CAPS_DIR_ALL),
  1420. },
  1421. .dev = &memory,
  1422. .fifo_size = EP_FIFO_SIZE,
  1423. .bEndpointAddress = 4,
  1424. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1425. }
  1426. };
  1427. /*
  1428. * probe - binds to the platform device
  1429. */
  1430. static int s3c2410_udc_probe(struct platform_device *pdev)
  1431. {
  1432. struct s3c2410_udc *udc = &memory;
  1433. struct device *dev = &pdev->dev;
  1434. int retval;
  1435. int irq;
  1436. dev_dbg(dev, "%s()\n", __func__);
  1437. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1438. if (IS_ERR(usb_bus_clock)) {
  1439. dev_err(dev, "failed to get usb bus clock source\n");
  1440. return PTR_ERR(usb_bus_clock);
  1441. }
  1442. clk_prepare_enable(usb_bus_clock);
  1443. udc_clock = clk_get(NULL, "usb-device");
  1444. if (IS_ERR(udc_clock)) {
  1445. dev_err(dev, "failed to get udc clock source\n");
  1446. return PTR_ERR(udc_clock);
  1447. }
  1448. clk_prepare_enable(udc_clock);
  1449. mdelay(10);
  1450. dev_dbg(dev, "got and enabled clocks\n");
  1451. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1452. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1453. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1454. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1455. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1456. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1457. }
  1458. spin_lock_init(&udc->lock);
  1459. udc_info = dev_get_platdata(&pdev->dev);
  1460. rsrc_start = S3C2410_PA_USBDEV;
  1461. rsrc_len = S3C24XX_SZ_USBDEV;
  1462. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1463. return -EBUSY;
  1464. base_addr = ioremap(rsrc_start, rsrc_len);
  1465. if (!base_addr) {
  1466. retval = -ENOMEM;
  1467. goto err_mem;
  1468. }
  1469. the_controller = udc;
  1470. platform_set_drvdata(pdev, udc);
  1471. s3c2410_udc_disable(udc);
  1472. s3c2410_udc_reinit(udc);
  1473. /* irq setup after old hardware state is cleaned up */
  1474. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1475. 0, gadget_name, udc);
  1476. if (retval != 0) {
  1477. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1478. retval = -EBUSY;
  1479. goto err_map;
  1480. }
  1481. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1482. if (udc_info && udc_info->vbus_pin > 0) {
  1483. retval = gpio_request(udc_info->vbus_pin, "udc vbus");
  1484. if (retval < 0) {
  1485. dev_err(dev, "cannot claim vbus pin\n");
  1486. goto err_int;
  1487. }
  1488. irq = gpio_to_irq(udc_info->vbus_pin);
  1489. if (irq < 0) {
  1490. dev_err(dev, "no irq for gpio vbus pin\n");
  1491. retval = irq;
  1492. goto err_gpio_claim;
  1493. }
  1494. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1495. IRQF_TRIGGER_RISING
  1496. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1497. gadget_name, udc);
  1498. if (retval != 0) {
  1499. dev_err(dev, "can't get vbus irq %d, err %d\n",
  1500. irq, retval);
  1501. retval = -EBUSY;
  1502. goto err_gpio_claim;
  1503. }
  1504. dev_dbg(dev, "got irq %i\n", irq);
  1505. } else {
  1506. udc->vbus = 1;
  1507. }
  1508. if (udc_info && !udc_info->udc_command &&
  1509. gpio_is_valid(udc_info->pullup_pin)) {
  1510. retval = gpio_request_one(udc_info->pullup_pin,
  1511. udc_info->vbus_pin_inverted ?
  1512. GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
  1513. "udc pullup");
  1514. if (retval)
  1515. goto err_vbus_irq;
  1516. }
  1517. retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1518. if (retval)
  1519. goto err_add_udc;
  1520. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1521. s3c2410_udc_debugfs_root, udc,
  1522. &s3c2410_udc_debugfs_fops);
  1523. dev_dbg(dev, "probe ok\n");
  1524. return 0;
  1525. err_add_udc:
  1526. if (udc_info && !udc_info->udc_command &&
  1527. gpio_is_valid(udc_info->pullup_pin))
  1528. gpio_free(udc_info->pullup_pin);
  1529. err_vbus_irq:
  1530. if (udc_info && udc_info->vbus_pin > 0)
  1531. free_irq(gpio_to_irq(udc_info->vbus_pin), udc);
  1532. err_gpio_claim:
  1533. if (udc_info && udc_info->vbus_pin > 0)
  1534. gpio_free(udc_info->vbus_pin);
  1535. err_int:
  1536. free_irq(IRQ_USBD, udc);
  1537. err_map:
  1538. iounmap(base_addr);
  1539. err_mem:
  1540. release_mem_region(rsrc_start, rsrc_len);
  1541. return retval;
  1542. }
  1543. /*
  1544. * s3c2410_udc_remove
  1545. */
  1546. static int s3c2410_udc_remove(struct platform_device *pdev)
  1547. {
  1548. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1549. unsigned int irq;
  1550. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1551. if (udc->driver)
  1552. return -EBUSY;
  1553. usb_del_gadget_udc(&udc->gadget);
  1554. debugfs_remove(udc->regs_info);
  1555. if (udc_info && !udc_info->udc_command &&
  1556. gpio_is_valid(udc_info->pullup_pin))
  1557. gpio_free(udc_info->pullup_pin);
  1558. if (udc_info && udc_info->vbus_pin > 0) {
  1559. irq = gpio_to_irq(udc_info->vbus_pin);
  1560. free_irq(irq, udc);
  1561. }
  1562. free_irq(IRQ_USBD, udc);
  1563. iounmap(base_addr);
  1564. release_mem_region(rsrc_start, rsrc_len);
  1565. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1566. clk_disable_unprepare(udc_clock);
  1567. clk_put(udc_clock);
  1568. udc_clock = NULL;
  1569. }
  1570. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1571. clk_disable_unprepare(usb_bus_clock);
  1572. clk_put(usb_bus_clock);
  1573. usb_bus_clock = NULL;
  1574. }
  1575. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1576. return 0;
  1577. }
  1578. #ifdef CONFIG_PM
  1579. static int
  1580. s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1581. {
  1582. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1583. return 0;
  1584. }
  1585. static int s3c2410_udc_resume(struct platform_device *pdev)
  1586. {
  1587. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1588. return 0;
  1589. }
  1590. #else
  1591. #define s3c2410_udc_suspend NULL
  1592. #define s3c2410_udc_resume NULL
  1593. #endif
  1594. static const struct platform_device_id s3c_udc_ids[] = {
  1595. { "s3c2410-usbgadget", },
  1596. { "s3c2440-usbgadget", },
  1597. { }
  1598. };
  1599. MODULE_DEVICE_TABLE(platform, s3c_udc_ids);
  1600. static struct platform_driver udc_driver_24x0 = {
  1601. .driver = {
  1602. .name = "s3c24x0-usbgadget",
  1603. },
  1604. .probe = s3c2410_udc_probe,
  1605. .remove = s3c2410_udc_remove,
  1606. .suspend = s3c2410_udc_suspend,
  1607. .resume = s3c2410_udc_resume,
  1608. .id_table = s3c_udc_ids,
  1609. };
  1610. static int __init udc_init(void)
  1611. {
  1612. int retval;
  1613. dprintk(DEBUG_NORMAL, "%s\n", gadget_name);
  1614. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1615. retval = platform_driver_register(&udc_driver_24x0);
  1616. if (retval)
  1617. goto err;
  1618. return 0;
  1619. err:
  1620. debugfs_remove(s3c2410_udc_debugfs_root);
  1621. return retval;
  1622. }
  1623. static void __exit udc_exit(void)
  1624. {
  1625. platform_driver_unregister(&udc_driver_24x0);
  1626. debugfs_remove_recursive(s3c2410_udc_debugfs_root);
  1627. }
  1628. module_init(udc_init);
  1629. module_exit(udc_exit);
  1630. MODULE_AUTHOR(DRIVER_AUTHOR);
  1631. MODULE_DESCRIPTION(DRIVER_DESC);
  1632. MODULE_LICENSE("GPL");