core_apecs.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/alpha/kernel/core_apecs.c
  4. *
  5. * Rewritten for Apecs from the lca.c from:
  6. *
  7. * Written by David Mosberger (davidm@cs.arizona.edu) with some code
  8. * taken from Dave Rusling's (david.rusling@reo.mts.dec.com) 32-bit
  9. * bios code.
  10. *
  11. * Code common to all APECS core logic chips.
  12. */
  13. #define __EXTERN_INLINE inline
  14. #include <asm/io.h>
  15. #include <asm/core_apecs.h>
  16. #undef __EXTERN_INLINE
  17. #include <linux/types.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <asm/ptrace.h>
  21. #include <asm/smp.h>
  22. #include <asm/mce.h>
  23. #include "proto.h"
  24. #include "pci_impl.h"
  25. /*
  26. * NOTE: Herein lie back-to-back mb instructions. They are magic.
  27. * One plausible explanation is that the i/o controller does not properly
  28. * handle the system transaction. Another involves timing. Ho hum.
  29. */
  30. /*
  31. * BIOS32-style PCI interface:
  32. */
  33. #define DEBUG_CONFIG 0
  34. #if DEBUG_CONFIG
  35. # define DBGC(args) printk args
  36. #else
  37. # define DBGC(args)
  38. #endif
  39. #define vuip volatile unsigned int *
  40. /*
  41. * Given a bus, device, and function number, compute resulting
  42. * configuration space address and setup the APECS_HAXR2 register
  43. * accordingly. It is therefore not safe to have concurrent
  44. * invocations to configuration space access routines, but there
  45. * really shouldn't be any need for this.
  46. *
  47. * Type 0:
  48. *
  49. * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  50. * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  51. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  52. * | | | | | | | | | | | | | | | | | | | | | | | |F|F|F|R|R|R|R|R|R|0|0|
  53. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  54. *
  55. * 31:11 Device select bit.
  56. * 10:8 Function number
  57. * 7:2 Register number
  58. *
  59. * Type 1:
  60. *
  61. * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  62. * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  63. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  64. * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
  65. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  66. *
  67. * 31:24 reserved
  68. * 23:16 bus number (8 bits = 128 possible buses)
  69. * 15:11 Device number (5 bits)
  70. * 10:8 function number
  71. * 7:2 register number
  72. *
  73. * Notes:
  74. * The function number selects which function of a multi-function device
  75. * (e.g., SCSI and Ethernet).
  76. *
  77. * The register selects a DWORD (32 bit) register offset. Hence it
  78. * doesn't get shifted by 2 bits as we want to "drop" the bottom two
  79. * bits.
  80. */
  81. static int
  82. mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
  83. unsigned long *pci_addr, unsigned char *type1)
  84. {
  85. unsigned long addr;
  86. u8 bus = pbus->number;
  87. DBGC(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x,"
  88. " pci_addr=0x%p, type1=0x%p)\n",
  89. bus, device_fn, where, pci_addr, type1));
  90. if (bus == 0) {
  91. int device = device_fn >> 3;
  92. /* type 0 configuration cycle: */
  93. if (device > 20) {
  94. DBGC(("mk_conf_addr: device (%d) > 20, returning -1\n",
  95. device));
  96. return -1;
  97. }
  98. *type1 = 0;
  99. addr = (device_fn << 8) | (where);
  100. } else {
  101. /* type 1 configuration cycle: */
  102. *type1 = 1;
  103. addr = (bus << 16) | (device_fn << 8) | (where);
  104. }
  105. *pci_addr = addr;
  106. DBGC(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
  107. return 0;
  108. }
  109. static unsigned int
  110. conf_read(unsigned long addr, unsigned char type1)
  111. {
  112. unsigned long flags;
  113. unsigned int stat0, value;
  114. unsigned int haxr2 = 0;
  115. local_irq_save(flags); /* avoid getting hit by machine check */
  116. DBGC(("conf_read(addr=0x%lx, type1=%d)\n", addr, type1));
  117. /* Reset status register to avoid losing errors. */
  118. stat0 = *(vuip)APECS_IOC_DCSR;
  119. *(vuip)APECS_IOC_DCSR = stat0;
  120. mb();
  121. DBGC(("conf_read: APECS DCSR was 0x%x\n", stat0));
  122. /* If Type1 access, must set HAE #2. */
  123. if (type1) {
  124. haxr2 = *(vuip)APECS_IOC_HAXR2;
  125. mb();
  126. *(vuip)APECS_IOC_HAXR2 = haxr2 | 1;
  127. DBGC(("conf_read: TYPE1 access\n"));
  128. }
  129. draina();
  130. mcheck_expected(0) = 1;
  131. mcheck_taken(0) = 0;
  132. mb();
  133. /* Access configuration space. */
  134. /* Some SRMs step on these registers during a machine check. */
  135. asm volatile("ldl %0,%1; mb; mb" : "=r"(value) : "m"(*(vuip)addr)
  136. : "$9", "$10", "$11", "$12", "$13", "$14", "memory");
  137. if (mcheck_taken(0)) {
  138. mcheck_taken(0) = 0;
  139. value = 0xffffffffU;
  140. mb();
  141. }
  142. mcheck_expected(0) = 0;
  143. mb();
  144. #if 1
  145. /*
  146. * david.rusling@reo.mts.dec.com. This code is needed for the
  147. * EB64+ as it does not generate a machine check (why I don't
  148. * know). When we build kernels for one particular platform
  149. * then we can make this conditional on the type.
  150. */
  151. draina();
  152. /* Now look for any errors. */
  153. stat0 = *(vuip)APECS_IOC_DCSR;
  154. DBGC(("conf_read: APECS DCSR after read 0x%x\n", stat0));
  155. /* Is any error bit set? */
  156. if (stat0 & 0xffe0U) {
  157. /* If not NDEV, print status. */
  158. if (!(stat0 & 0x0800)) {
  159. printk("apecs.c:conf_read: got stat0=%x\n", stat0);
  160. }
  161. /* Reset error status. */
  162. *(vuip)APECS_IOC_DCSR = stat0;
  163. mb();
  164. wrmces(0x7); /* reset machine check */
  165. value = 0xffffffff;
  166. }
  167. #endif
  168. /* If Type1 access, must reset HAE #2 so normal IO space ops work. */
  169. if (type1) {
  170. *(vuip)APECS_IOC_HAXR2 = haxr2 & ~1;
  171. mb();
  172. }
  173. local_irq_restore(flags);
  174. return value;
  175. }
  176. static void
  177. conf_write(unsigned long addr, unsigned int value, unsigned char type1)
  178. {
  179. unsigned long flags;
  180. unsigned int stat0;
  181. unsigned int haxr2 = 0;
  182. local_irq_save(flags); /* avoid getting hit by machine check */
  183. /* Reset status register to avoid losing errors. */
  184. stat0 = *(vuip)APECS_IOC_DCSR;
  185. *(vuip)APECS_IOC_DCSR = stat0;
  186. mb();
  187. /* If Type1 access, must set HAE #2. */
  188. if (type1) {
  189. haxr2 = *(vuip)APECS_IOC_HAXR2;
  190. mb();
  191. *(vuip)APECS_IOC_HAXR2 = haxr2 | 1;
  192. }
  193. draina();
  194. mcheck_expected(0) = 1;
  195. mb();
  196. /* Access configuration space. */
  197. *(vuip)addr = value;
  198. mb();
  199. mb(); /* magic */
  200. mcheck_expected(0) = 0;
  201. mb();
  202. #if 1
  203. /*
  204. * david.rusling@reo.mts.dec.com. This code is needed for the
  205. * EB64+ as it does not generate a machine check (why I don't
  206. * know). When we build kernels for one particular platform
  207. * then we can make this conditional on the type.
  208. */
  209. draina();
  210. /* Now look for any errors. */
  211. stat0 = *(vuip)APECS_IOC_DCSR;
  212. /* Is any error bit set? */
  213. if (stat0 & 0xffe0U) {
  214. /* If not NDEV, print status. */
  215. if (!(stat0 & 0x0800)) {
  216. printk("apecs.c:conf_write: got stat0=%x\n", stat0);
  217. }
  218. /* Reset error status. */
  219. *(vuip)APECS_IOC_DCSR = stat0;
  220. mb();
  221. wrmces(0x7); /* reset machine check */
  222. }
  223. #endif
  224. /* If Type1 access, must reset HAE #2 so normal IO space ops work. */
  225. if (type1) {
  226. *(vuip)APECS_IOC_HAXR2 = haxr2 & ~1;
  227. mb();
  228. }
  229. local_irq_restore(flags);
  230. }
  231. static int
  232. apecs_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  233. int size, u32 *value)
  234. {
  235. unsigned long addr, pci_addr;
  236. unsigned char type1;
  237. long mask;
  238. int shift;
  239. if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
  240. return PCIBIOS_DEVICE_NOT_FOUND;
  241. mask = (size - 1) * 8;
  242. shift = (where & 3) * 8;
  243. addr = (pci_addr << 5) + mask + APECS_CONF;
  244. *value = conf_read(addr, type1) >> (shift);
  245. return PCIBIOS_SUCCESSFUL;
  246. }
  247. static int
  248. apecs_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  249. int size, u32 value)
  250. {
  251. unsigned long addr, pci_addr;
  252. unsigned char type1;
  253. long mask;
  254. if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
  255. return PCIBIOS_DEVICE_NOT_FOUND;
  256. mask = (size - 1) * 8;
  257. addr = (pci_addr << 5) + mask + APECS_CONF;
  258. conf_write(addr, value << ((where & 3) * 8), type1);
  259. return PCIBIOS_SUCCESSFUL;
  260. }
  261. struct pci_ops apecs_pci_ops =
  262. {
  263. .read = apecs_read_config,
  264. .write = apecs_write_config,
  265. };
  266. void
  267. apecs_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
  268. {
  269. wmb();
  270. *(vip)APECS_IOC_TBIA = 0;
  271. mb();
  272. }
  273. void __init
  274. apecs_init_arch(void)
  275. {
  276. struct pci_controller *hose;
  277. /*
  278. * Create our single hose.
  279. */
  280. pci_isa_hose = hose = alloc_pci_controller();
  281. hose->io_space = &ioport_resource;
  282. hose->mem_space = &iomem_resource;
  283. hose->index = 0;
  284. hose->sparse_mem_base = APECS_SPARSE_MEM - IDENT_ADDR;
  285. hose->dense_mem_base = APECS_DENSE_MEM - IDENT_ADDR;
  286. hose->sparse_io_base = APECS_IO - IDENT_ADDR;
  287. hose->dense_io_base = 0;
  288. /*
  289. * Set up the PCI to main memory translation windows.
  290. *
  291. * Window 1 is direct access 1GB at 1GB
  292. * Window 2 is scatter-gather 8MB at 8MB (for isa)
  293. */
  294. hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
  295. hose->sg_pci = NULL;
  296. __direct_map_base = 0x40000000;
  297. __direct_map_size = 0x40000000;
  298. *(vuip)APECS_IOC_PB1R = __direct_map_base | 0x00080000;
  299. *(vuip)APECS_IOC_PM1R = (__direct_map_size - 1) & 0xfff00000U;
  300. *(vuip)APECS_IOC_TB1R = 0;
  301. *(vuip)APECS_IOC_PB2R = hose->sg_isa->dma_base | 0x000c0000;
  302. *(vuip)APECS_IOC_PM2R = (hose->sg_isa->size - 1) & 0xfff00000;
  303. *(vuip)APECS_IOC_TB2R = virt_to_phys(hose->sg_isa->ptes) >> 1;
  304. apecs_pci_tbi(hose, 0, -1);
  305. /*
  306. * Finally, clear the HAXR2 register, which gets used
  307. * for PCI Config Space accesses. That is the way
  308. * we want to use it, and we do not want to depend on
  309. * what ARC or SRM might have left behind...
  310. */
  311. *(vuip)APECS_IOC_HAXR2 = 0;
  312. mb();
  313. }
  314. void
  315. apecs_pci_clr_err(void)
  316. {
  317. unsigned int jd;
  318. jd = *(vuip)APECS_IOC_DCSR;
  319. if (jd & 0xffe0L) {
  320. *(vuip)APECS_IOC_SEAR;
  321. *(vuip)APECS_IOC_DCSR = jd | 0xffe1L;
  322. mb();
  323. *(vuip)APECS_IOC_DCSR;
  324. }
  325. *(vuip)APECS_IOC_TBIA = (unsigned int)APECS_IOC_TBIA;
  326. mb();
  327. *(vuip)APECS_IOC_TBIA;
  328. }
  329. void
  330. apecs_machine_check(unsigned long vector, unsigned long la_ptr)
  331. {
  332. struct el_common *mchk_header;
  333. struct el_apecs_procdata *mchk_procdata;
  334. struct el_apecs_sysdata_mcheck *mchk_sysdata;
  335. mchk_header = (struct el_common *)la_ptr;
  336. mchk_procdata = (struct el_apecs_procdata *)
  337. (la_ptr + mchk_header->proc_offset
  338. - sizeof(mchk_procdata->paltemp));
  339. mchk_sysdata = (struct el_apecs_sysdata_mcheck *)
  340. (la_ptr + mchk_header->sys_offset);
  341. /* Clear the error before any reporting. */
  342. mb();
  343. mb(); /* magic */
  344. draina();
  345. apecs_pci_clr_err();
  346. wrmces(0x7); /* reset machine check pending flag */
  347. mb();
  348. process_mcheck_info(vector, la_ptr, "APECS",
  349. (mcheck_expected(0)
  350. && (mchk_sysdata->epic_dcsr & 0x0c00UL)));
  351. }