core_tsunami.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/alpha/kernel/core_tsunami.c
  4. *
  5. * Based on code written by David A. Rusling (david.rusling@reo.mts.dec.com).
  6. *
  7. * Code common to all TSUNAMI core logic chips.
  8. */
  9. #define __EXTERN_INLINE inline
  10. #include <asm/io.h>
  11. #include <asm/core_tsunami.h>
  12. #undef __EXTERN_INLINE
  13. #include <linux/module.h>
  14. #include <linux/types.h>
  15. #include <linux/pci.h>
  16. #include <linux/sched.h>
  17. #include <linux/init.h>
  18. #include <linux/bootmem.h>
  19. #include <asm/ptrace.h>
  20. #include <asm/smp.h>
  21. #include <asm/vga.h>
  22. #include "proto.h"
  23. #include "pci_impl.h"
  24. /* Save Tsunami configuration data as the console had it set up. */
  25. struct
  26. {
  27. unsigned long wsba[4];
  28. unsigned long wsm[4];
  29. unsigned long tba[4];
  30. } saved_config[2] __attribute__((common));
  31. /*
  32. * NOTE: Herein lie back-to-back mb instructions. They are magic.
  33. * One plausible explanation is that the I/O controller does not properly
  34. * handle the system transaction. Another involves timing. Ho hum.
  35. */
  36. /*
  37. * BIOS32-style PCI interface:
  38. */
  39. #define DEBUG_CONFIG 0
  40. #if DEBUG_CONFIG
  41. # define DBG_CFG(args) printk args
  42. #else
  43. # define DBG_CFG(args)
  44. #endif
  45. /*
  46. * Given a bus, device, and function number, compute resulting
  47. * configuration space address
  48. * accordingly. It is therefore not safe to have concurrent
  49. * invocations to configuration space access routines, but there
  50. * really shouldn't be any need for this.
  51. *
  52. * Note that all config space accesses use Type 1 address format.
  53. *
  54. * Note also that type 1 is determined by non-zero bus number.
  55. *
  56. * Type 1:
  57. *
  58. * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  59. * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  60. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  61. * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
  62. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  63. *
  64. * 31:24 reserved
  65. * 23:16 bus number (8 bits = 128 possible buses)
  66. * 15:11 Device number (5 bits)
  67. * 10:8 function number
  68. * 7:2 register number
  69. *
  70. * Notes:
  71. * The function number selects which function of a multi-function device
  72. * (e.g., SCSI and Ethernet).
  73. *
  74. * The register selects a DWORD (32 bit) register offset. Hence it
  75. * doesn't get shifted by 2 bits as we want to "drop" the bottom two
  76. * bits.
  77. */
  78. static int
  79. mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
  80. unsigned long *pci_addr, unsigned char *type1)
  81. {
  82. struct pci_controller *hose = pbus->sysdata;
  83. unsigned long addr;
  84. u8 bus = pbus->number;
  85. DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "
  86. "pci_addr=0x%p, type1=0x%p)\n",
  87. bus, device_fn, where, pci_addr, type1));
  88. if (!pbus->parent) /* No parent means peer PCI bus. */
  89. bus = 0;
  90. *type1 = (bus != 0);
  91. addr = (bus << 16) | (device_fn << 8) | where;
  92. addr |= hose->config_space_base;
  93. *pci_addr = addr;
  94. DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
  95. return 0;
  96. }
  97. static int
  98. tsunami_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  99. int size, u32 *value)
  100. {
  101. unsigned long addr;
  102. unsigned char type1;
  103. if (mk_conf_addr(bus, devfn, where, &addr, &type1))
  104. return PCIBIOS_DEVICE_NOT_FOUND;
  105. switch (size) {
  106. case 1:
  107. *value = __kernel_ldbu(*(vucp)addr);
  108. break;
  109. case 2:
  110. *value = __kernel_ldwu(*(vusp)addr);
  111. break;
  112. case 4:
  113. *value = *(vuip)addr;
  114. break;
  115. }
  116. return PCIBIOS_SUCCESSFUL;
  117. }
  118. static int
  119. tsunami_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  120. int size, u32 value)
  121. {
  122. unsigned long addr;
  123. unsigned char type1;
  124. if (mk_conf_addr(bus, devfn, where, &addr, &type1))
  125. return PCIBIOS_DEVICE_NOT_FOUND;
  126. switch (size) {
  127. case 1:
  128. __kernel_stb(value, *(vucp)addr);
  129. mb();
  130. __kernel_ldbu(*(vucp)addr);
  131. break;
  132. case 2:
  133. __kernel_stw(value, *(vusp)addr);
  134. mb();
  135. __kernel_ldwu(*(vusp)addr);
  136. break;
  137. case 4:
  138. *(vuip)addr = value;
  139. mb();
  140. *(vuip)addr;
  141. break;
  142. }
  143. return PCIBIOS_SUCCESSFUL;
  144. }
  145. struct pci_ops tsunami_pci_ops =
  146. {
  147. .read = tsunami_read_config,
  148. .write = tsunami_write_config,
  149. };
  150. void
  151. tsunami_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
  152. {
  153. tsunami_pchip *pchip = hose->index ? TSUNAMI_pchip1 : TSUNAMI_pchip0;
  154. volatile unsigned long *csr;
  155. unsigned long value;
  156. /* We can invalidate up to 8 tlb entries in a go. The flush
  157. matches against <31:16> in the pci address. */
  158. csr = &pchip->tlbia.csr;
  159. if (((start ^ end) & 0xffff0000) == 0)
  160. csr = &pchip->tlbiv.csr;
  161. /* For TBIA, it doesn't matter what value we write. For TBI,
  162. it's the shifted tag bits. */
  163. value = (start & 0xffff0000) >> 12;
  164. *csr = value;
  165. mb();
  166. *csr;
  167. }
  168. #ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI
  169. static long __init
  170. tsunami_probe_read(volatile unsigned long *vaddr)
  171. {
  172. long dont_care, probe_result;
  173. int cpu = smp_processor_id();
  174. int s = swpipl(IPL_MCHECK - 1);
  175. mcheck_taken(cpu) = 0;
  176. mcheck_expected(cpu) = 1;
  177. mb();
  178. dont_care = *vaddr;
  179. draina();
  180. mcheck_expected(cpu) = 0;
  181. probe_result = !mcheck_taken(cpu);
  182. mcheck_taken(cpu) = 0;
  183. setipl(s);
  184. printk("dont_care == 0x%lx\n", dont_care);
  185. return probe_result;
  186. }
  187. static long __init
  188. tsunami_probe_write(volatile unsigned long *vaddr)
  189. {
  190. long true_contents, probe_result = 1;
  191. TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */
  192. true_contents = *vaddr;
  193. *vaddr = 0;
  194. draina();
  195. if (TSUNAMI_cchip->misc.csr & (1L << 28)) {
  196. int source = (TSUNAMI_cchip->misc.csr >> 29) & 7;
  197. TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */
  198. probe_result = 0;
  199. printk("tsunami_probe_write: unit %d at 0x%016lx\n", source,
  200. (unsigned long)vaddr);
  201. }
  202. if (probe_result)
  203. *vaddr = true_contents;
  204. return probe_result;
  205. }
  206. #else
  207. #define tsunami_probe_read(ADDR) 1
  208. #endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */
  209. static void __init
  210. tsunami_init_one_pchip(tsunami_pchip *pchip, int index)
  211. {
  212. struct pci_controller *hose;
  213. if (tsunami_probe_read(&pchip->pctl.csr) == 0)
  214. return;
  215. hose = alloc_pci_controller();
  216. if (index == 0)
  217. pci_isa_hose = hose;
  218. hose->io_space = alloc_resource();
  219. hose->mem_space = alloc_resource();
  220. /* This is for userland consumption. For some reason, the 40-bit
  221. PIO bias that we use in the kernel through KSEG didn't work for
  222. the page table based user mappings. So make sure we get the
  223. 43-bit PIO bias. */
  224. hose->sparse_mem_base = 0;
  225. hose->sparse_io_base = 0;
  226. hose->dense_mem_base
  227. = (TSUNAMI_MEM(index) & 0xffffffffffL) | 0x80000000000L;
  228. hose->dense_io_base
  229. = (TSUNAMI_IO(index) & 0xffffffffffL) | 0x80000000000L;
  230. hose->config_space_base = TSUNAMI_CONF(index);
  231. hose->index = index;
  232. hose->io_space->start = TSUNAMI_IO(index) - TSUNAMI_IO_BIAS;
  233. hose->io_space->end = hose->io_space->start + TSUNAMI_IO_SPACE - 1;
  234. hose->io_space->name = pci_io_names[index];
  235. hose->io_space->flags = IORESOURCE_IO;
  236. hose->mem_space->start = TSUNAMI_MEM(index) - TSUNAMI_MEM_BIAS;
  237. hose->mem_space->end = hose->mem_space->start + 0xffffffff;
  238. hose->mem_space->name = pci_mem_names[index];
  239. hose->mem_space->flags = IORESOURCE_MEM;
  240. if (request_resource(&ioport_resource, hose->io_space) < 0)
  241. printk(KERN_ERR "Failed to request IO on hose %d\n", index);
  242. if (request_resource(&iomem_resource, hose->mem_space) < 0)
  243. printk(KERN_ERR "Failed to request MEM on hose %d\n", index);
  244. /*
  245. * Save the existing PCI window translations. SRM will
  246. * need them when we go to reboot.
  247. */
  248. saved_config[index].wsba[0] = pchip->wsba[0].csr;
  249. saved_config[index].wsm[0] = pchip->wsm[0].csr;
  250. saved_config[index].tba[0] = pchip->tba[0].csr;
  251. saved_config[index].wsba[1] = pchip->wsba[1].csr;
  252. saved_config[index].wsm[1] = pchip->wsm[1].csr;
  253. saved_config[index].tba[1] = pchip->tba[1].csr;
  254. saved_config[index].wsba[2] = pchip->wsba[2].csr;
  255. saved_config[index].wsm[2] = pchip->wsm[2].csr;
  256. saved_config[index].tba[2] = pchip->tba[2].csr;
  257. saved_config[index].wsba[3] = pchip->wsba[3].csr;
  258. saved_config[index].wsm[3] = pchip->wsm[3].csr;
  259. saved_config[index].tba[3] = pchip->tba[3].csr;
  260. /*
  261. * Set up the PCI to main memory translation windows.
  262. *
  263. * Note: Window 3 is scatter-gather only
  264. *
  265. * Window 0 is scatter-gather 8MB at 8MB (for isa)
  266. * Window 1 is scatter-gather (up to) 1GB at 1GB
  267. * Window 2 is direct access 2GB at 2GB
  268. *
  269. * NOTE: we need the align_entry settings for Acer devices on ES40,
  270. * specifically floppy and IDE when memory is larger than 2GB.
  271. */
  272. hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
  273. /* Initially set for 4 PTEs, but will be overridden to 64K for ISA. */
  274. hose->sg_isa->align_entry = 4;
  275. hose->sg_pci = iommu_arena_new(hose, 0x40000000,
  276. size_for_memory(0x40000000), 0);
  277. hose->sg_pci->align_entry = 4; /* Tsunami caches 4 PTEs at a time */
  278. __direct_map_base = 0x80000000;
  279. __direct_map_size = 0x80000000;
  280. pchip->wsba[0].csr = hose->sg_isa->dma_base | 3;
  281. pchip->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000;
  282. pchip->tba[0].csr = virt_to_phys(hose->sg_isa->ptes);
  283. pchip->wsba[1].csr = hose->sg_pci->dma_base | 3;
  284. pchip->wsm[1].csr = (hose->sg_pci->size - 1) & 0xfff00000;
  285. pchip->tba[1].csr = virt_to_phys(hose->sg_pci->ptes);
  286. pchip->wsba[2].csr = 0x80000000 | 1;
  287. pchip->wsm[2].csr = (0x80000000 - 1) & 0xfff00000;
  288. pchip->tba[2].csr = 0;
  289. pchip->wsba[3].csr = 0;
  290. /* Enable the Monster Window to make DAC pci64 possible. */
  291. pchip->pctl.csr |= pctl_m_mwin;
  292. tsunami_pci_tbi(hose, 0, -1);
  293. }
  294. void __iomem *
  295. tsunami_ioportmap(unsigned long addr)
  296. {
  297. FIXUP_IOADDR_VGA(addr);
  298. return (void __iomem *)(addr + TSUNAMI_IO_BIAS);
  299. }
  300. void __iomem *
  301. tsunami_ioremap(unsigned long addr, unsigned long size)
  302. {
  303. FIXUP_MEMADDR_VGA(addr);
  304. return (void __iomem *)(addr + TSUNAMI_MEM_BIAS);
  305. }
  306. #ifndef CONFIG_ALPHA_GENERIC
  307. EXPORT_SYMBOL(tsunami_ioportmap);
  308. EXPORT_SYMBOL(tsunami_ioremap);
  309. #endif
  310. void __init
  311. tsunami_init_arch(void)
  312. {
  313. #ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI
  314. unsigned long tmp;
  315. /* Ho hum.. init_arch is called before init_IRQ, but we need to be
  316. able to handle machine checks. So install the handler now. */
  317. wrent(entInt, 0);
  318. /* NXMs just don't matter to Tsunami--unless they make it
  319. choke completely. */
  320. tmp = (unsigned long)(TSUNAMI_cchip - 1);
  321. printk("%s: probing bogus address: 0x%016lx\n", __func__, bogus_addr);
  322. printk("\tprobe %s\n",
  323. tsunami_probe_write((unsigned long *)bogus_addr)
  324. ? "succeeded" : "failed");
  325. #endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */
  326. #if 0
  327. printk("%s: CChip registers:\n", __func__);
  328. printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr);
  329. printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr);
  330. printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr);
  331. printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr);
  332. printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr);
  333. printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr);
  334. printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr);
  335. printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr);
  336. printk("%s: DChip registers:\n");
  337. printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr);
  338. printk("%s: CSR_STR 0x%lx\n", __func__, TSUNAMI_dchip->str.csr);
  339. printk("%s: CSR_DREV 0x%lx\n", __func__, TSUNAMI_dchip->drev.csr);
  340. #endif
  341. /* With multiple PCI busses, we play with I/O as physical addrs. */
  342. ioport_resource.end = ~0UL;
  343. /* Find how many hoses we have, and initialize them. TSUNAMI
  344. and TYPHOON can have 2, but might only have 1 (DS10). */
  345. tsunami_init_one_pchip(TSUNAMI_pchip0, 0);
  346. if (TSUNAMI_cchip->csc.csr & 1L<<14)
  347. tsunami_init_one_pchip(TSUNAMI_pchip1, 1);
  348. /* Check for graphic console location (if any). */
  349. find_console_vga_hose();
  350. }
  351. static void
  352. tsunami_kill_one_pchip(tsunami_pchip *pchip, int index)
  353. {
  354. pchip->wsba[0].csr = saved_config[index].wsba[0];
  355. pchip->wsm[0].csr = saved_config[index].wsm[0];
  356. pchip->tba[0].csr = saved_config[index].tba[0];
  357. pchip->wsba[1].csr = saved_config[index].wsba[1];
  358. pchip->wsm[1].csr = saved_config[index].wsm[1];
  359. pchip->tba[1].csr = saved_config[index].tba[1];
  360. pchip->wsba[2].csr = saved_config[index].wsba[2];
  361. pchip->wsm[2].csr = saved_config[index].wsm[2];
  362. pchip->tba[2].csr = saved_config[index].tba[2];
  363. pchip->wsba[3].csr = saved_config[index].wsba[3];
  364. pchip->wsm[3].csr = saved_config[index].wsm[3];
  365. pchip->tba[3].csr = saved_config[index].tba[3];
  366. }
  367. void
  368. tsunami_kill_arch(int mode)
  369. {
  370. tsunami_kill_one_pchip(TSUNAMI_pchip0, 0);
  371. if (TSUNAMI_cchip->csc.csr & 1L<<14)
  372. tsunami_kill_one_pchip(TSUNAMI_pchip1, 1);
  373. }
  374. static inline void
  375. tsunami_pci_clr_err_1(tsunami_pchip *pchip)
  376. {
  377. pchip->perror.csr;
  378. pchip->perror.csr = 0x040;
  379. mb();
  380. pchip->perror.csr;
  381. }
  382. static inline void
  383. tsunami_pci_clr_err(void)
  384. {
  385. tsunami_pci_clr_err_1(TSUNAMI_pchip0);
  386. /* TSUNAMI and TYPHOON can have 2, but might only have 1 (DS10) */
  387. if (TSUNAMI_cchip->csc.csr & 1L<<14)
  388. tsunami_pci_clr_err_1(TSUNAMI_pchip1);
  389. }
  390. void
  391. tsunami_machine_check(unsigned long vector, unsigned long la_ptr)
  392. {
  393. /* Clear error before any reporting. */
  394. mb();
  395. mb(); /* magic */
  396. draina();
  397. tsunami_pci_clr_err();
  398. wrmces(0x7);
  399. mb();
  400. process_mcheck_info(vector, la_ptr, "TSUNAMI",
  401. mcheck_expected(smp_processor_id()));
  402. }