machvec_impl.h 5.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * linux/arch/alpha/kernel/machvec_impl.h
  4. *
  5. * Copyright (C) 1997, 1998 Richard Henderson
  6. *
  7. * This file has goodies to help simplify instantiation of machine vectors.
  8. */
  9. #include <asm/pgalloc.h>
  10. /* Whee. These systems don't have an HAE:
  11. IRONGATE, MARVEL, POLARIS, TSUNAMI, TITAN, WILDFIRE
  12. Fix things up for the GENERIC kernel by defining the HAE address
  13. to be that of the cache. Now we can read and write it as we like. ;-) */
  14. #define IRONGATE_HAE_ADDRESS (&alpha_mv.hae_cache)
  15. #define MARVEL_HAE_ADDRESS (&alpha_mv.hae_cache)
  16. #define POLARIS_HAE_ADDRESS (&alpha_mv.hae_cache)
  17. #define TSUNAMI_HAE_ADDRESS (&alpha_mv.hae_cache)
  18. #define TITAN_HAE_ADDRESS (&alpha_mv.hae_cache)
  19. #define WILDFIRE_HAE_ADDRESS (&alpha_mv.hae_cache)
  20. #ifdef CIA_ONE_HAE_WINDOW
  21. #define CIA_HAE_ADDRESS (&alpha_mv.hae_cache)
  22. #endif
  23. #ifdef MCPCIA_ONE_HAE_WINDOW
  24. #define MCPCIA_HAE_ADDRESS (&alpha_mv.hae_cache)
  25. #endif
  26. #ifdef T2_ONE_HAE_WINDOW
  27. #define T2_HAE_ADDRESS (&alpha_mv.hae_cache)
  28. #endif
  29. /* Only a few systems don't define IACK_SC, handling all interrupts through
  30. the SRM console. But splitting out that one case from IO() below
  31. seems like such a pain. Define this to get things to compile. */
  32. #define JENSEN_IACK_SC 1
  33. #define T2_IACK_SC 1
  34. #define WILDFIRE_IACK_SC 1 /* FIXME */
  35. /*
  36. * Some helpful macros for filling in the blanks.
  37. */
  38. #define CAT1(x,y) x##y
  39. #define CAT(x,y) CAT1(x,y)
  40. #define DO_DEFAULT_RTC .rtc_port = 0x70
  41. #define DO_EV4_MMU \
  42. .max_asn = EV4_MAX_ASN, \
  43. .mv_switch_mm = ev4_switch_mm, \
  44. .mv_activate_mm = ev4_activate_mm, \
  45. .mv_flush_tlb_current = ev4_flush_tlb_current, \
  46. .mv_flush_tlb_current_page = ev4_flush_tlb_current_page
  47. #define DO_EV5_MMU \
  48. .max_asn = EV5_MAX_ASN, \
  49. .mv_switch_mm = ev5_switch_mm, \
  50. .mv_activate_mm = ev5_activate_mm, \
  51. .mv_flush_tlb_current = ev5_flush_tlb_current, \
  52. .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
  53. #define DO_EV6_MMU \
  54. .max_asn = EV6_MAX_ASN, \
  55. .mv_switch_mm = ev5_switch_mm, \
  56. .mv_activate_mm = ev5_activate_mm, \
  57. .mv_flush_tlb_current = ev5_flush_tlb_current, \
  58. .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
  59. #define DO_EV7_MMU \
  60. .max_asn = EV6_MAX_ASN, \
  61. .mv_switch_mm = ev5_switch_mm, \
  62. .mv_activate_mm = ev5_activate_mm, \
  63. .mv_flush_tlb_current = ev5_flush_tlb_current, \
  64. .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
  65. #define IO_LITE(UP,low) \
  66. .hae_register = (unsigned long *) CAT(UP,_HAE_ADDRESS), \
  67. .iack_sc = CAT(UP,_IACK_SC), \
  68. .mv_ioread8 = CAT(low,_ioread8), \
  69. .mv_ioread16 = CAT(low,_ioread16), \
  70. .mv_ioread32 = CAT(low,_ioread32), \
  71. .mv_iowrite8 = CAT(low,_iowrite8), \
  72. .mv_iowrite16 = CAT(low,_iowrite16), \
  73. .mv_iowrite32 = CAT(low,_iowrite32), \
  74. .mv_readb = CAT(low,_readb), \
  75. .mv_readw = CAT(low,_readw), \
  76. .mv_readl = CAT(low,_readl), \
  77. .mv_readq = CAT(low,_readq), \
  78. .mv_writeb = CAT(low,_writeb), \
  79. .mv_writew = CAT(low,_writew), \
  80. .mv_writel = CAT(low,_writel), \
  81. .mv_writeq = CAT(low,_writeq), \
  82. .mv_ioportmap = CAT(low,_ioportmap), \
  83. .mv_ioremap = CAT(low,_ioremap), \
  84. .mv_iounmap = CAT(low,_iounmap), \
  85. .mv_is_ioaddr = CAT(low,_is_ioaddr), \
  86. .mv_is_mmio = CAT(low,_is_mmio) \
  87. #define IO(UP,low) \
  88. IO_LITE(UP,low), \
  89. .pci_ops = &CAT(low,_pci_ops), \
  90. .mv_pci_tbi = CAT(low,_pci_tbi)
  91. #define DO_APECS_IO IO(APECS,apecs)
  92. #define DO_CIA_IO IO(CIA,cia)
  93. #define DO_IRONGATE_IO IO(IRONGATE,irongate)
  94. #define DO_LCA_IO IO(LCA,lca)
  95. #define DO_MARVEL_IO IO(MARVEL,marvel)
  96. #define DO_MCPCIA_IO IO(MCPCIA,mcpcia)
  97. #define DO_POLARIS_IO IO(POLARIS,polaris)
  98. #define DO_T2_IO IO(T2,t2)
  99. #define DO_TSUNAMI_IO IO(TSUNAMI,tsunami)
  100. #define DO_TITAN_IO IO(TITAN,titan)
  101. #define DO_WILDFIRE_IO IO(WILDFIRE,wildfire)
  102. #define DO_PYXIS_IO IO_LITE(CIA,cia_bwx), \
  103. .pci_ops = &cia_pci_ops, \
  104. .mv_pci_tbi = cia_pci_tbi
  105. /*
  106. * In a GENERIC kernel, we have lots of these vectors floating about,
  107. * all but one of which we want to go away. In a non-GENERIC kernel,
  108. * we want only one, ever.
  109. *
  110. * Accomplish this in the GENERIC kernel by putting all of the vectors
  111. * in the .init.data section where they'll go away. We'll copy the
  112. * one we want to the real alpha_mv vector in setup_arch.
  113. *
  114. * Accomplish this in a non-GENERIC kernel by ifdef'ing out all but
  115. * one of the vectors, which will not reside in .init.data. We then
  116. * alias this one vector to alpha_mv, so no copy is needed.
  117. *
  118. * Upshot: set __initdata to nothing for non-GENERIC kernels.
  119. */
  120. #ifdef CONFIG_ALPHA_GENERIC
  121. #define __initmv __initdata
  122. #define ALIAS_MV(x)
  123. #else
  124. #define __initmv __refdata
  125. /* GCC actually has a syntax for defining aliases, but is under some
  126. delusion that you shouldn't be able to declare it extern somewhere
  127. else beforehand. Fine. We'll do it ourselves. */
  128. #if 0
  129. #define ALIAS_MV(system) \
  130. struct alpha_machine_vector alpha_mv __attribute__((alias(#system "_mv"))); \
  131. EXPORT_SYMBOL(alpha_mv);
  132. #else
  133. #define ALIAS_MV(system) \
  134. asm(".global alpha_mv\nalpha_mv = " #system "_mv"); \
  135. EXPORT_SYMBOL(alpha_mv);
  136. #endif
  137. #endif /* GENERIC */