rt305x.c 8.4 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify it
  3. * under the terms of the GNU General Public License version 2 as published
  4. * by the Free Software Foundation.
  5. *
  6. * Parts of this file are based on Ralink's 2.6.21 BSP
  7. *
  8. * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  9. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  10. * Copyright (C) 2013 John Crispin <john@phrozen.org>
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/bug.h>
  15. #include <asm/io.h>
  16. #include <asm/mipsregs.h>
  17. #include <asm/mach-ralink/ralink_regs.h>
  18. #include <asm/mach-ralink/rt305x.h>
  19. #include <asm/mach-ralink/pinmux.h>
  20. #include "common.h"
  21. static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
  22. static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
  23. static struct rt2880_pmx_func uartf_func[] = {
  24. FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
  25. FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
  26. FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
  27. FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
  28. FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
  29. FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
  30. FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
  31. };
  32. static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
  33. static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
  34. static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
  35. static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
  36. static struct rt2880_pmx_func rt5350_cs1_func[] = {
  37. FUNC("spi_cs1", 0, 27, 1),
  38. FUNC("wdg_cs1", 1, 27, 1),
  39. };
  40. static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
  41. static struct rt2880_pmx_func rt3352_rgmii_func[] = {
  42. FUNC("rgmii", 0, 24, 12)
  43. };
  44. static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
  45. static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
  46. static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
  47. static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
  48. static struct rt2880_pmx_group rt3050_pinmux_data[] = {
  49. GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
  50. GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
  51. GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
  52. RT305X_GPIO_MODE_UART0_SHIFT),
  53. GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
  54. GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
  55. GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
  56. GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
  57. GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
  58. { 0 }
  59. };
  60. static struct rt2880_pmx_group rt3352_pinmux_data[] = {
  61. GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
  62. GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
  63. GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
  64. RT305X_GPIO_MODE_UART0_SHIFT),
  65. GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
  66. GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
  67. GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
  68. GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
  69. GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
  70. GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
  71. GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
  72. { 0 }
  73. };
  74. static struct rt2880_pmx_group rt5350_pinmux_data[] = {
  75. GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
  76. GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
  77. GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
  78. RT305X_GPIO_MODE_UART0_SHIFT),
  79. GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
  80. GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
  81. GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
  82. GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
  83. { 0 }
  84. };
  85. static unsigned long rt5350_get_mem_size(void)
  86. {
  87. void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  88. unsigned long ret;
  89. u32 t;
  90. t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
  91. t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
  92. RT5350_SYSCFG0_DRAM_SIZE_MASK;
  93. switch (t) {
  94. case RT5350_SYSCFG0_DRAM_SIZE_2M:
  95. ret = 2;
  96. break;
  97. case RT5350_SYSCFG0_DRAM_SIZE_8M:
  98. ret = 8;
  99. break;
  100. case RT5350_SYSCFG0_DRAM_SIZE_16M:
  101. ret = 16;
  102. break;
  103. case RT5350_SYSCFG0_DRAM_SIZE_32M:
  104. ret = 32;
  105. break;
  106. case RT5350_SYSCFG0_DRAM_SIZE_64M:
  107. ret = 64;
  108. break;
  109. default:
  110. panic("rt5350: invalid DRAM size: %u", t);
  111. break;
  112. }
  113. return ret;
  114. }
  115. void __init ralink_clk_init(void)
  116. {
  117. unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
  118. unsigned long wmac_rate = 40000000;
  119. u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  120. if (soc_is_rt305x() || soc_is_rt3350()) {
  121. t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
  122. RT305X_SYSCFG_CPUCLK_MASK;
  123. switch (t) {
  124. case RT305X_SYSCFG_CPUCLK_LOW:
  125. cpu_rate = 320000000;
  126. break;
  127. case RT305X_SYSCFG_CPUCLK_HIGH:
  128. cpu_rate = 384000000;
  129. break;
  130. }
  131. sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
  132. } else if (soc_is_rt3352()) {
  133. t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
  134. RT3352_SYSCFG0_CPUCLK_MASK;
  135. switch (t) {
  136. case RT3352_SYSCFG0_CPUCLK_LOW:
  137. cpu_rate = 384000000;
  138. break;
  139. case RT3352_SYSCFG0_CPUCLK_HIGH:
  140. cpu_rate = 400000000;
  141. break;
  142. }
  143. sys_rate = wdt_rate = cpu_rate / 3;
  144. uart_rate = 40000000;
  145. } else if (soc_is_rt5350()) {
  146. t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
  147. RT5350_SYSCFG0_CPUCLK_MASK;
  148. switch (t) {
  149. case RT5350_SYSCFG0_CPUCLK_360:
  150. cpu_rate = 360000000;
  151. sys_rate = cpu_rate / 3;
  152. break;
  153. case RT5350_SYSCFG0_CPUCLK_320:
  154. cpu_rate = 320000000;
  155. sys_rate = cpu_rate / 4;
  156. break;
  157. case RT5350_SYSCFG0_CPUCLK_300:
  158. cpu_rate = 300000000;
  159. sys_rate = cpu_rate / 3;
  160. break;
  161. default:
  162. BUG();
  163. }
  164. uart_rate = 40000000;
  165. wdt_rate = sys_rate;
  166. } else {
  167. BUG();
  168. }
  169. if (soc_is_rt3352() || soc_is_rt5350()) {
  170. u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
  171. if (!(val & RT3352_CLKCFG0_XTAL_SEL))
  172. wmac_rate = 20000000;
  173. }
  174. ralink_clk_add("cpu", cpu_rate);
  175. ralink_clk_add("sys", sys_rate);
  176. ralink_clk_add("10000900.i2c", uart_rate);
  177. ralink_clk_add("10000a00.i2s", uart_rate);
  178. ralink_clk_add("10000b00.spi", sys_rate);
  179. ralink_clk_add("10000b40.spi", sys_rate);
  180. ralink_clk_add("10000100.timer", wdt_rate);
  181. ralink_clk_add("10000120.watchdog", wdt_rate);
  182. ralink_clk_add("10000500.uart", uart_rate);
  183. ralink_clk_add("10000c00.uartlite", uart_rate);
  184. ralink_clk_add("10100000.ethernet", sys_rate);
  185. ralink_clk_add("10180000.wmac", wmac_rate);
  186. }
  187. void __init ralink_of_remap(void)
  188. {
  189. rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
  190. rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
  191. if (!rt_sysc_membase || !rt_memc_membase)
  192. panic("Failed to remap core resources");
  193. }
  194. void prom_soc_init(struct ralink_soc_info *soc_info)
  195. {
  196. void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  197. unsigned char *name;
  198. u32 n0;
  199. u32 n1;
  200. u32 id;
  201. n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  202. n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  203. if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
  204. unsigned long icache_sets;
  205. icache_sets = (read_c0_config1() >> 22) & 7;
  206. if (icache_sets == 1) {
  207. ralink_soc = RT305X_SOC_RT3050;
  208. name = "RT3050";
  209. soc_info->compatible = "ralink,rt3050-soc";
  210. } else {
  211. ralink_soc = RT305X_SOC_RT3052;
  212. name = "RT3052";
  213. soc_info->compatible = "ralink,rt3052-soc";
  214. }
  215. } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
  216. ralink_soc = RT305X_SOC_RT3350;
  217. name = "RT3350";
  218. soc_info->compatible = "ralink,rt3350-soc";
  219. } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
  220. ralink_soc = RT305X_SOC_RT3352;
  221. name = "RT3352";
  222. soc_info->compatible = "ralink,rt3352-soc";
  223. } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
  224. ralink_soc = RT305X_SOC_RT5350;
  225. name = "RT5350";
  226. soc_info->compatible = "ralink,rt5350-soc";
  227. } else {
  228. panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1);
  229. }
  230. id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
  231. snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
  232. "Ralink %s id:%u rev:%u",
  233. name,
  234. (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  235. (id & CHIP_ID_REV_MASK));
  236. soc_info->mem_base = RT305X_SDRAM_BASE;
  237. if (soc_is_rt5350()) {
  238. soc_info->mem_size = rt5350_get_mem_size();
  239. rt2880_pinmux_data = rt5350_pinmux_data;
  240. } else if (soc_is_rt305x() || soc_is_rt3350()) {
  241. soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
  242. soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
  243. rt2880_pinmux_data = rt3050_pinmux_data;
  244. } else if (soc_is_rt3352()) {
  245. soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
  246. soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
  247. rt2880_pinmux_data = rt3352_pinmux_data;
  248. }
  249. }