hx170dec.c 21 KB

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  1. /*
  2. * On2/Hantro G1 decoder/pp driver. Single core version.
  3. *
  4. * Copyright (C) 2009 Hantro Products Oy.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  18. */
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/of.h>
  22. #include <linux/clk.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/io.h>
  25. #include <linux/err.h>
  26. #include <linux/miscdevice.h>
  27. #include <linux/fs.h>
  28. #include <linux/uaccess.h>
  29. #include <linux/sched.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/delay.h>
  32. #include "hx170dec.h"
  33. #include "vdec.h"
  34. #include "jpegdecapi.h"
  35. #include "jpegdeccontainer.h"
  36. struct vdec_device *vdec6731_global;
  37. unsigned int animation_jpegPhyaddr;
  38. unsigned int dis_decWidth;
  39. unsigned int dis_decHeight;
  40. unsigned int dis_format;
  41. static struct mfc_jpeg_context *vde_jpeg_context = NULL;
  42. #define MAX_ANIMFRAME_WIDTH 1920
  43. #define MAX_ANIMFRAME_HEIGHT 1088
  44. #define MAX_ANIMFRAME_SIZE (MAX_ANIMFRAME_WIDTH * MAX_ANIMFRAME_HEIGHT * 4)
  45. extern int ark_bootanimation_display_init(int width, int height, unsigned int yaddr,unsigned int uaddr,unsigned int vadd,unsigned int format);
  46. extern int ark_bootanimation_display_uninit(void);
  47. extern int ark_bootanimation_set_display_addr(unsigned int yaddr,unsigned int uaddr,unsigned int vaddr,unsigned int format);
  48. int get_bootanimation_status(void)
  49. {
  50. return vde_jpeg_context->anmation_stats;
  51. }
  52. EXPORT_SYMBOL(get_bootanimation_status);
  53. static inline void vdec_writel(const struct vdec_device *p, unsigned offset, u32 val)
  54. {
  55. writel(val, p->mmio_base + offset);
  56. }
  57. static inline u32 vdec_readl(const struct vdec_device *p, unsigned offset)
  58. {
  59. return readl(p->mmio_base + offset);
  60. }
  61. /**
  62. * Write a range of registers. First register is assumed to be
  63. * "Interrupt Register" and will be written last.
  64. */
  65. static int vdec_regs_write(struct vdec_device *p, int begin, int end,
  66. const struct core_desc *core)
  67. {
  68. int i;
  69. if (copy_from_user(&p->regs[begin], core->regs, (end - begin + 1) * 4))
  70. {
  71. dev_err(p->dev, "%s: copy_from_user failed\n", __func__);
  72. return -EFAULT;
  73. }
  74. for (i = end; i >= begin; i--)
  75. vdec_writel(p, 4 * i, p->regs[i]);
  76. return 0;
  77. }
  78. /**
  79. * Read a range of registers [begin..end]
  80. */
  81. static int vdec_regs_read(struct vdec_device *p, int begin, int end,
  82. const struct core_desc *core)
  83. {
  84. int i;
  85. for (i = end; i >= begin; i--)
  86. p->regs[i] = vdec_readl(p, 4 * i);
  87. if (copy_to_user(core->regs, &p->regs[begin], (end - begin + 1) * 4))
  88. {
  89. dev_err(p->dev, "%s: copy_to_user failed\n", __func__);
  90. return -EFAULT;
  91. }
  92. return 0;
  93. }
  94. //mfc jpeg decode
  95. #define MKTAG(a,b,c,d) ((a) | ((b) << 8) | ((c) << 16) | ((unsigned)(d) << 24))
  96. typedef struct {
  97. unsigned int magic;
  98. int hasBootlogo;
  99. int bootlogoDisplayTime;
  100. int aniCount;
  101. int aniWidth;
  102. int aniHeight;
  103. int aniFps;
  104. int aniDelayHideTime;
  105. int reserved[4];
  106. } BANIHEADER;
  107. static int mfc_jpeg_decode(unsigned int src_addr,unsigned int pvSrc_addr,
  108. unsigned int dest_addr, unsigned int pvDest_addr,
  109. unsigned int size)
  110. {
  111. int ret = 0;
  112. JpegDecInst decoder;
  113. JpegDecRet infoRet;
  114. JpegDecInput DecIn;
  115. JpegDecImageInfo DecImgInf;
  116. JpegDecOutput DecOut;
  117. infoRet = JpegDecInit(&decoder);
  118. if(infoRet !=JPEGDEC_OK) {
  119. printk("JpegDecInit failure %d.\n", infoRet);
  120. return -1;
  121. }
  122. DecIn.decImageType = JPEGDEC_IMAGE;
  123. DecIn.sliceMbSet = 0;
  124. DecIn.bufferSize = 0;
  125. DecIn.streamLength = size;
  126. DecIn.streamBuffer.busAddress= src_addr;
  127. DecIn.streamBuffer.pVirtualAddress = (u32*)pvSrc_addr;
  128. /* Get image information of the JFIF */
  129. infoRet = JpegDecGetImageInfo(decoder,
  130. &DecIn,
  131. &DecImgInf);
  132. if(infoRet !=JPEGDEC_OK)
  133. {
  134. printk("JpegDecGetImageInfo failure.\n");
  135. ret = -1;
  136. goto dec_end;
  137. }
  138. // printk("mfc_jpeg_decode outputWidth %d,outputHeight %d,outputFormat 0x%x\n",DecImgInf.outputWidth,DecImgInf.outputHeight,DecImgInf.outputFormat);
  139. dis_decWidth = DecImgInf.outputWidth;
  140. dis_decHeight=DecImgInf.outputHeight;
  141. dis_format = DecImgInf.outputFormat;
  142. DecIn.pictureBufferY.busAddress = dest_addr;
  143. DecIn.pictureBufferY.pVirtualAddress = (u32*)pvDest_addr;
  144. DecIn.pictureBufferCbCr.busAddress = dest_addr + DecImgInf.outputWidth * DecImgInf.outputHeight;
  145. DecIn.pictureBufferCbCr.pVirtualAddress = (u32*)(pvDest_addr + DecImgInf.outputWidth * DecImgInf.outputHeight);
  146. DecIn.pictureBufferCr.busAddress = 0;
  147. DecIn.pictureBufferCr.pVirtualAddress = 0;
  148. /* Decode JFIF */
  149. infoRet = JpegDecDecode(decoder, &DecIn, &DecOut);
  150. if(infoRet != JPEGDEC_FRAME_READY)
  151. {
  152. printk("JpegDecDecode failure, ret=%d\n", infoRet);
  153. ret = -1;
  154. goto dec_end;
  155. }
  156. dec_end:
  157. JpegDecRelease(decoder);
  158. return 0;
  159. }
  160. //extern int ark_carback_get_status(void);
  161. static void animation_dec_work(struct work_struct *work)
  162. {
  163. static unsigned int frame = 0;
  164. static int timeout_count = 0;
  165. struct mfc_jpeg_context *context = container_of(work, struct mfc_jpeg_context, animation_work);
  166. BANIHEADER *header = (BANIHEADER *) context->animation_data_virtaddr;
  167. unsigned int size =
  168. *(unsigned int *)(context->animation_data_virtaddr + context->animation_file_phyaddr -
  169. context->animation_data_phyaddr);
  170. struct vdec_device *p = vdec6731_global;
  171. if (timeout_count > 50) {
  172. printk(KERN_ALERT "%s Error! Dec timeout.\n", __FUNCTION__);
  173. context->animation_end = true;
  174. } else if (context->animation_file_phyaddr + size >= context->animation_data_phyaddr + context->animation_data_size
  175. && frame < header->aniCount + header->hasBootlogo ? 1 : 0) {
  176. printk(KERN_ALERT "%s Error! Animation data is beyond the mark.\n", __FUNCTION__);
  177. context->animation_end = true;
  178. }
  179. if (context->animation_end) {
  180. ark_bootanimation_display_uninit();
  181. if (context->animation_display_phyaddr){
  182. dma_free_coherent(context->dev, context->animation_display_size,
  183. (void *)context->animation_display_virtaddr,
  184. context->animation_display_phyaddr);
  185. }
  186. iounmap((void*)context->animation_data_virtaddr);
  187. p->context.anmation_stats = 1;
  188. destroy_workqueue(context->animation_queue);
  189. return;
  190. }
  191. if (frame > 0) {
  192. if (!context->animation_dec_finish) {
  193. timeout_count++;
  194. mod_timer(&context->animation_timer, jiffies + msecs_to_jiffies(10));
  195. return;
  196. }
  197. timeout_count = 0;
  198. }
  199. if (frame == header->aniCount + header->hasBootlogo ? 1 : 0) {
  200. if (!context->animation_dec_finish) {
  201. timeout_count++;
  202. mod_timer(&context->animation_timer, jiffies + msecs_to_jiffies(10));
  203. return;
  204. }
  205. timeout_count = 0;
  206. context->animation_end = true;
  207. if (header->aniCount > 0) {
  208. mod_timer(&context->animation_timer, jiffies + msecs_to_jiffies(header->aniDelayHideTime));
  209. } else if (header->hasBootlogo) {
  210. mod_timer(&context->animation_timer, jiffies + msecs_to_jiffies(header->bootlogoDisplayTime));
  211. }
  212. return;
  213. }
  214. frame++;
  215. context->animation_dec_finish = false;
  216. context->intr_status = mfc_jpeg_decode(context->animation_file_phyaddr + 4, context->animation_file_virtaddr + 4,
  217. context->animation_display_phyaddr + MAX_ANIMFRAME_SIZE * context->animation_display_index,
  218. context->animation_display_virtaddr + MAX_ANIMFRAME_SIZE * context->animation_display_index,
  219. size);
  220. context->animation_file_phyaddr += size;
  221. context->animation_file_virtaddr += size;
  222. #if 1
  223. if (!context->animation_end) {
  224. if (!context->intr_status) {
  225. unsigned int format;
  226. if (!context->animation_initdisplay) {
  227. if(dis_format == JPEGDEC_YCbCr420_SEMIPLANAR)
  228. format = 0x11;//ARK1668E_LCDC_FORMAT_Y_UV420;
  229. if(dis_format == JPEGDEC_YCbCr422_SEMIPLANAR)
  230. format = 0x10;//ARK1668E_LCDC_FORMAT_YUV;
  231. ark_bootanimation_display_init(header->aniWidth, header->aniHeight,
  232. context->animation_display_phyaddr + MAX_ANIMFRAME_SIZE * context->animation_display_index,
  233. context->animation_display_phyaddr + MAX_ANIMFRAME_SIZE * context->animation_display_index +
  234. dis_decWidth * dis_decHeight, 0, format);
  235. context->animation_initdisplay = true;
  236. } else {
  237. if(dis_format == JPEGDEC_YCbCr420_SEMIPLANAR)
  238. format = 0x11;//ARK1668E_LCDC_FORMAT_Y_UV420;
  239. if(dis_format == JPEGDEC_YCbCr422_SEMIPLANAR)
  240. format = 0x10;//ARK1668E_LCDC_FORMAT_Y_UV422;
  241. ark_bootanimation_set_display_addr(context->animation_display_phyaddr + MAX_ANIMFRAME_SIZE * context->animation_display_index,
  242. context->animation_display_phyaddr + MAX_ANIMFRAME_SIZE * context->animation_display_index +
  243. dis_decWidth * dis_decHeight, 0, format);
  244. context->animation_display_index = !context->animation_display_index;
  245. }
  246. context->animation_dec_finish = true;
  247. } else {
  248. printk(KERN_ALERT "decode boot animation jpeg error.\n");
  249. context->animation_dec_finish = true;
  250. }
  251. }
  252. #endif
  253. if (header->hasBootlogo && frame == 1)
  254. mod_timer(&context->animation_timer, jiffies + msecs_to_jiffies(header->bootlogoDisplayTime));
  255. else
  256. mod_timer(&context->animation_timer, jiffies + msecs_to_jiffies(1000 / header->aniFps));
  257. }
  258. static void animation_timer_handler(struct timer_list *t)
  259. {
  260. struct mfc_jpeg_context *context = from_timer(context, t, animation_timer);
  261. queue_work(context->animation_queue, &context->animation_work);
  262. }
  263. /**
  264. * Misc driver related
  265. */
  266. static int vdec_misc_open(struct inode *inode, struct file *filp)
  267. {
  268. struct vdec_device *p = vdec6731_global;
  269. filp->private_data = p;
  270. dev_dbg(p->dev, "open\n");
  271. //clk_prepare_enable(p->clk);
  272. return 0;
  273. }
  274. static int vdec_misc_release(struct inode *inode, struct file *filp)
  275. {
  276. struct vdec_device *p = filp->private_data;
  277. if (p->dec_owner == filp) {
  278. p->dec_irq_done = false;
  279. init_waitqueue_head(&p->dec_wq);
  280. sema_init(&p->dec_sem, VDEC_MAX_CORES);
  281. p->dec_owner = NULL;
  282. }
  283. if (p->pp_owner == filp) {
  284. p->pp_irq_done = false;
  285. init_waitqueue_head(&p->pp_wq);
  286. sema_init(&p->pp_sem, 1);
  287. p->pp_owner = NULL;
  288. }
  289. //clk_disable_unprepare(p->clk);
  290. dev_dbg(p->dev, "release\n");
  291. return 0;
  292. }
  293. static long vdec_misc_ioctl(struct file *filp, unsigned int cmd,
  294. unsigned long arg)
  295. {
  296. int ret = 0;
  297. void __user *argp = (void __user *)arg;
  298. struct vdec_device *p = vdec6731_global;
  299. struct core_desc core;
  300. u32 reg;
  301. switch (cmd) {
  302. case HX170DEC_IOX_ASIC_ID:
  303. reg = vdec_readl(p, VDEC_IDR);
  304. if (copy_to_user(argp, &reg, sizeof(u32)))
  305. ret = -EFAULT;
  306. break;
  307. case HX170DEC_IOC_MC_OFFSETS:
  308. case HX170DEC_IOCGHWOFFSET:
  309. if (copy_to_user(argp, &p->iobaseaddr, sizeof(p->iobaseaddr)))
  310. ret = -EFAULT;
  311. break;
  312. case HX170DEC_IOCGHWIOSIZE: /* in bytes */
  313. if (copy_to_user(argp, &p->iosize, sizeof(p->iosize)))
  314. ret = -EFAULT;
  315. break;
  316. case HX170DEC_IOC_MC_CORES:
  317. if (copy_to_user(argp, &p->num_cores, sizeof(p->num_cores)))
  318. ret = -EFAULT;
  319. break;
  320. case HX170DEC_IOCS_DEC_PUSH_REG:
  321. if (copy_from_user(&core, (void *)arg, sizeof(struct core_desc))) {
  322. dev_err(p->dev, "copy_from_user (dec push reg) failed\n");
  323. ret = -EFAULT;
  324. } else {
  325. /* Skip VDEC_IDR (ID Register, ro) */
  326. core.regs++; // core.size -= 4;
  327. ret = vdec_regs_write(p, VDEC_DEC_FIRST_REG + 1, VDEC_DEC_LAST_REG, &core);
  328. }
  329. break;
  330. case HX170DEC_IOCS_PP_PUSH_REG:
  331. if (copy_from_user(&core, (void *)arg, sizeof(struct core_desc))) {
  332. dev_err(p->dev, "copy_from_user (pp push reg) failed\n");
  333. ret = -EFAULT;
  334. } else {
  335. /* Don't consider the 5 lastest registers (ro or unused) */
  336. ret = vdec_regs_write(p, VDEC_PP_FIRST_REG, VDEC_PP_LAST_REG - 5, &core);
  337. }
  338. break;
  339. case HX170DEC_IOCS_DEC_PULL_REG:
  340. if (copy_from_user(&core, (void *)arg, sizeof(struct core_desc))) {
  341. dev_err(p->dev, "copy_from_user (dec pull reg) failed\n");
  342. ret = -EFAULT;
  343. } else {
  344. ret = vdec_regs_read(p, VDEC_DEC_FIRST_REG, VDEC_DEC_LAST_REG, &core);
  345. }
  346. break;
  347. case HX170DEC_IOCS_PP_PULL_REG:
  348. if (copy_from_user(&core, (void*)arg, sizeof(struct core_desc))) {
  349. dev_err(p->dev, "copy_from_user (pp pull reg) failed\n");
  350. ret = -EFAULT;
  351. } else {
  352. ret = vdec_regs_read(p, VDEC_PP_FIRST_REG, VDEC_PP_LAST_REG, &core);
  353. }
  354. break;
  355. case HX170DEC_IOCX_DEC_WAIT:
  356. if (copy_from_user(&core, (void *)arg, sizeof(struct core_desc))) {
  357. dev_err(p->dev, "copy_from_user (dec wait) failed\n");
  358. ret = -EFAULT;
  359. } else {
  360. ret = wait_event_interruptible(p->dec_wq, p->dec_irq_done);
  361. p->dec_irq_done = false;
  362. if (unlikely(ret != 0)) {
  363. dev_err(p->dev, "wait_event_interruptible dec error %d\n", ret);
  364. } else {
  365. /* Update dec registers */
  366. ret = vdec_regs_read(p, VDEC_DEC_FIRST_REG, VDEC_DEC_LAST_REG, &core);
  367. }
  368. }
  369. break;
  370. case HX170DEC_IOCX_PP_WAIT:
  371. if (copy_from_user(&core, (void *)arg, sizeof(struct core_desc))) {
  372. dev_err(p->dev, "copy_from_user (pp wait) failed\n");
  373. ret = -EFAULT;
  374. } else {
  375. ret = wait_event_interruptible(p->pp_wq, p->pp_irq_done);
  376. p->pp_irq_done = false;
  377. if (unlikely(ret != 0)) {
  378. dev_err(p->dev, "wait_event_interruptible pp error %d\n", ret);
  379. } else {
  380. /* Update pp registers */
  381. ret = vdec_regs_read(p, VDEC_PP_FIRST_REG, VDEC_PP_LAST_REG, &core);
  382. }
  383. }
  384. break;
  385. case HX170DEC_IOCH_DEC_RESERVE:
  386. if (likely(down_interruptible(&p->dec_sem) == 0)) {
  387. p->dec_owner = filp;
  388. ret = 0; /* core id */
  389. dev_dbg(p->dev, "down dec_sem (core id %d)\n", ret);
  390. } else {
  391. dev_err(p->dev, "down_interruptible dec error\n");
  392. ret = -ERESTARTSYS;
  393. }
  394. break;
  395. case HX170DEC_IOCT_DEC_RELEASE:
  396. dev_dbg(p->dev, "up dec_sem\n");
  397. p->dec_owner = NULL;
  398. up(&p->dec_sem);
  399. break;
  400. case HX170DEC_IOCQ_PP_RESERVE:
  401. if (likely(down_interruptible(&p->pp_sem) == 0)) {
  402. p->pp_owner = filp;
  403. ret = 0; /* core id */
  404. dev_dbg(p->dev, "down pp_sem (core id %d)\n", ret);
  405. } else {
  406. dev_err(p->dev, "down_interruptible pp error\n");
  407. ret = -ERESTARTSYS;
  408. }
  409. break;
  410. case HX170DEC_IOCT_PP_RELEASE:
  411. dev_dbg(p->dev, "up pp_sem\n");
  412. p->pp_owner = NULL;
  413. up(&p->pp_sem);
  414. break;
  415. default:
  416. dev_warn(p->dev, "unknown ioctl %x\n", cmd);
  417. ret = -EINVAL;
  418. }
  419. return ret;
  420. }
  421. const struct file_operations vdec_misc_fops = {
  422. .owner = THIS_MODULE,
  423. .llseek = no_llseek,
  424. .open = vdec_misc_open,
  425. .release = vdec_misc_release,
  426. .unlocked_ioctl = vdec_misc_ioctl,
  427. };
  428. static struct miscdevice vdec_misc_device = {
  429. MISC_DYNAMIC_MINOR,
  430. "vdec",
  431. &vdec_misc_fops
  432. };
  433. /*
  434. * Platform driver related
  435. */
  436. /* Should we use spin_lock_irqsave here? */
  437. static irqreturn_t vdec_isr(int irq, void *dev_id)
  438. {
  439. struct vdec_device *p = dev_id;
  440. u32 irq_status_dec, irq_status_pp;
  441. int handled = 0;
  442. // struct mfc_jpeg_context *context = vde_jpeg_context;
  443. /* interrupt status register read */
  444. irq_status_dec = vdec_readl(p, VDEC_DIR);
  445. //printk(KERN_ALERT "irq_status=0x%x.\n", irq_status_dec);
  446. if (irq_status_dec & VDEC_DIR_ISET) {
  447. /* Clear IRQ */
  448. vdec_writel(p, VDEC_DIR, irq_status_dec & ~VDEC_DIR_ISET);
  449. p->dec_irq_done = true;
  450. wake_up_interruptible(&p->dec_wq);
  451. handled++;
  452. }
  453. irq_status_pp = vdec_readl(p, VDEC_PPIR);
  454. if (irq_status_pp & VDEC_PPIR_ISET) {
  455. /* Clear IRQ */
  456. vdec_writel(p, VDEC_PPIR, irq_status_pp & ~VDEC_PPIR_ISET);
  457. p->pp_irq_done = true;
  458. wake_up_interruptible(&p->pp_wq);
  459. handled++;
  460. }
  461. if (handled == 0) {
  462. dev_warn(p->dev, "Spurious IRQ (DIR=%08x PPIR=%08x)\n", \
  463. irq_status_dec, irq_status_pp);
  464. return IRQ_NONE;
  465. }
  466. return IRQ_HANDLED;
  467. }
  468. static int vdec_probe(struct platform_device *pdev)
  469. {
  470. struct vdec_device *p;
  471. struct resource *res, *animres;
  472. int ret;
  473. u32 hwid;
  474. /* Allocate private data */
  475. p = devm_kzalloc(&pdev->dev, sizeof(struct vdec_device), GFP_KERNEL);
  476. if (!p) {
  477. dev_dbg(&pdev->dev, "out of memory\n");
  478. return -ENOMEM;
  479. }
  480. p->dev = &pdev->dev;
  481. platform_set_drvdata(pdev, p);
  482. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  483. p->mmio_base = devm_ioremap_resource(&pdev->dev, res);
  484. if (IS_ERR(p->mmio_base))
  485. return PTR_ERR(p->mmio_base);
  486. p->clk = devm_clk_get(&pdev->dev, "vdec_clk");
  487. if (IS_ERR(p->clk)) {
  488. dev_err(&pdev->dev, "no vdec_clk clock defined\n");
  489. return -ENXIO;
  490. }
  491. p->irq = platform_get_irq(pdev, 0);
  492. if (!p->irq) {
  493. dev_err(&pdev->dev, "could not get irq\n");
  494. return -ENXIO;
  495. }
  496. ret = devm_request_irq(&pdev->dev, p->irq, vdec_isr,
  497. 0, pdev->name, p);
  498. if (ret) {
  499. dev_err(&pdev->dev, "unable to request VDEC irq\n");
  500. return ret;
  501. }
  502. /* Register the miscdevice */
  503. ret = misc_register(&vdec_misc_device);
  504. if (ret) {
  505. dev_err(&pdev->dev, "unable to register miscdevice\n");
  506. return ret;
  507. }
  508. p->num_cores = VDEC_MAX_CORES;
  509. p->iosize = resource_size(res);
  510. p->iobaseaddr = res->start;
  511. vdec6731_global = p;
  512. p->dec_irq_done = false;
  513. p->pp_irq_done = false;
  514. p->dec_owner = NULL;
  515. p->pp_owner = NULL;
  516. init_waitqueue_head(&p->dec_wq);
  517. init_waitqueue_head(&p->pp_wq);
  518. sema_init(&p->dec_sem, VDEC_MAX_CORES);
  519. sema_init(&p->pp_sem, 1);
  520. ret = clk_prepare_enable(p->clk);
  521. if (ret) {
  522. dev_err(&pdev->dev, "unable to prepare and enable clock\n");
  523. misc_deregister(&vdec_misc_device);
  524. return ret;
  525. }
  526. dev_info(&pdev->dev, "VDEC controller at 0x%p, irq = %d, misc_minor = %d\n",
  527. p->mmio_base, p->irq, vdec_misc_device.minor);
  528. //MFC jpeg decode
  529. animres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  530. if (IS_ERR(animres)) {
  531. return PTR_ERR(animres);
  532. }
  533. p->context.dev = p->dev;
  534. p->context.anmation_stats = 0;
  535. p->context.animation_data_phyaddr = animres->start;
  536. p->context.animation_data_size = resource_size(animres);
  537. p->context.animation_data_virtaddr =
  538. (unsigned int)ioremap(p->context.animation_data_phyaddr, resource_size(animres));
  539. if (p->context.animation_data_virtaddr) {
  540. BANIHEADER *header = (BANIHEADER *) p->context.animation_data_virtaddr;
  541. if (header->magic == MKTAG('B', 'A', 'N', 'I')) {
  542. vde_jpeg_context = &p->context;
  543. p->context.animation_file_phyaddr =
  544. p->context.animation_data_phyaddr + sizeof(BANIHEADER);
  545. p->context.animation_file_virtaddr =
  546. p->context.animation_data_virtaddr + sizeof(BANIHEADER);
  547. p->context.animation_display_size = MAX_ANIMFRAME_SIZE * 2;
  548. p->context.animation_display_virtaddr =
  549. (unsigned int)dma_alloc_coherent(&pdev->dev, p->context.animation_display_size,
  550. &p->context.animation_display_phyaddr, GFP_KERNEL);
  551. if (!p->context.animation_display_virtaddr) {
  552. dev_err(&pdev->dev, "alloc animation display buffer failed.\n");
  553. p->context.animation_end = true;
  554. } else {
  555. p->context.animation_end = false;
  556. p->context.animation_dec_finish = false;
  557. p->context.animation_initdisplay = false;
  558. p->context.animation_queue = create_singlethread_workqueue("animation_queue");
  559. if(!p->context.animation_queue) {
  560. printk(KERN_ERR "%s %d: , create_singlethread_workqueue fail.\n",__FUNCTION__, __LINE__);
  561. return -1;
  562. }
  563. INIT_WORK(&p->context.animation_work, animation_dec_work);
  564. timer_setup(&p->context.animation_timer, animation_timer_handler, 0);
  565. p->context.animation_timer.expires = jiffies + 10;
  566. add_timer(&p->context.animation_timer);
  567. }
  568. } else {
  569. vde_jpeg_context = &p->context;
  570. p->context.animation_end = true;
  571. }
  572. } else
  573. p->context.animation_end = true;
  574. /* Reset Asic (just in case..) */
  575. vdec_writel(p, VDEC_DIR, VDEC_DIR_ID | VDEC_DIR_ABORT);
  576. vdec_writel(p, VDEC_PPIR, VDEC_PPIR_ID);
  577. hwid = vdec_readl(p, VDEC_IDR);
  578. dev_warn(&pdev->dev, "Product ID: %#x (revision %d.%d.%d)\n", \
  579. (hwid & VDEC_IDR_PROD_ID) >> 16,
  580. (hwid & VDEC_IDR_MAJOR_VER) >> 12,
  581. (hwid & VDEC_IDR_MINOR_VER) >> 4,
  582. (hwid & VDEC_IDR_BUILD_VER));
  583. return 0;
  584. }
  585. static int vdec_remove(struct platform_device *pdev)
  586. {
  587. platform_set_drvdata(pdev, NULL);
  588. misc_deregister(&vdec_misc_device);
  589. return 0;
  590. }
  591. static const struct of_device_id vdec_of_match[] = {
  592. { .compatible = "on2,ark-vdec", .data = NULL },
  593. {},
  594. };
  595. MODULE_DEVICE_TABLE(of, vdec_of_match);
  596. static struct platform_driver vdec_of_driver = {
  597. .driver = {
  598. .name = "ark-vdec",
  599. .owner = THIS_MODULE,
  600. .of_match_table = vdec_of_match,
  601. },
  602. .probe = vdec_probe,
  603. .remove = vdec_remove,
  604. };
  605. //module_platform_driver(vdec_of_driver);
  606. static int __init ark_vdec_init(void)
  607. {
  608. int ret;
  609. ret = platform_driver_register(&vdec_of_driver);
  610. if (ret != 0) {
  611. printk(KERN_ERR "%s %d: failed to register vdec_of_driver\n",
  612. __FUNCTION__, __LINE__);
  613. }
  614. return ret;
  615. }
  616. fs_initcall(ark_vdec_init);
  617. MODULE_AUTHOR("Hantro Products Oy");
  618. MODULE_DESCRIPTION("G1 decoder/pp driver");
  619. MODULE_LICENSE("GPL");
  620. MODULE_VERSION("0.4");
  621. MODULE_ALIAS("platform:vdec");