linux-arkmicro/linux/tools/perf/pmu-events/arch/s390/cf_z13/extended.json

[
	{
		"Unit": "CPU-M-CF",
		"EventCode": "128",
		"EventName": "L1D_RO_EXCL_WRITES",
		"BriefDescription": "L1D Read-only Exclusive Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "129",
		"EventName": "DTLB1_WRITES",
		"BriefDescription": "DTLB1 Writes",
		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "130",
		"EventName": "DTLB1_MISSES",
		"BriefDescription": "DTLB1 Misses",
		"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "131",
		"EventName": "DTLB1_HPAGE_WRITES",
		"BriefDescription": "DTLB1 One-Megabyte Page Writes",
		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "132",
		"EventName": "DTLB1_GPAGE_WRITES",
		"BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
		"PublicDescription": "Counter:132	Name:DTLB1_GPAGE_WRITES A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a two-gigabyte page."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "133",
		"EventName": "L1D_L2D_SOURCED_WRITES",
		"BriefDescription": "L1D L2D Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "134",
		"EventName": "ITLB1_WRITES",
		"BriefDescription": "ITLB1 Writes",
		"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "135",
		"EventName": "ITLB1_MISSES",
		"BriefDescription": "ITLB1 Misses",
		"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "136",
		"EventName": "L1I_L2I_SOURCED_WRITES",
		"BriefDescription": "L1I L2I Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "137",
		"EventName": "TLB2_PTE_WRITES",
		"BriefDescription": "TLB2 PTE Writes",
		"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "138",
		"EventName": "TLB2_CRSTE_HPAGE_WRITES",
		"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
		"PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "139",
		"EventName": "TLB2_CRSTE_WRITES",
		"BriefDescription": "TLB2 CRSTE Writes",
		"PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "140",
		"EventName": "TX_C_TEND",
		"BriefDescription": "Completed TEND instructions in constrained TX mode",
		"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "141",
		"EventName": "TX_NC_TEND",
		"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
		"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "143",
		"EventName": "L1C_TLB1_MISSES",
		"BriefDescription": "L1C TLB1 Misses",
		"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is in progress."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "144",
		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
		"BriefDescription": "L1D On-Chip L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "145",
		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "146",
		"EventName": "L1D_ONNODE_L4_SOURCED_WRITES",
		"BriefDescription": "L1D On-Node L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "147",
		"EventName": "L1D_ONNODE_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "148",
		"EventName": "L1D_ONNODE_L3_SOURCED_WRITES",
		"BriefDescription": "L1D On-Node L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "149",
		"EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
		"BriefDescription": "L1D On-Drawer L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "150",
		"EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "151",
		"EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES",
		"BriefDescription": "L1D On-Drawer L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "152",
		"EventName": "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "153",
		"EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "154",
		"EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "155",
		"EventName": "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "156",
		"EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "157",
		"EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "158",
		"EventName": "L1D_ONNODE_MEM_SOURCED_WRITES",
		"BriefDescription": "L1D On-Node Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "159",
		"EventName": "L1D_ONDRAWER_MEM_SOURCED_WRITES",
		"BriefDescription": "L1D On-Drawer Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "160",
		"EventName": "L1D_OFFDRAWER_MEM_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "161",
		"EventName": "L1D_ONCHIP_MEM_SOURCED_WRITES",
		"BriefDescription": "L1D On-Chip Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "162",
		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
		"BriefDescription": "L1I On-Chip L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "163",
		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "164",
		"EventName": "L1I_ONNODE_L4_SOURCED_WRITES",
		"BriefDescription": "L1I On-Chip L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "165",
		"EventName": "L1I_ONNODE_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1I On-Node L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "166",
		"EventName": "L1I_ONNODE_L3_SOURCED_WRITES",
		"BriefDescription": "L1I On-Node L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "167",
		"EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
		"BriefDescription": "L1I On-Drawer L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "168",
		"EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1I On-Drawer L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "169",
		"EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES",
		"BriefDescription": "L1I On-Drawer L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "170",
		"EventName": "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
		"BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "171",
		"EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "172",
		"EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
		"BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "173",
		"EventName": "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
		"BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "174",
		"EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "175",
		"EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
		"BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "176",
		"EventName": "L1I_ONNODE_MEM_SOURCED_WRITES",
		"BriefDescription": "L1I On-Node Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "177",
		"EventName": "L1I_ONDRAWER_MEM_SOURCED_WRITES",
		"BriefDescription": "L1I On-Drawer Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "178",
		"EventName": "L1I_OFFDRAWER_MEM_SOURCED_WRITES",
		"BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "179",
		"EventName": "L1I_ONCHIP_MEM_SOURCED_WRITES",
		"BriefDescription": "L1I On-Chip Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "218",
		"EventName": "TX_NC_TABORT",
		"BriefDescription": "Aborted transactions in non-constrained TX mode",
		"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "219",
		"EventName": "TX_C_TABORT_NO_SPECIAL",
		"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "220",
		"EventName": "TX_C_TABORT_SPECIAL",
		"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "448",
		"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
		"BriefDescription": "Cycle count with one thread active",
		"PublicDescription": "Cycle count with one thread active"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "449",
		"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
		"BriefDescription": "Cycle count with two threads active",
		"PublicDescription": "Cycle count with two threads active"
	},
]