clk.c 1.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/addrspace.h>
  8. #include <asm/types.h>
  9. #include <mach/ar71xx_regs.h>
  10. #include <mach/ath79.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. static u32 ar933x_get_xtal(void)
  13. {
  14. u32 val;
  15. val = ath79_get_bootstrap();
  16. if (val & AR933X_BOOTSTRAP_REF_CLK_40)
  17. return 40000000;
  18. else
  19. return 25000000;
  20. }
  21. int get_serial_clock(void)
  22. {
  23. return ar933x_get_xtal();
  24. }
  25. int get_clocks(void)
  26. {
  27. void __iomem *regs;
  28. u32 val, xtal, pll, div;
  29. regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
  30. MAP_NOCACHE);
  31. xtal = ar933x_get_xtal();
  32. val = readl(regs + AR933X_PLL_CPU_CONFIG_REG);
  33. /* VCOOUT = XTAL * DIV_INT */
  34. div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
  35. & AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
  36. pll = xtal / div;
  37. /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
  38. div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
  39. & AR933X_PLL_CPU_CONFIG_NINT_MASK;
  40. pll *= div;
  41. div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
  42. & AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
  43. if (!div)
  44. div = 1;
  45. pll >>= div;
  46. val = readl(regs + AR933X_PLL_CLK_CTRL_REG);
  47. /* CPU_CLK = PLLOUT / CPU_POST_DIV */
  48. div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
  49. & AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
  50. gd->cpu_clk = pll / div;
  51. /* DDR_CLK = PLLOUT / DDR_POST_DIV */
  52. div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
  53. & AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
  54. gd->mem_clk = pll / div;
  55. /* AHB_CLK = PLLOUT / AHB_POST_DIV */
  56. div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
  57. & AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
  58. gd->bus_clk = pll / div;
  59. return 0;
  60. }
  61. ulong get_bus_freq(ulong dummy)
  62. {
  63. if (!gd->bus_clk)
  64. get_clocks();
  65. return gd->bus_clk;
  66. }
  67. ulong get_ddr_freq(ulong dummy)
  68. {
  69. if (!gd->mem_clk)
  70. get_clocks();
  71. return gd->mem_clk;
  72. }