me_status.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * From Coreboot src/southbridge/intel/bd82x6x/me_status.c
  4. *
  5. * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
  6. */
  7. #include <common.h>
  8. #include <asm/arch/me.h>
  9. /* HFS1[3:0] Current Working State Values */
  10. static const char *const me_cws_values[] = {
  11. [ME_HFS_CWS_RESET] = "Reset",
  12. [ME_HFS_CWS_INIT] = "Initializing",
  13. [ME_HFS_CWS_REC] = "Recovery",
  14. [ME_HFS_CWS_NORMAL] = "Normal",
  15. [ME_HFS_CWS_WAIT] = "Platform Disable Wait",
  16. [ME_HFS_CWS_TRANS] = "OP State Transition",
  17. [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In"
  18. };
  19. /* HFS1[8:6] Current Operation State Values */
  20. static const char *const me_opstate_values[] = {
  21. [ME_HFS_STATE_PREBOOT] = "Preboot",
  22. [ME_HFS_STATE_M0_UMA] = "M0 with UMA",
  23. [ME_HFS_STATE_M3] = "M3 without UMA",
  24. [ME_HFS_STATE_M0] = "M0 without UMA",
  25. [ME_HFS_STATE_BRINGUP] = "Bring up",
  26. [ME_HFS_STATE_ERROR] = "M0 without UMA but with error"
  27. };
  28. /* HFS[19:16] Current Operation Mode Values */
  29. static const char *const me_opmode_values[] = {
  30. [ME_HFS_MODE_NORMAL] = "Normal",
  31. [ME_HFS_MODE_DEBUG] = "Debug",
  32. [ME_HFS_MODE_DIS] = "Soft Temporary Disable",
  33. [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
  34. [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message"
  35. };
  36. /* HFS[15:12] Error Code Values */
  37. static const char *const me_error_values[] = {
  38. [ME_HFS_ERROR_NONE] = "No Error",
  39. [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure",
  40. [ME_HFS_ERROR_IMAGE] = "Image Failure",
  41. [ME_HFS_ERROR_DEBUG] = "Debug Failure"
  42. };
  43. /* GMES[31:28] ME Progress Code */
  44. static const char *const me_progress_values[] = {
  45. [ME_GMES_PHASE_ROM] = "ROM Phase",
  46. [ME_GMES_PHASE_BUP] = "BUP Phase",
  47. [ME_GMES_PHASE_UKERNEL] = "uKernel Phase",
  48. [ME_GMES_PHASE_POLICY] = "Policy Module",
  49. [ME_GMES_PHASE_MODULE] = "Module Loading",
  50. [ME_GMES_PHASE_UNKNOWN] = "Unknown",
  51. [ME_GMES_PHASE_HOST] = "Host Communication"
  52. };
  53. /* GMES[27:24] Power Management Event */
  54. static const char *const me_pmevent_values[] = {
  55. [0x00] = "Clean Moff->Mx wake",
  56. [0x01] = "Moff->Mx wake after an error",
  57. [0x02] = "Clean global reset",
  58. [0x03] = "Global reset after an error",
  59. [0x04] = "Clean Intel ME reset",
  60. [0x05] = "Intel ME reset due to exception",
  61. [0x06] = "Pseudo-global reset",
  62. [0x07] = "S0/M0->Sx/M3",
  63. [0x08] = "Sx/M3->S0/M0",
  64. [0x09] = "Non-power cycle reset",
  65. [0x0a] = "Power cycle reset through M3",
  66. [0x0b] = "Power cycle reset through Moff",
  67. [0x0c] = "Sx/Mx->Sx/Moff"
  68. };
  69. /* Progress Code 0 states */
  70. static const char *const me_progress_rom_values[] = {
  71. [0x00] = "BEGIN",
  72. [0x06] = "DISABLE"
  73. };
  74. /* Progress Code 1 states */
  75. static const char *const me_progress_bup_values[] = {
  76. [0x00] = "Initialization starts",
  77. [0x01] = "Disable the host wake event",
  78. [0x04] = "Flow determination start process",
  79. [0x08] = "Error reading/matching the VSCC table in the descriptor",
  80. [0x0a] = "Check to see if straps say ME DISABLED",
  81. [0x0b] = "Timeout waiting for PWROK",
  82. [0x0d] = "Possibly handle BUP manufacturing override strap",
  83. [0x11] = "Bringup in M3",
  84. [0x12] = "Bringup in M0",
  85. [0x13] = "Flow detection error",
  86. [0x15] = "M3 clock switching error",
  87. [0x18] = "M3 kernel load",
  88. [0x1c] = "T34 missing - cannot program ICC",
  89. [0x1f] = "Waiting for DID BIOS message",
  90. [0x20] = "Waiting for DID BIOS message failure",
  91. [0x21] = "DID reported an error",
  92. [0x22] = "Enabling UMA",
  93. [0x23] = "Enabling UMA error",
  94. [0x24] = "Sending DID Ack to BIOS",
  95. [0x25] = "Sending DID Ack to BIOS error",
  96. [0x26] = "Switching clocks in M0",
  97. [0x27] = "Switching clocks in M0 error",
  98. [0x28] = "ME in temp disable",
  99. [0x32] = "M0 kernel load",
  100. };
  101. /* Progress Code 3 states */
  102. static const char *const me_progress_policy_values[] = {
  103. [0x00] = "Entery into Policy Module",
  104. [0x03] = "Received S3 entry",
  105. [0x04] = "Received S4 entry",
  106. [0x05] = "Received S5 entry",
  107. [0x06] = "Received UPD entry",
  108. [0x07] = "Received PCR entry",
  109. [0x08] = "Received NPCR entry",
  110. [0x09] = "Received host wake",
  111. [0x0a] = "Received AC<>DC switch",
  112. [0x0b] = "Received DRAM Init Done",
  113. [0x0c] = "VSCC Data not found for flash device",
  114. [0x0d] = "VSCC Table is not valid",
  115. [0x0e] = "Flash Partition Boundary is outside address space",
  116. [0x0f] = "ME cannot access the chipset descriptor region",
  117. [0x10] = "Required VSCC values for flash parts do not match",
  118. };
  119. /**
  120. * _intel_me_status() - Check Intel Management Engine status
  121. *
  122. * struct hfs: Firmware status
  123. * struct gmes: Management engine status
  124. */
  125. static void _intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
  126. {
  127. /* Check Current States */
  128. debug("ME: FW Partition Table : %s\n",
  129. hfs->fpt_bad ? "BAD" : "OK");
  130. debug("ME: Bringup Loader Failure : %s\n",
  131. hfs->ft_bup_ld_flr ? "YES" : "NO");
  132. debug("ME: Firmware Init Complete : %s\n",
  133. hfs->fw_init_complete ? "YES" : "NO");
  134. debug("ME: Manufacturing Mode : %s\n",
  135. hfs->mfg_mode ? "YES" : "NO");
  136. debug("ME: Boot Options Present : %s\n",
  137. hfs->boot_options_present ? "YES" : "NO");
  138. debug("ME: Update In Progress : %s\n",
  139. hfs->update_in_progress ? "YES" : "NO");
  140. debug("ME: Current Working State : %s\n",
  141. me_cws_values[hfs->working_state]);
  142. debug("ME: Current Operation State : %s\n",
  143. me_opstate_values[hfs->operation_state]);
  144. debug("ME: Current Operation Mode : %s\n",
  145. me_opmode_values[hfs->operation_mode]);
  146. debug("ME: Error Code : %s\n",
  147. me_error_values[hfs->error_code]);
  148. debug("ME: Progress Phase : %s\n",
  149. me_progress_values[gmes->progress_code]);
  150. debug("ME: Power Management Event : %s\n",
  151. me_pmevent_values[gmes->current_pmevent]);
  152. debug("ME: Progress Phase State : ");
  153. switch (gmes->progress_code) {
  154. case ME_GMES_PHASE_ROM: /* ROM Phase */
  155. debug("%s", me_progress_rom_values[gmes->current_state]);
  156. break;
  157. case ME_GMES_PHASE_BUP: /* Bringup Phase */
  158. if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) &&
  159. me_progress_bup_values[gmes->current_state])
  160. debug("%s",
  161. me_progress_bup_values[gmes->current_state]);
  162. else
  163. debug("0x%02x", gmes->current_state);
  164. break;
  165. case ME_GMES_PHASE_POLICY: /* Policy Module Phase */
  166. if (gmes->current_state <
  167. ARRAY_SIZE(me_progress_policy_values) &&
  168. me_progress_policy_values[gmes->current_state])
  169. debug("%s",
  170. me_progress_policy_values[gmes->current_state]);
  171. else
  172. debug("0x%02x", gmes->current_state);
  173. break;
  174. case ME_GMES_PHASE_HOST: /* Host Communication Phase */
  175. if (!gmes->current_state)
  176. debug("Host communication established");
  177. else
  178. debug("0x%02x", gmes->current_state);
  179. break;
  180. default:
  181. debug("Unknown 0x%02x", gmes->current_state);
  182. }
  183. debug("\n");
  184. }
  185. void intel_me_status(struct udevice *me_dev)
  186. {
  187. struct me_hfs hfs;
  188. struct me_gmes gmes;
  189. pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
  190. pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
  191. _intel_me_status(&hfs, &gmes);
  192. }