early_me.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
  4. *
  5. * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <asm/pci.h>
  11. #include <asm/cpu.h>
  12. #include <asm/processor.h>
  13. #include <asm/arch/me.h>
  14. #include <asm/arch/pch.h>
  15. #include <asm/io.h>
  16. static const char *const me_ack_values[] = {
  17. [ME_HFS_ACK_NO_DID] = "No DID Ack received",
  18. [ME_HFS_ACK_RESET] = "Non-power cycle reset",
  19. [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
  20. [ME_HFS_ACK_S3] = "Go to S3",
  21. [ME_HFS_ACK_S4] = "Go to S4",
  22. [ME_HFS_ACK_S5] = "Go to S5",
  23. [ME_HFS_ACK_GBL_RESET] = "Global Reset",
  24. [ME_HFS_ACK_CONTINUE] = "Continue to boot"
  25. };
  26. int intel_early_me_init(struct udevice *me_dev)
  27. {
  28. int count;
  29. struct me_uma uma;
  30. struct me_hfs hfs;
  31. debug("Intel ME early init\n");
  32. /* Wait for ME UMA SIZE VALID bit to be set */
  33. for (count = ME_RETRY; count > 0; --count) {
  34. pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
  35. if (uma.valid)
  36. break;
  37. udelay(ME_DELAY);
  38. }
  39. if (!count) {
  40. printf("ERROR: ME is not ready!\n");
  41. return -EBUSY;
  42. }
  43. /* Check for valid firmware */
  44. pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
  45. if (hfs.fpt_bad) {
  46. printf("WARNING: ME has bad firmware\n");
  47. return -EBADF;
  48. }
  49. debug("Intel ME firmware is ready\n");
  50. return 0;
  51. }
  52. int intel_early_me_uma_size(struct udevice *me_dev)
  53. {
  54. struct me_uma uma;
  55. pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
  56. if (uma.valid) {
  57. debug("ME: Requested %uMB UMA\n", uma.size);
  58. return uma.size;
  59. }
  60. debug("ME: Invalid UMA size\n");
  61. return -EINVAL;
  62. }
  63. static inline void set_global_reset(struct udevice *dev, int enable)
  64. {
  65. u32 etr3;
  66. dm_pci_read_config32(dev, ETR3, &etr3);
  67. /* Clear CF9 Without Resume Well Reset Enable */
  68. etr3 &= ~ETR3_CWORWRE;
  69. /* CF9GR indicates a Global Reset */
  70. if (enable)
  71. etr3 |= ETR3_CF9GR;
  72. else
  73. etr3 &= ~ETR3_CF9GR;
  74. dm_pci_write_config32(dev, ETR3, etr3);
  75. }
  76. int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
  77. uint status)
  78. {
  79. int count;
  80. u32 mebase_l, mebase_h;
  81. struct me_hfs hfs;
  82. struct me_did did = {
  83. .init_done = ME_INIT_DONE,
  84. .status = status
  85. };
  86. /* MEBASE from MESEG_BASE[35:20] */
  87. dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l);
  88. dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h);
  89. mebase_h &= 0xf;
  90. did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
  91. /* Send message to ME */
  92. debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
  93. status, did.uma_base);
  94. pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS);
  95. /* Must wait for ME acknowledgement */
  96. for (count = ME_RETRY; count > 0; --count) {
  97. pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
  98. if (hfs.bios_msg_ack)
  99. break;
  100. udelay(ME_DELAY);
  101. }
  102. if (!count) {
  103. printf("ERROR: ME failed to respond\n");
  104. return -ETIMEDOUT;
  105. }
  106. /* Return the requested BIOS action */
  107. debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
  108. /* Check status after acknowledgement */
  109. intel_me_status(me_dev);
  110. switch (hfs.ack_data) {
  111. case ME_HFS_ACK_CONTINUE:
  112. /* Continue to boot */
  113. return 0;
  114. case ME_HFS_ACK_RESET:
  115. /* Non-power cycle reset */
  116. set_global_reset(dev, 0);
  117. reset_cpu(0);
  118. break;
  119. case ME_HFS_ACK_PWR_CYCLE:
  120. /* Power cycle reset */
  121. set_global_reset(dev, 0);
  122. x86_full_reset();
  123. break;
  124. case ME_HFS_ACK_GBL_RESET:
  125. /* Global reset */
  126. set_global_reset(dev, 1);
  127. x86_full_reset();
  128. break;
  129. case ME_HFS_ACK_S3:
  130. case ME_HFS_ACK_S4:
  131. case ME_HFS_ACK_S5:
  132. break;
  133. }
  134. return -EINVAL;
  135. }
  136. static const struct udevice_id ivybridge_syscon_ids[] = {
  137. { .compatible = "intel,me", .data = X86_SYSCON_ME },
  138. { }
  139. };
  140. U_BOOT_DRIVER(syscon_intel_me) = {
  141. .name = "intel_me_syscon",
  142. .id = UCLASS_SYSCON,
  143. .of_match = ivybridge_syscon_ids,
  144. };