smc.h 15 KB

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  1. /* SPDX-License-Identifier: Intel */
  2. /*
  3. * Copyright (C) 2013, Intel Corporation
  4. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  5. *
  6. * Ported from Intel released Quark UEFI BIOS
  7. * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
  8. */
  9. #ifndef _SMC_H_
  10. #define _SMC_H_
  11. /* System Memory Controller Register Defines */
  12. /* Memory Controller Message Bus Registers Offsets */
  13. #define DRP 0x00
  14. #define DTR0 0x01
  15. #define DTR1 0x02
  16. #define DTR2 0x03
  17. #define DTR3 0x04
  18. #define DTR4 0x05
  19. #define DPMC0 0x06
  20. #define DPMC1 0x07
  21. #define DRFC 0x08
  22. #define DSCH 0x09
  23. #define DCAL 0x0a
  24. #define DRMC 0x0b
  25. #define PMSTS 0x0c
  26. #define DCO 0x0f
  27. #define DSTAT 0x20
  28. #define SSKPD0 0x4a
  29. #define SSKPD1 0x4b
  30. #define DECCCTRL 0x60
  31. #define DECCSTAT 0x61
  32. #define DECCSBECNT 0x62
  33. #define DECCSBECA 0x68
  34. #define DECCSBECS 0x69
  35. #define DECCDBECA 0x6a
  36. #define DECCDBECS 0x6b
  37. #define DFUSESTAT 0x70
  38. #define SCRMSEED 0x80
  39. #define SCRMLO 0x81
  40. #define SCRMHI 0x82
  41. /* DRP register defines */
  42. #define DRP_RKEN0 (1 << 0)
  43. #define DRP_RKEN1 (1 << 1)
  44. #define DRP_PRI64BSPLITEN (1 << 13)
  45. #define DRP_ADDRMAP_MAP0 (1 << 14)
  46. #define DRP_ADDRMAP_MAP1 (1 << 15)
  47. #define DRP_ADDRMAP_MASK 0x0000c000
  48. /* DTR0 register defines */
  49. #define DTR0_DFREQ_MASK 0x00000003
  50. #define DTR0_TRP_MASK 0x000000f0
  51. #define DTR0_TRCD_MASK 0x00000f00
  52. #define DTR0_TCL_MASK 0x00007000
  53. /* DTR1 register defines */
  54. #define DTR1_TWCL_MASK 0x00000007
  55. #define DTR1_TCMD_MASK 0x00000030
  56. #define DTR1_TWTP_MASK 0x00000f00
  57. #define DTR1_TCCD_12CLK (1 << 12)
  58. #define DTR1_TCCD_18CLK (1 << 13)
  59. #define DTR1_TCCD_MASK 0x00003000
  60. #define DTR1_TFAW_MASK 0x000f0000
  61. #define DTR1_TRAS_MASK 0x00f00000
  62. #define DTR1_TRRD_MASK 0x03000000
  63. #define DTR1_TRTP_MASK 0x70000000
  64. /* DTR2 register defines */
  65. #define DTR2_TRRDR_MASK 0x00000007
  66. #define DTR2_TWWDR_MASK 0x00000700
  67. #define DTR2_TRWDR_MASK 0x000f0000
  68. /* DTR3 register defines */
  69. #define DTR3_TWRDR_MASK 0x00000007
  70. #define DTR3_TXXXX_MASK 0x00000070
  71. #define DTR3_TRWSR_MASK 0x00000f00
  72. #define DTR3_TWRSR_MASK 0x0001e000
  73. #define DTR3_TXP_MASK 0x00c00000
  74. /* DTR4 register defines */
  75. #define DTR4_WRODTSTRT_MASK 0x00000003
  76. #define DTR4_WRODTSTOP_MASK 0x00000070
  77. #define DTR4_XXXX1_MASK 0x00000700
  78. #define DTR4_XXXX2_MASK 0x00007000
  79. #define DTR4_ODTDIS (1 << 15)
  80. #define DTR4_TRGSTRDIS (1 << 16)
  81. /* DPMC0 register defines */
  82. #define DPMC0_PCLSTO_MASK 0x00070000
  83. #define DPMC0_PREAPWDEN (1 << 21)
  84. #define DPMC0_DYNSREN (1 << 23)
  85. #define DPMC0_CLKGTDIS (1 << 24)
  86. #define DPMC0_DISPWRDN (1 << 25)
  87. #define DPMC0_ENPHYCLKGATE (1 << 29)
  88. /* DRFC register defines */
  89. #define DRFC_TREFI_MASK 0x00007000
  90. #define DRFC_REFDBTCLR (1 << 21)
  91. /* DSCH register defines */
  92. #define DSCH_OOODIS (1 << 8)
  93. #define DSCH_OOOST3DIS (1 << 9)
  94. #define DSCH_NEWBYPDIS (1 << 12)
  95. /* DCAL register defines */
  96. #define DCAL_ZQCINT_MASK 0x00000700
  97. #define DCAL_SRXZQCL_MASK 0x00003000
  98. /* DRMC register defines */
  99. #define DRMC_CKEMODE (1 << 4)
  100. #define DRMC_ODTMODE (1 << 12)
  101. #define DRMC_COLDWAKE (1 << 16)
  102. /* PMSTS register defines */
  103. #define PMSTS_DISR (1 << 0)
  104. /* DCO register defines */
  105. #define DCO_DRPLOCK (1 << 0)
  106. #define DCO_CPGCLOCK (1 << 8)
  107. #define DCO_PMICTL (1 << 28)
  108. #define DCO_PMIDIS (1 << 29)
  109. #define DCO_IC (1 << 31)
  110. /* DECCCTRL register defines */
  111. #define DECCCTRL_SBEEN (1 << 0)
  112. #define DECCCTRL_DBEEN (1 << 1)
  113. #define DECCCTRL_ENCBGEN (1 << 17)
  114. /* DRAM init command */
  115. #define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6))
  116. #define DCMD_REF(rnk) (1 | ((rnk) << 22))
  117. #define DCMD_PRE(rnk) (2 | ((rnk) << 22))
  118. #define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (0x400 << 6))
  119. #define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6))
  120. #define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6))
  121. #define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6))
  122. #define DCMD_ZQCS(rnk) (6 | ((rnk) << 22))
  123. #define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (0x400 << 6))
  124. #define DCMD_NOP(rnk) (7 | ((rnk) << 22))
  125. #define DDR3_EMRS1_DIC_40 0
  126. #define DDR3_EMRS1_DIC_34 1
  127. #define DDR3_EMRS1_RTTNOM_0 0
  128. #define DDR3_EMRS1_RTTNOM_60 0x04
  129. #define DDR3_EMRS1_RTTNOM_120 0x40
  130. #define DDR3_EMRS1_RTTNOM_40 0x44
  131. #define DDR3_EMRS1_RTTNOM_20 0x200
  132. #define DDR3_EMRS1_RTTNOM_30 0x204
  133. #define DDR3_EMRS2_RTTWR_60 (1 << 9)
  134. #define DDR3_EMRS2_RTTWR_120 (1 << 10)
  135. /* BEGIN DDRIO Registers */
  136. /* DDR IOs & COMPs */
  137. #define DDRIODQ_BL_OFFSET 0x0800
  138. #define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES / 2) * DDRIODQ_BL_OFFSET)
  139. #define DDRIOCCC_CH_OFFSET 0x0800
  140. #define DDRCOMP_CH_OFFSET 0x0100
  141. /* CH0-BL01-DQ */
  142. #define DQOBSCKEBBCTL 0x0000
  143. #define DQDLLTXCTL 0x0004
  144. #define DQDLLRXCTL 0x0008
  145. #define DQMDLLCTL 0x000c
  146. #define B0RXIOBUFCTL 0x0010
  147. #define B0VREFCTL 0x0014
  148. #define B0RXOFFSET1 0x0018
  149. #define B0RXOFFSET0 0x001c
  150. #define B1RXIOBUFCTL 0x0020
  151. #define B1VREFCTL 0x0024
  152. #define B1RXOFFSET1 0x0028
  153. #define B1RXOFFSET0 0x002c
  154. #define DQDFTCTL 0x0030
  155. #define DQTRAINSTS 0x0034
  156. #define B1DLLPICODER0 0x0038
  157. #define B0DLLPICODER0 0x003c
  158. #define B1DLLPICODER1 0x0040
  159. #define B0DLLPICODER1 0x0044
  160. #define B1DLLPICODER2 0x0048
  161. #define B0DLLPICODER2 0x004c
  162. #define B1DLLPICODER3 0x0050
  163. #define B0DLLPICODER3 0x0054
  164. #define B1RXDQSPICODE 0x0058
  165. #define B0RXDQSPICODE 0x005c
  166. #define B1RXDQPICODER32 0x0060
  167. #define B1RXDQPICODER10 0x0064
  168. #define B0RXDQPICODER32 0x0068
  169. #define B0RXDQPICODER10 0x006c
  170. #define B01PTRCTL0 0x0070
  171. #define B01PTRCTL1 0x0074
  172. #define B01DBCTL0 0x0078
  173. #define B01DBCTL1 0x007c
  174. #define B0LATCTL0 0x0080
  175. #define B1LATCTL0 0x0084
  176. #define B01LATCTL1 0x0088
  177. #define B0ONDURCTL 0x008c
  178. #define B1ONDURCTL 0x0090
  179. #define B0OVRCTL 0x0094
  180. #define B1OVRCTL 0x0098
  181. #define DQCTL 0x009c
  182. #define B0RK2RKCHGPTRCTRL 0x00a0
  183. #define B1RK2RKCHGPTRCTRL 0x00a4
  184. #define DQRK2RKCTL 0x00a8
  185. #define DQRK2RKPTRCTL 0x00ac
  186. #define B0RK2RKLAT 0x00b0
  187. #define B1RK2RKLAT 0x00b4
  188. #define DQCLKALIGNREG0 0x00b8
  189. #define DQCLKALIGNREG1 0x00bc
  190. #define DQCLKALIGNREG2 0x00c0
  191. #define DQCLKALIGNSTS0 0x00c4
  192. #define DQCLKALIGNSTS1 0x00c8
  193. #define DQCLKGATE 0x00cc
  194. #define B0COMPSLV1 0x00d0
  195. #define B1COMPSLV1 0x00d4
  196. #define B0COMPSLV2 0x00d8
  197. #define B1COMPSLV2 0x00dc
  198. #define B0COMPSLV3 0x00e0
  199. #define B1COMPSLV3 0x00e4
  200. #define DQVISALANECR0TOP 0x00e8
  201. #define DQVISALANECR1TOP 0x00ec
  202. #define DQVISACONTROLCRTOP 0x00f0
  203. #define DQVISALANECR0BL 0x00f4
  204. #define DQVISALANECR1BL 0x00f8
  205. #define DQVISACONTROLCRBL 0x00fc
  206. #define DQTIMINGCTRL 0x010c
  207. /* CH0-ECC */
  208. #define ECCDLLTXCTL 0x2004
  209. #define ECCDLLRXCTL 0x2008
  210. #define ECCMDLLCTL 0x200c
  211. #define ECCB1DLLPICODER0 0x2038
  212. #define ECCB1DLLPICODER1 0x2040
  213. #define ECCB1DLLPICODER2 0x2048
  214. #define ECCB1DLLPICODER3 0x2050
  215. #define ECCB01DBCTL0 0x2078
  216. #define ECCB01DBCTL1 0x207c
  217. #define ECCCLKALIGNREG0 0x20b8
  218. #define ECCCLKALIGNREG1 0x20bc
  219. #define ECCCLKALIGNREG2 0x20c0
  220. /* CH0-CMD */
  221. #define CMDOBSCKEBBCTL 0x4800
  222. #define CMDDLLTXCTL 0x4808
  223. #define CMDDLLRXCTL 0x480c
  224. #define CMDMDLLCTL 0x4810
  225. #define CMDRCOMPODT 0x4814
  226. #define CMDDLLPICODER0 0x4820
  227. #define CMDDLLPICODER1 0x4824
  228. #define CMDCFGREG0 0x4840
  229. #define CMDPTRREG 0x4844
  230. #define CMDCLKALIGNREG0 0x4850
  231. #define CMDCLKALIGNREG1 0x4854
  232. #define CMDCLKALIGNREG2 0x4858
  233. #define CMDPMCONFIG0 0x485c
  234. #define CMDPMDLYREG0 0x4860
  235. #define CMDPMDLYREG1 0x4864
  236. #define CMDPMDLYREG2 0x4868
  237. #define CMDPMDLYREG3 0x486c
  238. #define CMDPMDLYREG4 0x4870
  239. #define CMDCLKALIGNSTS0 0x4874
  240. #define CMDCLKALIGNSTS1 0x4878
  241. #define CMDPMSTS0 0x487c
  242. #define CMDPMSTS1 0x4880
  243. #define CMDCOMPSLV 0x4884
  244. #define CMDBONUS0 0x488c
  245. #define CMDBONUS1 0x4890
  246. #define CMDVISALANECR0 0x4894
  247. #define CMDVISALANECR1 0x4898
  248. #define CMDVISACONTROLCR 0x489c
  249. #define CMDCLKGATE 0x48a0
  250. #define CMDTIMINGCTRL 0x48a4
  251. /* CH0-CLK-CTL */
  252. #define CCOBSCKEBBCTL 0x5800
  253. #define CCRCOMPIO 0x5804
  254. #define CCDLLTXCTL 0x5808
  255. #define CCDLLRXCTL 0x580c
  256. #define CCMDLLCTL 0x5810
  257. #define CCRCOMPODT 0x5814
  258. #define CCDLLPICODER0 0x5820
  259. #define CCDLLPICODER1 0x5824
  260. #define CCDDR3RESETCTL 0x5830
  261. #define CCCFGREG0 0x5838
  262. #define CCCFGREG1 0x5840
  263. #define CCPTRREG 0x5844
  264. #define CCCLKALIGNREG0 0x5850
  265. #define CCCLKALIGNREG1 0x5854
  266. #define CCCLKALIGNREG2 0x5858
  267. #define CCPMCONFIG0 0x585c
  268. #define CCPMDLYREG0 0x5860
  269. #define CCPMDLYREG1 0x5864
  270. #define CCPMDLYREG2 0x5868
  271. #define CCPMDLYREG3 0x586c
  272. #define CCPMDLYREG4 0x5870
  273. #define CCCLKALIGNSTS0 0x5874
  274. #define CCCLKALIGNSTS1 0x5878
  275. #define CCPMSTS0 0x587c
  276. #define CCPMSTS1 0x5880
  277. #define CCCOMPSLV1 0x5884
  278. #define CCCOMPSLV2 0x5888
  279. #define CCCOMPSLV3 0x588c
  280. #define CCBONUS0 0x5894
  281. #define CCBONUS1 0x5898
  282. #define CCVISALANECR0 0x589c
  283. #define CCVISALANECR1 0x58a0
  284. #define CCVISACONTROLCR 0x58a4
  285. #define CCCLKGATE 0x58a8
  286. #define CCTIMINGCTL 0x58ac
  287. /* COMP */
  288. #define CMPCTRL 0x6800
  289. #define SOFTRSTCNTL 0x6804
  290. #define MSCNTR 0x6808
  291. #define NMSCNTRL 0x680c
  292. #define LATCH1CTL 0x6814
  293. #define COMPVISALANECR0 0x681c
  294. #define COMPVISALANECR1 0x6820
  295. #define COMPVISACONTROLCR 0x6824
  296. #define COMPBONUS0 0x6830
  297. #define TCOCNTCTRL 0x683c
  298. #define DQANAODTPUCTL 0x6840
  299. #define DQANAODTPDCTL 0x6844
  300. #define DQANADRVPUCTL 0x6848
  301. #define DQANADRVPDCTL 0x684c
  302. #define DQANADLYPUCTL 0x6850
  303. #define DQANADLYPDCTL 0x6854
  304. #define DQANATCOPUCTL 0x6858
  305. #define DQANATCOPDCTL 0x685c
  306. #define CMDANADRVPUCTL 0x6868
  307. #define CMDANADRVPDCTL 0x686c
  308. #define CMDANADLYPUCTL 0x6870
  309. #define CMDANADLYPDCTL 0x6874
  310. #define CLKANAODTPUCTL 0x6880
  311. #define CLKANAODTPDCTL 0x6884
  312. #define CLKANADRVPUCTL 0x6888
  313. #define CLKANADRVPDCTL 0x688c
  314. #define CLKANADLYPUCTL 0x6890
  315. #define CLKANADLYPDCTL 0x6894
  316. #define CLKANATCOPUCTL 0x6898
  317. #define CLKANATCOPDCTL 0x689c
  318. #define DQSANAODTPUCTL 0x68a0
  319. #define DQSANAODTPDCTL 0x68a4
  320. #define DQSANADRVPUCTL 0x68a8
  321. #define DQSANADRVPDCTL 0x68ac
  322. #define DQSANADLYPUCTL 0x68b0
  323. #define DQSANADLYPDCTL 0x68b4
  324. #define DQSANATCOPUCTL 0x68b8
  325. #define DQSANATCOPDCTL 0x68bc
  326. #define CTLANADRVPUCTL 0x68c8
  327. #define CTLANADRVPDCTL 0x68cc
  328. #define CTLANADLYPUCTL 0x68d0
  329. #define CTLANADLYPDCTL 0x68d4
  330. #define CHNLBUFSTATIC 0x68f0
  331. #define COMPOBSCNTRL 0x68f4
  332. #define COMPBUFFDBG0 0x68f8
  333. #define COMPBUFFDBG1 0x68fc
  334. #define CFGMISCCH0 0x6900
  335. #define COMPEN0CH0 0x6904
  336. #define COMPEN1CH0 0x6908
  337. #define COMPEN2CH0 0x690c
  338. #define STATLEGEN0CH0 0x6910
  339. #define STATLEGEN1CH0 0x6914
  340. #define DQVREFCH0 0x6918
  341. #define CMDVREFCH0 0x691c
  342. #define CLKVREFCH0 0x6920
  343. #define DQSVREFCH0 0x6924
  344. #define CTLVREFCH0 0x6928
  345. #define TCOVREFCH0 0x692c
  346. #define DLYSELCH0 0x6930
  347. #define TCODRAMBUFODTCH0 0x6934
  348. #define CCBUFODTCH0 0x6938
  349. #define RXOFFSETCH0 0x693c
  350. #define DQODTPUCTLCH0 0x6940
  351. #define DQODTPDCTLCH0 0x6944
  352. #define DQDRVPUCTLCH0 0x6948
  353. #define DQDRVPDCTLCH0 0x694c
  354. #define DQDLYPUCTLCH0 0x6950
  355. #define DQDLYPDCTLCH0 0x6954
  356. #define DQTCOPUCTLCH0 0x6958
  357. #define DQTCOPDCTLCH0 0x695c
  358. #define CMDDRVPUCTLCH0 0x6968
  359. #define CMDDRVPDCTLCH0 0x696c
  360. #define CMDDLYPUCTLCH0 0x6970
  361. #define CMDDLYPDCTLCH0 0x6974
  362. #define CLKODTPUCTLCH0 0x6980
  363. #define CLKODTPDCTLCH0 0x6984
  364. #define CLKDRVPUCTLCH0 0x6988
  365. #define CLKDRVPDCTLCH0 0x698c
  366. #define CLKDLYPUCTLCH0 0x6990
  367. #define CLKDLYPDCTLCH0 0x6994
  368. #define CLKTCOPUCTLCH0 0x6998
  369. #define CLKTCOPDCTLCH0 0x699c
  370. #define DQSODTPUCTLCH0 0x69a0
  371. #define DQSODTPDCTLCH0 0x69a4
  372. #define DQSDRVPUCTLCH0 0x69a8
  373. #define DQSDRVPDCTLCH0 0x69ac
  374. #define DQSDLYPUCTLCH0 0x69b0
  375. #define DQSDLYPDCTLCH0 0x69b4
  376. #define DQSTCOPUCTLCH0 0x69b8
  377. #define DQSTCOPDCTLCH0 0x69bc
  378. #define CTLDRVPUCTLCH0 0x69c8
  379. #define CTLDRVPDCTLCH0 0x69cc
  380. #define CTLDLYPUCTLCH0 0x69d0
  381. #define CTLDLYPDCTLCH0 0x69d4
  382. #define FNLUPDTCTLCH0 0x69f0
  383. /* PLL */
  384. #define MPLLCTRL0 0x7800
  385. #define MPLLCTRL1 0x7808
  386. #define MPLLCSR0 0x7810
  387. #define MPLLCSR1 0x7814
  388. #define MPLLCSR2 0x7820
  389. #define MPLLDFT 0x7828
  390. #define MPLLMON0CTL 0x7830
  391. #define MPLLMON1CTL 0x7838
  392. #define MPLLMON2CTL 0x783c
  393. #define SFRTRIM 0x7850
  394. #define MPLLDFTOUT0 0x7858
  395. #define MPLLDFTOUT1 0x785c
  396. #define MASTERRSTN 0x7880
  397. #define PLLLOCKDEL 0x7884
  398. #define SFRDEL 0x7888
  399. #define CRUVISALANECR0 0x78f0
  400. #define CRUVISALANECR1 0x78f4
  401. #define CRUVISACONTROLCR 0x78f8
  402. #define IOSFVISALANECR0 0x78fc
  403. #define IOSFVISALANECR1 0x7900
  404. #define IOSFVISACONTROLCR 0x7904
  405. /* END DDRIO Registers */
  406. /* DRAM Specific Message Bus OpCodes */
  407. #define MSG_OP_DRAM_INIT 0x68
  408. #define MSG_OP_DRAM_WAKE 0xca
  409. #define SAMPLE_SIZE 6
  410. /* must be less than this number to enable early deadband */
  411. #define EARLY_DB 0x12
  412. /* must be greater than this number to enable late deadband */
  413. #define LATE_DB 0x34
  414. #define CHX_REGS (11 * 4)
  415. #define FULL_CLK 128
  416. #define HALF_CLK 64
  417. #define QRTR_CLK 32
  418. #define MCEIL(num, den) ((uint8_t)((num + den - 1) / den))
  419. #define MMAX(a, b) ((a) > (b) ? (a) : (b))
  420. #define DEAD_LOOP() for (;;);
  421. #define MIN_RDQS_EYE 10 /* in PI Codes */
  422. #define MIN_VREF_EYE 10 /* in VREF Codes */
  423. /* how many RDQS codes to jump while margining */
  424. #define RDQS_STEP 1
  425. /* how many VREF codes to jump while margining */
  426. #define VREF_STEP 1
  427. /* offset into "vref_codes[]" for minimum allowed VREF setting */
  428. #define VREF_MIN 0x00
  429. /* offset into "vref_codes[]" for maximum allowed VREF setting */
  430. #define VREF_MAX 0x3f
  431. #define RDQS_MIN 0x00 /* minimum RDQS delay value */
  432. #define RDQS_MAX 0x3f /* maximum RDQS delay value */
  433. /* how many WDQ codes to jump while margining */
  434. #define WDQ_STEP 1
  435. enum {
  436. B, /* BOTTOM VREF */
  437. T /* TOP VREF */
  438. };
  439. enum {
  440. L, /* LEFT RDQS */
  441. R /* RIGHT RDQS */
  442. };
  443. /* Memory Options */
  444. /* enable STATIC timing settings for RCVN (BACKUP_MODE) */
  445. #undef BACKUP_RCVN
  446. /* enable STATIC timing settings for WDQS (BACKUP_MODE) */
  447. #undef BACKUP_WDQS
  448. /* enable STATIC timing settings for RDQS (BACKUP_MODE) */
  449. #undef BACKUP_RDQS
  450. /* enable STATIC timing settings for WDQ (BACKUP_MODE) */
  451. #undef BACKUP_WDQ
  452. /* enable *COMP overrides (BACKUP_MODE) */
  453. #undef BACKUP_COMPS
  454. /* enable the RD_TRAIN eye check */
  455. #undef RX_EYE_CHECK
  456. /* enable Host to Memory Clock Alignment */
  457. #define HMC_TEST
  458. /* enable multi-rank support via rank2rank sharing */
  459. #define R2R_SHARING
  460. /* disable signals not used in 16bit mode of DDRIO */
  461. #define FORCE_16BIT_DDRIO
  462. #define PLATFORM_ID 1
  463. void clear_self_refresh(struct mrc_params *mrc_params);
  464. void prog_ddr_timing_control(struct mrc_params *mrc_params);
  465. void prog_decode_before_jedec(struct mrc_params *mrc_params);
  466. void perform_ddr_reset(struct mrc_params *mrc_params);
  467. void ddrphy_init(struct mrc_params *mrc_params);
  468. void perform_jedec_init(struct mrc_params *mrc_params);
  469. void set_ddr_init_complete(struct mrc_params *mrc_params);
  470. void restore_timings(struct mrc_params *mrc_params);
  471. void default_timings(struct mrc_params *mrc_params);
  472. void rcvn_cal(struct mrc_params *mrc_params);
  473. void wr_level(struct mrc_params *mrc_params);
  474. void prog_page_ctrl(struct mrc_params *mrc_params);
  475. void rd_train(struct mrc_params *mrc_params);
  476. void wr_train(struct mrc_params *mrc_params);
  477. void store_timings(struct mrc_params *mrc_params);
  478. void enable_scrambling(struct mrc_params *mrc_params);
  479. void prog_ddr_control(struct mrc_params *mrc_params);
  480. void prog_dra_drb(struct mrc_params *mrc_params);
  481. void perform_wake(struct mrc_params *mrc_params);
  482. void change_refresh_period(struct mrc_params *mrc_params);
  483. void set_auto_refresh(struct mrc_params *mrc_params);
  484. void ecc_enable(struct mrc_params *mrc_params);
  485. void memory_test(struct mrc_params *mrc_params);
  486. void lock_registers(struct mrc_params *mrc_params);
  487. #endif /* _SMC_H_ */