xor.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #ifndef _XOR_H
  6. #define _XOR_H
  7. #define SRAM_BASE 0x40000000
  8. #define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */
  9. #define MV_XOR_MAX_CHAN 4 /* total channels for all units */
  10. #define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */
  11. #define MV_IS_POWER_OF_2(num) (((num) != 0) && (((num) & ((num) - 1)) == 0))
  12. /*
  13. * This structure describes address space window. Window base can be
  14. * 64 bit, window size up to 4GB
  15. */
  16. struct addr_win {
  17. u32 base_low; /* 32bit base low */
  18. u32 base_high; /* 32bit base high */
  19. u32 size; /* 32bit size */
  20. };
  21. /* This structure describes SoC units address decode window */
  22. struct unit_win_info {
  23. struct addr_win addr_win; /* An address window */
  24. int enable; /* Address decode window is enabled/disabled */
  25. u8 attrib; /* chip select attributes */
  26. u8 target_id; /* Target Id of this MV_TARGET */
  27. };
  28. /*
  29. * This enumerator describes the type of functionality the XOR channel
  30. * can have while using the same data structures.
  31. */
  32. enum xor_type {
  33. MV_XOR, /* XOR channel functions as XOR accelerator */
  34. MV_DMA, /* XOR channel functions as IDMA channel */
  35. MV_CRC32 /* XOR channel functions as CRC 32 calculator */
  36. };
  37. enum mv_state {
  38. MV_IDLE,
  39. MV_ACTIVE,
  40. MV_PAUSED,
  41. MV_UNDEFINED_STATE
  42. };
  43. /*
  44. * This enumerator describes the set of commands that can be applied on
  45. * an engine (e.g. IDMA, XOR). Appling a comman depends on the current
  46. * status (see MV_STATE enumerator)
  47. *
  48. * Start can be applied only when status is IDLE
  49. * Stop can be applied only when status is IDLE, ACTIVE or PAUSED
  50. * Pause can be applied only when status is ACTIVE
  51. * Restart can be applied only when status is PAUSED
  52. */
  53. enum mv_command {
  54. MV_START, /* Start */
  55. MV_STOP, /* Stop */
  56. MV_PAUSE, /* Pause */
  57. MV_RESTART /* Restart */
  58. };
  59. enum xor_override_target {
  60. SRC_ADDR0, /* Source Address #0 Control */
  61. SRC_ADDR1, /* Source Address #1 Control */
  62. SRC_ADDR2, /* Source Address #2 Control */
  63. SRC_ADDR3, /* Source Address #3 Control */
  64. SRC_ADDR4, /* Source Address #4 Control */
  65. SRC_ADDR5, /* Source Address #5 Control */
  66. SRC_ADDR6, /* Source Address #6 Control */
  67. SRC_ADDR7, /* Source Address #7 Control */
  68. XOR_DST_ADDR, /* Destination Address Control */
  69. XOR_NEXT_DESC /* Next Descriptor Address Control */
  70. };
  71. enum mv_state mv_xor_state_get(u32 chan);
  72. void mv_xor_hal_init(u32 xor_chan_num);
  73. int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
  74. int mv_xor_command_set(u32 chan, enum mv_command command);
  75. int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num,
  76. int enable);
  77. int mv_xor_transfer(u32 chan, enum xor_type type, u32 xor_chain_ptr);
  78. #endif