pinctrl_ar933x.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <asm/io.h>
  9. #include <dm/pinctrl.h>
  10. #include <mach/ar71xx_regs.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. enum periph_id {
  13. PERIPH_ID_UART0,
  14. PERIPH_ID_SPI0,
  15. PERIPH_ID_NONE = -1,
  16. };
  17. struct ar933x_pinctrl_priv {
  18. void __iomem *regs;
  19. };
  20. static void pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv *priv, int cs)
  21. {
  22. switch (cs) {
  23. case 0:
  24. clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
  25. AR933X_GPIO(4), AR933X_GPIO(3) |
  26. AR933X_GPIO(5) | AR933X_GPIO(2));
  27. setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
  28. AR933X_GPIO_FUNC_SPI_EN |
  29. AR933X_GPIO_FUNC_RES_TRUE);
  30. break;
  31. }
  32. }
  33. static void pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv *priv, int uart_id)
  34. {
  35. switch (uart_id) {
  36. case PERIPH_ID_UART0:
  37. clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
  38. AR933X_GPIO(9), AR933X_GPIO(10));
  39. setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
  40. AR933X_GPIO_FUNC_UART_EN |
  41. AR933X_GPIO_FUNC_RES_TRUE);
  42. break;
  43. }
  44. }
  45. static int ar933x_pinctrl_request(struct udevice *dev, int func, int flags)
  46. {
  47. struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
  48. debug("%s: func=%x, flags=%x\n", __func__, func, flags);
  49. switch (func) {
  50. case PERIPH_ID_SPI0:
  51. pinctrl_ar933x_spi_config(priv, flags);
  52. break;
  53. case PERIPH_ID_UART0:
  54. pinctrl_ar933x_uart_config(priv, func);
  55. break;
  56. default:
  57. return -EINVAL;
  58. }
  59. return 0;
  60. }
  61. static int ar933x_pinctrl_get_periph_id(struct udevice *dev,
  62. struct udevice *periph)
  63. {
  64. u32 cell[2];
  65. int ret;
  66. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
  67. "interrupts", cell, ARRAY_SIZE(cell));
  68. if (ret < 0)
  69. return -EINVAL;
  70. switch (cell[0]) {
  71. case 128:
  72. return PERIPH_ID_UART0;
  73. case 129:
  74. return PERIPH_ID_SPI0;
  75. }
  76. return -ENOENT;
  77. }
  78. static int ar933x_pinctrl_set_state_simple(struct udevice *dev,
  79. struct udevice *periph)
  80. {
  81. int func;
  82. func = ar933x_pinctrl_get_periph_id(dev, periph);
  83. if (func < 0)
  84. return func;
  85. return ar933x_pinctrl_request(dev, func, 0);
  86. }
  87. static struct pinctrl_ops ar933x_pinctrl_ops = {
  88. .set_state_simple = ar933x_pinctrl_set_state_simple,
  89. .request = ar933x_pinctrl_request,
  90. .get_periph_id = ar933x_pinctrl_get_periph_id,
  91. };
  92. static int ar933x_pinctrl_probe(struct udevice *dev)
  93. {
  94. struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
  95. fdt_addr_t addr;
  96. addr = devfdt_get_addr(dev);
  97. if (addr == FDT_ADDR_T_NONE)
  98. return -EINVAL;
  99. priv->regs = map_physmem(addr,
  100. AR71XX_GPIO_SIZE,
  101. MAP_NOCACHE);
  102. return 0;
  103. }
  104. static const struct udevice_id ar933x_pinctrl_ids[] = {
  105. { .compatible = "qca,ar933x-pinctrl" },
  106. { }
  107. };
  108. U_BOOT_DRIVER(pinctrl_ar933x) = {
  109. .name = "pinctrl_ar933x",
  110. .id = UCLASS_PINCTRL,
  111. .of_match = ar933x_pinctrl_ids,
  112. .priv_auto_alloc_size = sizeof(struct ar933x_pinctrl_priv),
  113. .ops = &ar933x_pinctrl_ops,
  114. .probe = ar933x_pinctrl_probe,
  115. };