ohci-hcd.c 58 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
  4. *
  5. * Interrupt support is added. Now, it has been tested
  6. * on ULI1575 chip and works well with USB keyboard.
  7. *
  8. * (C) Copyright 2007
  9. * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
  10. *
  11. * (C) Copyright 2003
  12. * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
  13. *
  14. * Note: Much of this code has been derived from Linux 2.4
  15. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  16. * (C) Copyright 2000-2002 David Brownell
  17. *
  18. * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
  19. * ebenard@eukrea.com - based on s3c24x0's driver
  20. */
  21. /*
  22. * IMPORTANT NOTES
  23. * 1 - Read doc/README.generic_usb_ohci
  24. * 2 - this driver is intended for use with USB Mass Storage Devices
  25. * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
  26. * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
  27. * to activate workaround for bug #41 or this driver will NOT work!
  28. */
  29. #include <common.h>
  30. #include <asm/byteorder.h>
  31. #include <dm.h>
  32. #include <errno.h>
  33. #if defined(CONFIG_PCI_OHCI)
  34. # include <pci.h>
  35. #if !defined(CONFIG_PCI_OHCI_DEVNO)
  36. #define CONFIG_PCI_OHCI_DEVNO 0
  37. #endif
  38. #endif
  39. #include <malloc.h>
  40. #include <memalign.h>
  41. #include <usb.h>
  42. #include "ohci.h"
  43. #ifdef CONFIG_AT91RM9200
  44. #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
  45. #endif
  46. #if defined(CONFIG_CPU_ARM920T) || \
  47. defined(CONFIG_PCI_OHCI) || \
  48. defined(CONFIG_SYS_OHCI_USE_NPS)
  49. # define OHCI_USE_NPS /* force NoPowerSwitching mode */
  50. #endif
  51. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  52. #undef DEBUG
  53. #undef SHOW_INFO
  54. #undef OHCI_FILL_TRACE
  55. /* For initializing controller (mask in an HCFS mode too) */
  56. #define OHCI_CONTROL_INIT \
  57. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  58. #ifdef CONFIG_PCI_OHCI
  59. static struct pci_device_id ohci_pci_ids[] = {
  60. {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
  61. {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
  62. {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */
  63. /* Please add supported PCI OHCI controller ids here */
  64. {0, 0}
  65. };
  66. #endif
  67. #ifdef CONFIG_PCI_EHCI_DEVNO
  68. static struct pci_device_id ehci_pci_ids[] = {
  69. {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */
  70. /* Please add supported PCI EHCI controller ids here */
  71. {0, 0}
  72. };
  73. #endif
  74. #ifdef DEBUG
  75. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  76. #else
  77. #define dbg(format, arg...) do {} while (0)
  78. #endif /* DEBUG */
  79. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  80. #ifdef SHOW_INFO
  81. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  82. #else
  83. #define info(format, arg...) do {} while (0)
  84. #endif
  85. #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER
  86. # define m16_swap(x) cpu_to_be16(x)
  87. # define m32_swap(x) cpu_to_be32(x)
  88. #else
  89. # define m16_swap(x) cpu_to_le16(x)
  90. # define m32_swap(x) cpu_to_le32(x)
  91. #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */
  92. /* We really should do proper cache flushing everywhere */
  93. #define flush_dcache_buffer(addr, size) \
  94. flush_dcache_range((unsigned long)(addr), \
  95. ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
  96. #define invalidate_dcache_buffer(addr, size) \
  97. invalidate_dcache_range((unsigned long)(addr), \
  98. ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
  99. /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */
  100. #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16)
  101. #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16)
  102. #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32)
  103. #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256)
  104. #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16)
  105. #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16)
  106. #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32)
  107. #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256)
  108. #ifdef CONFIG_DM_USB
  109. /*
  110. * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep
  111. * them around when building for older boards not yet converted to the dm
  112. * just in case (to avoid regressions), for dm this turns them into nops.
  113. */
  114. #define ohci_mdelay(x)
  115. #else
  116. #define ohci_mdelay(x) mdelay(x)
  117. #endif
  118. #ifndef CONFIG_DM_USB
  119. /* global ohci_t */
  120. static ohci_t gohci;
  121. /* this must be aligned to a 256 byte boundary */
  122. struct ohci_hcca ghcca[1];
  123. #endif
  124. /* mapping of the OHCI CC status to error codes */
  125. static int cc_to_error[16] = {
  126. /* No Error */ 0,
  127. /* CRC Error */ USB_ST_CRC_ERR,
  128. /* Bit Stuff */ USB_ST_BIT_ERR,
  129. /* Data Togg */ USB_ST_CRC_ERR,
  130. /* Stall */ USB_ST_STALLED,
  131. /* DevNotResp */ -1,
  132. /* PIDCheck */ USB_ST_BIT_ERR,
  133. /* UnExpPID */ USB_ST_BIT_ERR,
  134. /* DataOver */ USB_ST_BUF_ERR,
  135. /* DataUnder */ USB_ST_BUF_ERR,
  136. /* reservd */ -1,
  137. /* reservd */ -1,
  138. /* BufferOver */ USB_ST_BUF_ERR,
  139. /* BuffUnder */ USB_ST_BUF_ERR,
  140. /* Not Access */ -1,
  141. /* Not Access */ -1
  142. };
  143. static const char *cc_to_string[16] = {
  144. "No Error",
  145. "CRC: Last data packet from endpoint contained a CRC error.",
  146. "BITSTUFFING: Last data packet from endpoint contained a bit " \
  147. "stuffing violation",
  148. "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \
  149. "that did not match the expected value.",
  150. "STALL: TD was moved to the Done Queue because the endpoint returned" \
  151. " a STALL PID",
  152. "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \
  153. "not provide a handshake (OUT)",
  154. "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\
  155. "(IN) or handshake (OUT)",
  156. "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \
  157. "value is not defined.",
  158. "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \
  159. "either the size of the maximum data packet allowed\n" \
  160. "from the endpoint (found in MaximumPacketSize field\n" \
  161. "of ED) or the remaining buffer size.",
  162. "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \
  163. "and that amount was not sufficient to fill the\n" \
  164. "specified buffer",
  165. "reserved1",
  166. "reserved2",
  167. "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \
  168. "than it could be written to system memory",
  169. "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \
  170. "system memory fast enough to keep up with data USB " \
  171. "data rate.",
  172. "NOT ACCESSED: This code is set by software before the TD is placed" \
  173. "on a list to be processed by the HC.(1)",
  174. "NOT ACCESSED: This code is set by software before the TD is placed" \
  175. "on a list to be processed by the HC.(2)",
  176. };
  177. static inline u32 roothub_a(struct ohci *hc)
  178. { return ohci_readl(&hc->regs->roothub.a); }
  179. static inline u32 roothub_b(struct ohci *hc)
  180. { return ohci_readl(&hc->regs->roothub.b); }
  181. static inline u32 roothub_status(struct ohci *hc)
  182. { return ohci_readl(&hc->regs->roothub.status); }
  183. static inline u32 roothub_portstatus(struct ohci *hc, int i)
  184. { return ohci_readl(&hc->regs->roothub.portstatus[i]); }
  185. /* forward declaration */
  186. static int hc_interrupt(ohci_t *ohci);
  187. static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
  188. unsigned long pipe, void *buffer, int transfer_len,
  189. struct devrequest *setup, urb_priv_t *urb,
  190. int interval);
  191. static int ep_link(ohci_t * ohci, ed_t * ed);
  192. static int ep_unlink(ohci_t * ohci, ed_t * ed);
  193. static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
  194. unsigned long pipe, int interval, int load);
  195. /*-------------------------------------------------------------------------*/
  196. /* TDs ... */
  197. static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev)
  198. {
  199. int i;
  200. struct td *td;
  201. td = NULL;
  202. for (i = 0; i < NUM_TD; i++)
  203. {
  204. if (ohci_dev->tds[i].usb_dev == NULL)
  205. {
  206. td = &ohci_dev->tds[i];
  207. td->usb_dev = usb_dev;
  208. break;
  209. }
  210. }
  211. return td;
  212. }
  213. static inline void ed_free(struct ed *ed)
  214. {
  215. ed->usb_dev = NULL;
  216. }
  217. /*-------------------------------------------------------------------------*
  218. * URB support functions
  219. *-------------------------------------------------------------------------*/
  220. /* free HCD-private data associated with this URB */
  221. static void urb_free_priv(urb_priv_t *urb)
  222. {
  223. int i;
  224. int last;
  225. struct td *td;
  226. last = urb->length - 1;
  227. if (last >= 0) {
  228. for (i = 0; i <= last; i++) {
  229. td = urb->td[i];
  230. if (td) {
  231. td->usb_dev = NULL;
  232. urb->td[i] = NULL;
  233. }
  234. }
  235. }
  236. free(urb);
  237. }
  238. /*-------------------------------------------------------------------------*/
  239. #ifdef DEBUG
  240. static int sohci_get_current_frame_number(ohci_t *ohci);
  241. /* debug| print the main components of an URB
  242. * small: 0) header + data packets 1) just header */
  243. static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev,
  244. unsigned long pipe, void *buffer, int transfer_len,
  245. struct devrequest *setup, char *str, int small)
  246. {
  247. dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx",
  248. str,
  249. sohci_get_current_frame_number(ohci),
  250. usb_pipedevice(pipe),
  251. usb_pipeendpoint(pipe),
  252. usb_pipeout(pipe)? 'O': 'I',
  253. usb_pipetype(pipe) < 2 ? \
  254. (usb_pipeint(pipe)? "INTR": "ISOC"): \
  255. (usb_pipecontrol(pipe)? "CTRL": "BULK"),
  256. (purb ? purb->actual_length : 0),
  257. transfer_len, dev->status);
  258. #ifdef OHCI_VERBOSE_DEBUG
  259. if (!small) {
  260. int i, len;
  261. if (usb_pipecontrol(pipe)) {
  262. printf(__FILE__ ": cmd(8):");
  263. for (i = 0; i < 8 ; i++)
  264. printf(" %02x", ((__u8 *) setup) [i]);
  265. printf("\n");
  266. }
  267. if (transfer_len > 0 && buffer) {
  268. printf(__FILE__ ": data(%d/%d):",
  269. (purb ? purb->actual_length : 0),
  270. transfer_len);
  271. len = usb_pipeout(pipe)? transfer_len:
  272. (purb ? purb->actual_length : 0);
  273. for (i = 0; i < 16 && i < len; i++)
  274. printf(" %02x", ((__u8 *) buffer) [i]);
  275. printf("%s\n", i < len? "...": "");
  276. }
  277. }
  278. #endif
  279. }
  280. /* just for debugging; prints non-empty branches of the int ed tree
  281. * inclusive iso eds */
  282. void ep_print_int_eds(ohci_t *ohci, char *str)
  283. {
  284. int i, j;
  285. __u32 *ed_p;
  286. for (i = 0; i < 32; i++) {
  287. j = 5;
  288. ed_p = &(ohci->hcca->int_table [i]);
  289. if (*ed_p == 0)
  290. continue;
  291. invalidate_dcache_ed(ed_p);
  292. printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  293. while (*ed_p != 0 && j--) {
  294. ed_t *ed = (ed_t *)m32_swap(ed_p);
  295. invalidate_dcache_ed(ed);
  296. printf(" ed: %4x;", ed->hwINFO);
  297. ed_p = &ed->hwNextED;
  298. }
  299. printf("\n");
  300. }
  301. }
  302. static void ohci_dump_intr_mask(char *label, __u32 mask)
  303. {
  304. dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  305. label,
  306. mask,
  307. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  308. (mask & OHCI_INTR_OC) ? " OC" : "",
  309. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  310. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  311. (mask & OHCI_INTR_UE) ? " UE" : "",
  312. (mask & OHCI_INTR_RD) ? " RD" : "",
  313. (mask & OHCI_INTR_SF) ? " SF" : "",
  314. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  315. (mask & OHCI_INTR_SO) ? " SO" : ""
  316. );
  317. }
  318. static void maybe_print_eds(char *label, __u32 value)
  319. {
  320. ed_t *edp = (ed_t *)value;
  321. if (value) {
  322. dbg("%s %08x", label, value);
  323. invalidate_dcache_ed(edp);
  324. dbg("%08x", edp->hwINFO);
  325. dbg("%08x", edp->hwTailP);
  326. dbg("%08x", edp->hwHeadP);
  327. dbg("%08x", edp->hwNextED);
  328. }
  329. }
  330. static char *hcfs2string(int state)
  331. {
  332. switch (state) {
  333. case OHCI_USB_RESET: return "reset";
  334. case OHCI_USB_RESUME: return "resume";
  335. case OHCI_USB_OPER: return "operational";
  336. case OHCI_USB_SUSPEND: return "suspend";
  337. }
  338. return "?";
  339. }
  340. /* dump control and status registers */
  341. static void ohci_dump_status(ohci_t *controller)
  342. {
  343. struct ohci_regs *regs = controller->regs;
  344. __u32 temp;
  345. temp = ohci_readl(&regs->revision) & 0xff;
  346. if (temp != 0x10)
  347. dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
  348. temp = ohci_readl(&regs->control);
  349. dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  350. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  351. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  352. (temp & OHCI_CTRL_IR) ? " IR" : "",
  353. hcfs2string(temp & OHCI_CTRL_HCFS),
  354. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  355. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  356. (temp & OHCI_CTRL_IE) ? " IE" : "",
  357. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  358. temp & OHCI_CTRL_CBSR
  359. );
  360. temp = ohci_readl(&regs->cmdstatus);
  361. dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  362. (temp & OHCI_SOC) >> 16,
  363. (temp & OHCI_OCR) ? " OCR" : "",
  364. (temp & OHCI_BLF) ? " BLF" : "",
  365. (temp & OHCI_CLF) ? " CLF" : "",
  366. (temp & OHCI_HCR) ? " HCR" : ""
  367. );
  368. ohci_dump_intr_mask("intrstatus", ohci_readl(&regs->intrstatus));
  369. ohci_dump_intr_mask("intrenable", ohci_readl(&regs->intrenable));
  370. maybe_print_eds("ed_periodcurrent",
  371. ohci_readl(&regs->ed_periodcurrent));
  372. maybe_print_eds("ed_controlhead", ohci_readl(&regs->ed_controlhead));
  373. maybe_print_eds("ed_controlcurrent",
  374. ohci_readl(&regs->ed_controlcurrent));
  375. maybe_print_eds("ed_bulkhead", ohci_readl(&regs->ed_bulkhead));
  376. maybe_print_eds("ed_bulkcurrent", ohci_readl(&regs->ed_bulkcurrent));
  377. maybe_print_eds("donehead", ohci_readl(&regs->donehead));
  378. }
  379. static void ohci_dump_roothub(ohci_t *controller, int verbose)
  380. {
  381. __u32 temp, ndp, i;
  382. temp = roothub_a(controller);
  383. ndp = (temp & RH_A_NDP);
  384. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  385. ndp = (ndp == 2) ? 1:0;
  386. #endif
  387. if (verbose) {
  388. dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  389. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  390. (temp & RH_A_NOCP) ? " NOCP" : "",
  391. (temp & RH_A_OCPM) ? " OCPM" : "",
  392. (temp & RH_A_DT) ? " DT" : "",
  393. (temp & RH_A_NPS) ? " NPS" : "",
  394. (temp & RH_A_PSM) ? " PSM" : "",
  395. ndp
  396. );
  397. temp = roothub_b(controller);
  398. dbg("roothub.b: %08x PPCM=%04x DR=%04x",
  399. temp,
  400. (temp & RH_B_PPCM) >> 16,
  401. (temp & RH_B_DR)
  402. );
  403. temp = roothub_status(controller);
  404. dbg("roothub.status: %08x%s%s%s%s%s%s",
  405. temp,
  406. (temp & RH_HS_CRWE) ? " CRWE" : "",
  407. (temp & RH_HS_OCIC) ? " OCIC" : "",
  408. (temp & RH_HS_LPSC) ? " LPSC" : "",
  409. (temp & RH_HS_DRWE) ? " DRWE" : "",
  410. (temp & RH_HS_OCI) ? " OCI" : "",
  411. (temp & RH_HS_LPS) ? " LPS" : ""
  412. );
  413. }
  414. for (i = 0; i < ndp; i++) {
  415. temp = roothub_portstatus(controller, i);
  416. dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  417. i,
  418. temp,
  419. (temp & RH_PS_PRSC) ? " PRSC" : "",
  420. (temp & RH_PS_OCIC) ? " OCIC" : "",
  421. (temp & RH_PS_PSSC) ? " PSSC" : "",
  422. (temp & RH_PS_PESC) ? " PESC" : "",
  423. (temp & RH_PS_CSC) ? " CSC" : "",
  424. (temp & RH_PS_LSDA) ? " LSDA" : "",
  425. (temp & RH_PS_PPS) ? " PPS" : "",
  426. (temp & RH_PS_PRS) ? " PRS" : "",
  427. (temp & RH_PS_POCI) ? " POCI" : "",
  428. (temp & RH_PS_PSS) ? " PSS" : "",
  429. (temp & RH_PS_PES) ? " PES" : "",
  430. (temp & RH_PS_CCS) ? " CCS" : ""
  431. );
  432. }
  433. }
  434. static void ohci_dump(ohci_t *controller, int verbose)
  435. {
  436. dbg("OHCI controller usb-%s state", controller->slot_name);
  437. /* dumps some of the state we know about */
  438. ohci_dump_status(controller);
  439. if (verbose)
  440. ep_print_int_eds(controller, "hcca");
  441. invalidate_dcache_hcca(controller->hcca);
  442. dbg("hcca frame #%04x", controller->hcca->frame_no);
  443. ohci_dump_roothub(controller, 1);
  444. }
  445. #endif /* DEBUG */
  446. /*-------------------------------------------------------------------------*
  447. * Interface functions (URB)
  448. *-------------------------------------------------------------------------*/
  449. /* get a transfer request */
  450. int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb,
  451. struct devrequest *setup)
  452. {
  453. ed_t *ed;
  454. urb_priv_t *purb_priv = urb;
  455. int i, size = 0;
  456. struct usb_device *dev = urb->dev;
  457. unsigned long pipe = urb->pipe;
  458. void *buffer = urb->transfer_buffer;
  459. int transfer_len = urb->transfer_buffer_length;
  460. int interval = urb->interval;
  461. /* when controller's hung, permit only roothub cleanup attempts
  462. * such as powering down ports */
  463. if (ohci->disabled) {
  464. err("sohci_submit_job: EPIPE");
  465. return -1;
  466. }
  467. /* we're about to begin a new transaction here so mark the
  468. * URB unfinished */
  469. urb->finished = 0;
  470. /* every endpoint has a ed, locate and fill it */
  471. ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1);
  472. if (!ed) {
  473. err("sohci_submit_job: ENOMEM");
  474. return -1;
  475. }
  476. /* for the private part of the URB we need the number of TDs (size) */
  477. switch (usb_pipetype(pipe)) {
  478. case PIPE_BULK: /* one TD for every 4096 Byte */
  479. size = (transfer_len - 1) / 4096 + 1;
  480. break;
  481. case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  482. size = (transfer_len == 0)? 2:
  483. (transfer_len - 1) / 4096 + 3;
  484. break;
  485. case PIPE_INTERRUPT: /* 1 TD */
  486. size = 1;
  487. break;
  488. }
  489. ed->purb = urb;
  490. if (size >= (N_URB_TD - 1)) {
  491. err("need %d TDs, only have %d", size, N_URB_TD);
  492. return -1;
  493. }
  494. purb_priv->pipe = pipe;
  495. /* fill the private part of the URB */
  496. purb_priv->length = size;
  497. purb_priv->ed = ed;
  498. purb_priv->actual_length = 0;
  499. /* allocate the TDs */
  500. /* note that td[0] was allocated in ep_add_ed */
  501. for (i = 0; i < size; i++) {
  502. purb_priv->td[i] = td_alloc(ohci_dev, dev);
  503. if (!purb_priv->td[i]) {
  504. purb_priv->length = i;
  505. urb_free_priv(purb_priv);
  506. err("sohci_submit_job: ENOMEM");
  507. return -1;
  508. }
  509. }
  510. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  511. urb_free_priv(purb_priv);
  512. err("sohci_submit_job: EINVAL");
  513. return -1;
  514. }
  515. /* link the ed into a chain if is not already */
  516. if (ed->state != ED_OPER)
  517. ep_link(ohci, ed);
  518. /* fill the TDs and link it to the ed */
  519. td_submit_job(ohci, dev, pipe, buffer, transfer_len,
  520. setup, purb_priv, interval);
  521. return 0;
  522. }
  523. /*-------------------------------------------------------------------------*/
  524. #ifdef DEBUG
  525. /* tell us the current USB frame number */
  526. static int sohci_get_current_frame_number(ohci_t *ohci)
  527. {
  528. invalidate_dcache_hcca(ohci->hcca);
  529. return m16_swap(ohci->hcca->frame_no);
  530. }
  531. #endif
  532. /*-------------------------------------------------------------------------*
  533. * ED handling functions
  534. *-------------------------------------------------------------------------*/
  535. /* search for the right branch to insert an interrupt ed into the int tree
  536. * do some load ballancing;
  537. * returns the branch and
  538. * sets the interval to interval = 2^integer (ld (interval)) */
  539. static int ep_int_ballance(ohci_t *ohci, int interval, int load)
  540. {
  541. int i, branch = 0;
  542. /* search for the least loaded interrupt endpoint
  543. * branch of all 32 branches
  544. */
  545. for (i = 0; i < 32; i++)
  546. if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
  547. branch = i;
  548. branch = branch % interval;
  549. for (i = branch; i < 32; i += interval)
  550. ohci->ohci_int_load [i] += load;
  551. return branch;
  552. }
  553. /*-------------------------------------------------------------------------*/
  554. /* 2^int( ld (inter)) */
  555. static int ep_2_n_interval(int inter)
  556. {
  557. int i;
  558. for (i = 0; ((inter >> i) > 1) && (i < 5); i++);
  559. return 1 << i;
  560. }
  561. /*-------------------------------------------------------------------------*/
  562. /* the int tree is a binary tree
  563. * in order to process it sequentially the indexes of the branches have to
  564. * be mapped the mapping reverses the bits of a word of num_bits length */
  565. static int ep_rev(int num_bits, int word)
  566. {
  567. int i, wout = 0;
  568. for (i = 0; i < num_bits; i++)
  569. wout |= (((word >> i) & 1) << (num_bits - i - 1));
  570. return wout;
  571. }
  572. /*-------------------------------------------------------------------------*
  573. * ED handling functions
  574. *-------------------------------------------------------------------------*/
  575. /* link an ed into one of the HC chains */
  576. static int ep_link(ohci_t *ohci, ed_t *edi)
  577. {
  578. volatile ed_t *ed = edi;
  579. int int_branch;
  580. int i;
  581. int inter;
  582. int interval;
  583. int load;
  584. __u32 *ed_p;
  585. ed->state = ED_OPER;
  586. ed->int_interval = 0;
  587. switch (ed->type) {
  588. case PIPE_CONTROL:
  589. ed->hwNextED = 0;
  590. flush_dcache_ed(ed);
  591. if (ohci->ed_controltail == NULL)
  592. ohci_writel((uintptr_t)ed, &ohci->regs->ed_controlhead);
  593. else
  594. ohci->ed_controltail->hwNextED =
  595. m32_swap((unsigned long)ed);
  596. ed->ed_prev = ohci->ed_controltail;
  597. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  598. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  599. ohci->hc_control |= OHCI_CTRL_CLE;
  600. ohci_writel(ohci->hc_control, &ohci->regs->control);
  601. }
  602. ohci->ed_controltail = edi;
  603. break;
  604. case PIPE_BULK:
  605. ed->hwNextED = 0;
  606. flush_dcache_ed(ed);
  607. if (ohci->ed_bulktail == NULL)
  608. ohci_writel((uintptr_t)ed, &ohci->regs->ed_bulkhead);
  609. else
  610. ohci->ed_bulktail->hwNextED =
  611. m32_swap((unsigned long)ed);
  612. ed->ed_prev = ohci->ed_bulktail;
  613. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  614. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  615. ohci->hc_control |= OHCI_CTRL_BLE;
  616. ohci_writel(ohci->hc_control, &ohci->regs->control);
  617. }
  618. ohci->ed_bulktail = edi;
  619. break;
  620. case PIPE_INTERRUPT:
  621. load = ed->int_load;
  622. interval = ep_2_n_interval(ed->int_period);
  623. ed->int_interval = interval;
  624. int_branch = ep_int_ballance(ohci, interval, load);
  625. ed->int_branch = int_branch;
  626. for (i = 0; i < ep_rev(6, interval); i += inter) {
  627. inter = 1;
  628. for (ed_p = &(ohci->hcca->int_table[\
  629. ep_rev(5, i) + int_branch]);
  630. (*ed_p != 0) &&
  631. (((ed_t *)ed_p)->int_interval >= interval);
  632. ed_p = &(((ed_t *)ed_p)->hwNextED))
  633. inter = ep_rev(6,
  634. ((ed_t *)ed_p)->int_interval);
  635. ed->hwNextED = *ed_p;
  636. flush_dcache_ed(ed);
  637. *ed_p = m32_swap((unsigned long)ed);
  638. flush_dcache_hcca(ohci->hcca);
  639. }
  640. break;
  641. }
  642. return 0;
  643. }
  644. /*-------------------------------------------------------------------------*/
  645. /* scan the periodic table to find and unlink this ED */
  646. static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed,
  647. unsigned index, unsigned period)
  648. {
  649. __maybe_unused unsigned long aligned_ed_p;
  650. for (; index < NUM_INTS; index += period) {
  651. __u32 *ed_p = &ohci->hcca->int_table [index];
  652. /* ED might have been unlinked through another path */
  653. while (*ed_p != 0) {
  654. if (((struct ed *)(uintptr_t)
  655. m32_swap((unsigned long)ed_p)) == ed) {
  656. *ed_p = ed->hwNextED;
  657. aligned_ed_p = (unsigned long)ed_p;
  658. aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1);
  659. flush_dcache_range(aligned_ed_p,
  660. aligned_ed_p + ARCH_DMA_MINALIGN);
  661. break;
  662. }
  663. ed_p = &(((struct ed *)(uintptr_t)
  664. m32_swap((unsigned long)ed_p))->hwNextED);
  665. }
  666. }
  667. }
  668. /* unlink an ed from one of the HC chains.
  669. * just the link to the ed is unlinked.
  670. * the link from the ed still points to another operational ed or 0
  671. * so the HC can eventually finish the processing of the unlinked ed */
  672. static int ep_unlink(ohci_t *ohci, ed_t *edi)
  673. {
  674. volatile ed_t *ed = edi;
  675. int i;
  676. ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
  677. flush_dcache_ed(ed);
  678. switch (ed->type) {
  679. case PIPE_CONTROL:
  680. if (ed->ed_prev == NULL) {
  681. if (!ed->hwNextED) {
  682. ohci->hc_control &= ~OHCI_CTRL_CLE;
  683. ohci_writel(ohci->hc_control,
  684. &ohci->regs->control);
  685. }
  686. ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
  687. &ohci->regs->ed_controlhead);
  688. } else {
  689. ed->ed_prev->hwNextED = ed->hwNextED;
  690. flush_dcache_ed(ed->ed_prev);
  691. }
  692. if (ohci->ed_controltail == ed) {
  693. ohci->ed_controltail = ed->ed_prev;
  694. } else {
  695. ((ed_t *)(uintptr_t)m32_swap(
  696. *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  697. }
  698. break;
  699. case PIPE_BULK:
  700. if (ed->ed_prev == NULL) {
  701. if (!ed->hwNextED) {
  702. ohci->hc_control &= ~OHCI_CTRL_BLE;
  703. ohci_writel(ohci->hc_control,
  704. &ohci->regs->control);
  705. }
  706. ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
  707. &ohci->regs->ed_bulkhead);
  708. } else {
  709. ed->ed_prev->hwNextED = ed->hwNextED;
  710. flush_dcache_ed(ed->ed_prev);
  711. }
  712. if (ohci->ed_bulktail == ed) {
  713. ohci->ed_bulktail = ed->ed_prev;
  714. } else {
  715. ((ed_t *)(uintptr_t)m32_swap(
  716. *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  717. }
  718. break;
  719. case PIPE_INTERRUPT:
  720. periodic_unlink(ohci, ed, 0, 1);
  721. for (i = ed->int_branch; i < 32; i += ed->int_interval)
  722. ohci->ohci_int_load[i] -= ed->int_load;
  723. break;
  724. }
  725. ed->state = ED_UNLINK;
  726. return 0;
  727. }
  728. /*-------------------------------------------------------------------------*/
  729. /* add/reinit an endpoint; this should be done once at the
  730. * usb_set_configuration command, but the USB stack is a little bit
  731. * stateless so we do it at every transaction if the state of the ed
  732. * is ED_NEW then a dummy td is added and the state is changed to
  733. * ED_UNLINK in all other cases the state is left unchanged the ed
  734. * info fields are setted anyway even though most of them should not
  735. * change
  736. */
  737. static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
  738. unsigned long pipe, int interval, int load)
  739. {
  740. td_t *td;
  741. ed_t *ed_ret;
  742. volatile ed_t *ed;
  743. ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) |
  744. (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))];
  745. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  746. err("ep_add_ed: pending delete");
  747. /* pending delete request */
  748. return NULL;
  749. }
  750. if (ed->state == ED_NEW) {
  751. /* dummy td; end of td list for ed */
  752. td = td_alloc(ohci_dev, usb_dev);
  753. ed->hwTailP = m32_swap((unsigned long)td);
  754. ed->hwHeadP = ed->hwTailP;
  755. ed->state = ED_UNLINK;
  756. ed->type = usb_pipetype(pipe);
  757. ohci_dev->ed_cnt++;
  758. }
  759. ed->hwINFO = m32_swap(usb_pipedevice(pipe)
  760. | usb_pipeendpoint(pipe) << 7
  761. | (usb_pipeisoc(pipe)? 0x8000: 0)
  762. | (usb_pipecontrol(pipe)? 0: \
  763. (usb_pipeout(pipe)? 0x800: 0x1000))
  764. | (usb_dev->speed == USB_SPEED_LOW) << 13
  765. | usb_maxpacket(usb_dev, pipe) << 16);
  766. if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
  767. ed->int_period = interval;
  768. ed->int_load = load;
  769. }
  770. flush_dcache_ed(ed);
  771. return ed_ret;
  772. }
  773. /*-------------------------------------------------------------------------*
  774. * TD handling functions
  775. *-------------------------------------------------------------------------*/
  776. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  777. static void td_fill(ohci_t *ohci, unsigned int info,
  778. void *data, int len,
  779. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  780. {
  781. volatile td_t *td, *td_pt;
  782. #ifdef OHCI_FILL_TRACE
  783. int i;
  784. #endif
  785. if (index > urb_priv->length) {
  786. err("index > length");
  787. return;
  788. }
  789. /* use this td as the next dummy */
  790. td_pt = urb_priv->td [index];
  791. td_pt->hwNextTD = 0;
  792. flush_dcache_td(td_pt);
  793. /* fill the old dummy TD */
  794. td = urb_priv->td [index] =
  795. (td_t *)(uintptr_t)
  796. (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
  797. td->ed = urb_priv->ed;
  798. td->next_dl_td = NULL;
  799. td->index = index;
  800. td->data = (uintptr_t)data;
  801. #ifdef OHCI_FILL_TRACE
  802. if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
  803. for (i = 0; i < len; i++)
  804. printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]);
  805. printf("\n");
  806. }
  807. #endif
  808. if (!len)
  809. data = 0;
  810. td->hwINFO = m32_swap(info);
  811. td->hwCBP = m32_swap((unsigned long)data);
  812. if (data)
  813. td->hwBE = m32_swap((unsigned long)(data + len - 1));
  814. else
  815. td->hwBE = 0;
  816. td->hwNextTD = m32_swap((unsigned long)td_pt);
  817. flush_dcache_td(td);
  818. /* append to queue */
  819. td->ed->hwTailP = td->hwNextTD;
  820. flush_dcache_ed(td->ed);
  821. }
  822. /*-------------------------------------------------------------------------*/
  823. /* prepare all TDs of a transfer */
  824. static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
  825. unsigned long pipe, void *buffer, int transfer_len,
  826. struct devrequest *setup, urb_priv_t *urb,
  827. int interval)
  828. {
  829. int data_len = transfer_len;
  830. void *data;
  831. int cnt = 0;
  832. __u32 info = 0;
  833. unsigned int toggle = 0;
  834. flush_dcache_buffer(buffer, data_len);
  835. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle
  836. * bits for resetting */
  837. if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  838. toggle = TD_T_TOGGLE;
  839. } else {
  840. toggle = TD_T_DATA0;
  841. usb_settoggle(dev, usb_pipeendpoint(pipe),
  842. usb_pipeout(pipe), 1);
  843. }
  844. urb->td_cnt = 0;
  845. if (data_len)
  846. data = buffer;
  847. else
  848. data = 0;
  849. switch (usb_pipetype(pipe)) {
  850. case PIPE_BULK:
  851. info = usb_pipeout(pipe)?
  852. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  853. while (data_len > 4096) {
  854. td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle),
  855. data, 4096, dev, cnt, urb);
  856. data += 4096; data_len -= 4096; cnt++;
  857. }
  858. info = usb_pipeout(pipe)?
  859. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  860. td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data,
  861. data_len, dev, cnt, urb);
  862. cnt++;
  863. if (!ohci->sleeping) {
  864. /* start bulk list */
  865. ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus);
  866. }
  867. break;
  868. case PIPE_CONTROL:
  869. /* Setup phase */
  870. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  871. flush_dcache_buffer(setup, 8);
  872. td_fill(ohci, info, setup, 8, dev, cnt++, urb);
  873. /* Optional Data phase */
  874. if (data_len > 0) {
  875. info = usb_pipeout(pipe)?
  876. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
  877. TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  878. /* NOTE: mishandles transfers >8K, some >4K */
  879. td_fill(ohci, info, data, data_len, dev, cnt++, urb);
  880. }
  881. /* Status phase */
  882. info = (usb_pipeout(pipe) || data_len == 0) ?
  883. TD_CC | TD_DP_IN | TD_T_DATA1:
  884. TD_CC | TD_DP_OUT | TD_T_DATA1;
  885. td_fill(ohci, info, data, 0, dev, cnt++, urb);
  886. if (!ohci->sleeping) {
  887. /* start Control list */
  888. ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus);
  889. }
  890. break;
  891. case PIPE_INTERRUPT:
  892. info = usb_pipeout(urb->pipe)?
  893. TD_CC | TD_DP_OUT | toggle:
  894. TD_CC | TD_R | TD_DP_IN | toggle;
  895. td_fill(ohci, info, data, data_len, dev, cnt++, urb);
  896. break;
  897. }
  898. if (urb->length != cnt)
  899. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  900. }
  901. /*-------------------------------------------------------------------------*
  902. * Done List handling functions
  903. *-------------------------------------------------------------------------*/
  904. /* calculate the transfer length and update the urb */
  905. static void dl_transfer_length(td_t *td)
  906. {
  907. __u32 tdBE, tdCBP;
  908. urb_priv_t *lurb_priv = td->ed->purb;
  909. tdBE = m32_swap(td->hwBE);
  910. tdCBP = m32_swap(td->hwCBP);
  911. if (!(usb_pipecontrol(lurb_priv->pipe) &&
  912. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  913. if (tdBE != 0) {
  914. if (td->hwCBP == 0)
  915. lurb_priv->actual_length += tdBE - td->data + 1;
  916. else
  917. lurb_priv->actual_length += tdCBP - td->data;
  918. }
  919. }
  920. }
  921. /*-------------------------------------------------------------------------*/
  922. static void check_status(td_t *td_list)
  923. {
  924. urb_priv_t *lurb_priv = td_list->ed->purb;
  925. int urb_len = lurb_priv->length;
  926. __u32 *phwHeadP = &td_list->ed->hwHeadP;
  927. int cc;
  928. cc = TD_CC_GET(m32_swap(td_list->hwINFO));
  929. if (cc) {
  930. err(" USB-error: %s (%x)", cc_to_string[cc], cc);
  931. invalidate_dcache_ed(td_list->ed);
  932. if (*phwHeadP & m32_swap(0x1)) {
  933. if (lurb_priv &&
  934. ((td_list->index + 1) < urb_len)) {
  935. *phwHeadP =
  936. (lurb_priv->td[urb_len - 1]->hwNextTD &\
  937. m32_swap(0xfffffff0)) |
  938. (*phwHeadP & m32_swap(0x2));
  939. lurb_priv->td_cnt += urb_len -
  940. td_list->index - 1;
  941. } else
  942. *phwHeadP &= m32_swap(0xfffffff2);
  943. flush_dcache_ed(td_list->ed);
  944. }
  945. }
  946. }
  947. /* replies to the request have to be on a FIFO basis so
  948. * we reverse the reversed done-list */
  949. static td_t *dl_reverse_done_list(ohci_t *ohci)
  950. {
  951. uintptr_t td_list_hc;
  952. td_t *td_rev = NULL;
  953. td_t *td_list = NULL;
  954. invalidate_dcache_hcca(ohci->hcca);
  955. td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
  956. ohci->hcca->done_head = 0;
  957. flush_dcache_hcca(ohci->hcca);
  958. while (td_list_hc) {
  959. td_list = (td_t *)td_list_hc;
  960. invalidate_dcache_td(td_list);
  961. check_status(td_list);
  962. td_list->next_dl_td = td_rev;
  963. td_rev = td_list;
  964. td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
  965. }
  966. return td_list;
  967. }
  968. /*-------------------------------------------------------------------------*/
  969. /*-------------------------------------------------------------------------*/
  970. static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status)
  971. {
  972. if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL))
  973. urb->finished = 1;
  974. else
  975. dbg("finish_urb: strange.., ED state %x, \n", status);
  976. }
  977. /*
  978. * Used to take back a TD from the host controller. This would normally be
  979. * called from within dl_done_list, however it may be called directly if the
  980. * HC no longer sees the TD and it has not appeared on the donelist (after
  981. * two frames). This bug has been observed on ZF Micro systems.
  982. */
  983. static int takeback_td(ohci_t *ohci, td_t *td_list)
  984. {
  985. ed_t *ed;
  986. int cc;
  987. int stat = 0;
  988. /* urb_t *urb; */
  989. urb_priv_t *lurb_priv;
  990. __u32 tdINFO, edHeadP, edTailP;
  991. invalidate_dcache_td(td_list);
  992. tdINFO = m32_swap(td_list->hwINFO);
  993. ed = td_list->ed;
  994. lurb_priv = ed->purb;
  995. dl_transfer_length(td_list);
  996. lurb_priv->td_cnt++;
  997. /* error code of transfer */
  998. cc = TD_CC_GET(tdINFO);
  999. if (cc) {
  1000. err("USB-error: %s (%x)", cc_to_string[cc], cc);
  1001. stat = cc_to_error[cc];
  1002. }
  1003. /* see if this done list makes for all TD's of current URB,
  1004. * and mark the URB finished if so */
  1005. if (lurb_priv->td_cnt == lurb_priv->length)
  1006. finish_urb(ohci, lurb_priv, ed->state);
  1007. dbg("dl_done_list: processing TD %x, len %x\n",
  1008. lurb_priv->td_cnt, lurb_priv->length);
  1009. if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) {
  1010. invalidate_dcache_ed(ed);
  1011. edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
  1012. edTailP = m32_swap(ed->hwTailP);
  1013. /* unlink eds if they are not busy */
  1014. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  1015. ep_unlink(ohci, ed);
  1016. }
  1017. return stat;
  1018. }
  1019. static int dl_done_list(ohci_t *ohci)
  1020. {
  1021. int stat = 0;
  1022. td_t *td_list = dl_reverse_done_list(ohci);
  1023. while (td_list) {
  1024. td_t *td_next = td_list->next_dl_td;
  1025. stat = takeback_td(ohci, td_list);
  1026. td_list = td_next;
  1027. }
  1028. return stat;
  1029. }
  1030. /*-------------------------------------------------------------------------*
  1031. * Virtual Root Hub
  1032. *-------------------------------------------------------------------------*/
  1033. #include <usbroothubdes.h>
  1034. /* Hub class-specific descriptor is constructed dynamically */
  1035. /*-------------------------------------------------------------------------*/
  1036. #define OK(x) len = (x); break
  1037. #ifdef DEBUG
  1038. #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \
  1039. &ohci->regs->roothub.status); }
  1040. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \
  1041. (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); }
  1042. #else
  1043. #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status)
  1044. #define WR_RH_PORTSTAT(x) ohci_writel((x), \
  1045. &ohci->regs->roothub.portstatus[wIndex-1])
  1046. #endif
  1047. #define RD_RH_STAT roothub_status(ohci)
  1048. #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1)
  1049. /* request to virtual root hub */
  1050. int rh_check_port_status(ohci_t *controller)
  1051. {
  1052. __u32 temp, ndp, i;
  1053. int res;
  1054. res = -1;
  1055. temp = roothub_a(controller);
  1056. ndp = (temp & RH_A_NDP);
  1057. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  1058. ndp = (ndp == 2) ? 1:0;
  1059. #endif
  1060. for (i = 0; i < ndp; i++) {
  1061. temp = roothub_portstatus(controller, i);
  1062. /* check for a device disconnect */
  1063. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  1064. (RH_PS_PESC | RH_PS_CSC)) &&
  1065. ((temp & RH_PS_CCS) == 0)) {
  1066. res = i;
  1067. break;
  1068. }
  1069. }
  1070. return res;
  1071. }
  1072. static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev,
  1073. unsigned long pipe, void *buffer, int transfer_len,
  1074. struct devrequest *cmd)
  1075. {
  1076. void *data = buffer;
  1077. int leni = transfer_len;
  1078. int len = 0;
  1079. int stat = 0;
  1080. __u16 bmRType_bReq;
  1081. __u16 wValue;
  1082. __u16 wIndex;
  1083. __u16 wLength;
  1084. ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32));
  1085. #ifdef DEBUG
  1086. pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
  1087. cmd, "SUB(rh)", usb_pipein(pipe));
  1088. #else
  1089. ohci_mdelay(1);
  1090. #endif
  1091. if (usb_pipeint(pipe)) {
  1092. info("Root-Hub submit IRQ: NOT implemented");
  1093. return 0;
  1094. }
  1095. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  1096. wValue = le16_to_cpu(cmd->value);
  1097. wIndex = le16_to_cpu(cmd->index);
  1098. wLength = le16_to_cpu(cmd->length);
  1099. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  1100. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  1101. switch (bmRType_bReq) {
  1102. /* Request Destination:
  1103. without flags: Device,
  1104. RH_INTERFACE: interface,
  1105. RH_ENDPOINT: endpoint,
  1106. RH_CLASS means HUB here,
  1107. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  1108. */
  1109. case RH_GET_STATUS:
  1110. *(u16 *)databuf = cpu_to_le16(1);
  1111. OK(2);
  1112. case RH_GET_STATUS | RH_INTERFACE:
  1113. *(u16 *)databuf = cpu_to_le16(0);
  1114. OK(2);
  1115. case RH_GET_STATUS | RH_ENDPOINT:
  1116. *(u16 *)databuf = cpu_to_le16(0);
  1117. OK(2);
  1118. case RH_GET_STATUS | RH_CLASS:
  1119. *(u32 *)databuf = cpu_to_le32(
  1120. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  1121. OK(4);
  1122. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  1123. *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT);
  1124. OK(4);
  1125. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  1126. switch (wValue) {
  1127. case (RH_ENDPOINT_STALL):
  1128. OK(0);
  1129. }
  1130. break;
  1131. case RH_CLEAR_FEATURE | RH_CLASS:
  1132. switch (wValue) {
  1133. case RH_C_HUB_LOCAL_POWER:
  1134. OK(0);
  1135. case (RH_C_HUB_OVER_CURRENT):
  1136. WR_RH_STAT(RH_HS_OCIC);
  1137. OK(0);
  1138. }
  1139. break;
  1140. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  1141. switch (wValue) {
  1142. case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0);
  1143. case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0);
  1144. case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0);
  1145. case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0);
  1146. case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0);
  1147. case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0);
  1148. case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0);
  1149. case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0);
  1150. }
  1151. break;
  1152. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  1153. switch (wValue) {
  1154. case (RH_PORT_SUSPEND):
  1155. WR_RH_PORTSTAT(RH_PS_PSS); OK(0);
  1156. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  1157. if (RD_RH_PORTSTAT & RH_PS_CCS)
  1158. WR_RH_PORTSTAT(RH_PS_PRS);
  1159. OK(0);
  1160. case (RH_PORT_POWER):
  1161. WR_RH_PORTSTAT(RH_PS_PPS);
  1162. OK(0);
  1163. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  1164. if (RD_RH_PORTSTAT & RH_PS_CCS)
  1165. WR_RH_PORTSTAT(RH_PS_PES);
  1166. OK(0);
  1167. }
  1168. break;
  1169. case RH_SET_ADDRESS:
  1170. ohci->rh.devnum = wValue;
  1171. OK(0);
  1172. case RH_GET_DESCRIPTOR:
  1173. switch ((wValue & 0xff00) >> 8) {
  1174. case (0x01): /* device descriptor */
  1175. len = min_t(unsigned int,
  1176. leni,
  1177. min_t(unsigned int,
  1178. sizeof(root_hub_dev_des),
  1179. wLength));
  1180. databuf = root_hub_dev_des; OK(len);
  1181. case (0x02): /* configuration descriptor */
  1182. len = min_t(unsigned int,
  1183. leni,
  1184. min_t(unsigned int,
  1185. sizeof(root_hub_config_des),
  1186. wLength));
  1187. databuf = root_hub_config_des; OK(len);
  1188. case (0x03): /* string descriptors */
  1189. if (wValue == 0x0300) {
  1190. len = min_t(unsigned int,
  1191. leni,
  1192. min_t(unsigned int,
  1193. sizeof(root_hub_str_index0),
  1194. wLength));
  1195. databuf = root_hub_str_index0;
  1196. OK(len);
  1197. }
  1198. if (wValue == 0x0301) {
  1199. len = min_t(unsigned int,
  1200. leni,
  1201. min_t(unsigned int,
  1202. sizeof(root_hub_str_index1),
  1203. wLength));
  1204. databuf = root_hub_str_index1;
  1205. OK(len);
  1206. }
  1207. default:
  1208. stat = USB_ST_STALLED;
  1209. }
  1210. break;
  1211. case RH_GET_DESCRIPTOR | RH_CLASS:
  1212. {
  1213. __u32 temp = roothub_a(ohci);
  1214. databuf[0] = 9; /* min length; */
  1215. databuf[1] = 0x29;
  1216. databuf[2] = temp & RH_A_NDP;
  1217. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  1218. databuf[2] = (databuf[2] == 2) ? 1 : 0;
  1219. #endif
  1220. databuf[3] = 0;
  1221. if (temp & RH_A_PSM) /* per-port power switching? */
  1222. databuf[3] |= 0x1;
  1223. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  1224. databuf[3] |= 0x10;
  1225. else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */
  1226. databuf[3] |= 0x8;
  1227. databuf[4] = 0;
  1228. databuf[5] = (temp & RH_A_POTPGT) >> 24;
  1229. databuf[6] = 0;
  1230. temp = roothub_b(ohci);
  1231. databuf[7] = temp & RH_B_DR;
  1232. if (databuf[2] < 7) {
  1233. databuf[8] = 0xff;
  1234. } else {
  1235. databuf[0] += 2;
  1236. databuf[8] = (temp & RH_B_DR) >> 8;
  1237. databuf[10] = databuf[9] = 0xff;
  1238. }
  1239. len = min_t(unsigned int, leni,
  1240. min_t(unsigned int, databuf[0], wLength));
  1241. OK(len);
  1242. }
  1243. case RH_GET_CONFIGURATION:
  1244. databuf[0] = 0x01;
  1245. OK(1);
  1246. case RH_SET_CONFIGURATION:
  1247. WR_RH_STAT(0x10000);
  1248. OK(0);
  1249. default:
  1250. dbg("unsupported root hub command");
  1251. stat = USB_ST_STALLED;
  1252. }
  1253. #ifdef DEBUG
  1254. ohci_dump_roothub(ohci, 1);
  1255. #else
  1256. ohci_mdelay(1);
  1257. #endif
  1258. len = min_t(int, len, leni);
  1259. if (data != databuf)
  1260. memcpy(data, databuf, len);
  1261. dev->act_len = len;
  1262. dev->status = stat;
  1263. #ifdef DEBUG
  1264. pkt_print(ohci, NULL, dev, pipe, buffer,
  1265. transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1266. #else
  1267. ohci_mdelay(1);
  1268. #endif
  1269. return stat;
  1270. }
  1271. /*-------------------------------------------------------------------------*/
  1272. static ohci_dev_t *ohci_get_ohci_dev(ohci_t *ohci, int devnum, int intr)
  1273. {
  1274. int i;
  1275. if (!intr)
  1276. return &ohci->ohci_dev;
  1277. /* First see if we already have an ohci_dev for this dev. */
  1278. for (i = 0; i < NUM_INT_DEVS; i++) {
  1279. if (ohci->int_dev[i].devnum == devnum)
  1280. return &ohci->int_dev[i];
  1281. }
  1282. /* If not then find a free one. */
  1283. for (i = 0; i < NUM_INT_DEVS; i++) {
  1284. if (ohci->int_dev[i].devnum == -1) {
  1285. ohci->int_dev[i].devnum = devnum;
  1286. return &ohci->int_dev[i];
  1287. }
  1288. }
  1289. printf("ohci: Error out of ohci_devs for interrupt endpoints\n");
  1290. return NULL;
  1291. }
  1292. /* common code for handling submit messages - used for all but root hub */
  1293. /* accesses. */
  1294. static urb_priv_t *ohci_alloc_urb(struct usb_device *dev, unsigned long pipe,
  1295. void *buffer, int transfer_len, int interval)
  1296. {
  1297. urb_priv_t *urb;
  1298. urb = calloc(1, sizeof(urb_priv_t));
  1299. if (!urb) {
  1300. printf("ohci: Error out of memory allocating urb\n");
  1301. return NULL;
  1302. }
  1303. urb->dev = dev;
  1304. urb->pipe = pipe;
  1305. urb->transfer_buffer = buffer;
  1306. urb->transfer_buffer_length = transfer_len;
  1307. urb->interval = interval;
  1308. return urb;
  1309. }
  1310. static int submit_common_msg(ohci_t *ohci, struct usb_device *dev,
  1311. unsigned long pipe, void *buffer, int transfer_len,
  1312. struct devrequest *setup, int interval)
  1313. {
  1314. int stat = 0;
  1315. int maxsize = usb_maxpacket(dev, pipe);
  1316. int timeout;
  1317. urb_priv_t *urb;
  1318. ohci_dev_t *ohci_dev;
  1319. urb = ohci_alloc_urb(dev, pipe, buffer, transfer_len, interval);
  1320. if (!urb)
  1321. return -ENOMEM;
  1322. #ifdef DEBUG
  1323. urb->actual_length = 0;
  1324. pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
  1325. setup, "SUB", usb_pipein(pipe));
  1326. #else
  1327. ohci_mdelay(1);
  1328. #endif
  1329. if (!maxsize) {
  1330. err("submit_common_message: pipesize for pipe %lx is zero",
  1331. pipe);
  1332. return -1;
  1333. }
  1334. ohci_dev = ohci_get_ohci_dev(ohci, dev->devnum, usb_pipeint(pipe));
  1335. if (!ohci_dev)
  1336. return -ENOMEM;
  1337. if (sohci_submit_job(ohci, ohci_dev, urb, setup) < 0) {
  1338. err("sohci_submit_job failed");
  1339. return -1;
  1340. }
  1341. #if 0
  1342. mdelay(10);
  1343. /* ohci_dump_status(ohci); */
  1344. #endif
  1345. timeout = USB_TIMEOUT_MS(pipe);
  1346. /* wait for it to complete */
  1347. for (;;) {
  1348. /* check whether the controller is done */
  1349. stat = hc_interrupt(ohci);
  1350. if (stat < 0) {
  1351. stat = USB_ST_CRC_ERR;
  1352. break;
  1353. }
  1354. /* NOTE: since we are not interrupt driven in U-Boot and always
  1355. * handle only one URB at a time, we cannot assume the
  1356. * transaction finished on the first successful return from
  1357. * hc_interrupt().. unless the flag for current URB is set,
  1358. * meaning that all TD's to/from device got actually
  1359. * transferred and processed. If the current URB is not
  1360. * finished we need to re-iterate this loop so as
  1361. * hc_interrupt() gets called again as there needs to be some
  1362. * more TD's to process still */
  1363. if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
  1364. /* 0xff is returned for an SF-interrupt */
  1365. break;
  1366. }
  1367. if (--timeout) {
  1368. mdelay(1);
  1369. if (!urb->finished)
  1370. dbg("*");
  1371. } else {
  1372. if (!usb_pipeint(pipe))
  1373. err("CTL:TIMEOUT ");
  1374. dbg("submit_common_msg: TO status %x\n", stat);
  1375. urb->finished = 1;
  1376. stat = USB_ST_CRC_ERR;
  1377. break;
  1378. }
  1379. }
  1380. dev->status = stat;
  1381. dev->act_len = urb->actual_length;
  1382. if (usb_pipein(pipe) && dev->status == 0 && dev->act_len)
  1383. invalidate_dcache_buffer(buffer, dev->act_len);
  1384. #ifdef DEBUG
  1385. pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
  1386. setup, "RET(ctlr)", usb_pipein(pipe));
  1387. #else
  1388. ohci_mdelay(1);
  1389. #endif
  1390. urb_free_priv(urb);
  1391. return 0;
  1392. }
  1393. #define MAX_INT_QUEUESIZE 8
  1394. struct int_queue {
  1395. int queuesize;
  1396. int curr_urb;
  1397. urb_priv_t *urb[MAX_INT_QUEUESIZE];
  1398. };
  1399. static struct int_queue *_ohci_create_int_queue(ohci_t *ohci,
  1400. struct usb_device *udev, unsigned long pipe, int queuesize,
  1401. int elementsize, void *buffer, int interval)
  1402. {
  1403. struct int_queue *queue;
  1404. ohci_dev_t *ohci_dev;
  1405. int i;
  1406. if (queuesize > MAX_INT_QUEUESIZE)
  1407. return NULL;
  1408. ohci_dev = ohci_get_ohci_dev(ohci, udev->devnum, 1);
  1409. if (!ohci_dev)
  1410. return NULL;
  1411. queue = malloc(sizeof(*queue));
  1412. if (!queue) {
  1413. printf("ohci: Error out of memory allocating int queue\n");
  1414. return NULL;
  1415. }
  1416. for (i = 0; i < queuesize; i++) {
  1417. queue->urb[i] = ohci_alloc_urb(udev, pipe,
  1418. buffer + i * elementsize,
  1419. elementsize, interval);
  1420. if (!queue->urb[i])
  1421. break;
  1422. if (sohci_submit_job(ohci, ohci_dev, queue->urb[i], NULL)) {
  1423. printf("ohci: Error submitting int queue job\n");
  1424. urb_free_priv(queue->urb[i]);
  1425. break;
  1426. }
  1427. }
  1428. if (i == 0) {
  1429. /* We did not succeed in submitting even 1 urb */
  1430. free(queue);
  1431. return NULL;
  1432. }
  1433. queue->queuesize = i;
  1434. queue->curr_urb = 0;
  1435. return queue;
  1436. }
  1437. static void *_ohci_poll_int_queue(ohci_t *ohci, struct usb_device *udev,
  1438. struct int_queue *queue)
  1439. {
  1440. if (queue->curr_urb == queue->queuesize)
  1441. return NULL; /* Queue depleted */
  1442. if (hc_interrupt(ohci) < 0)
  1443. return NULL;
  1444. if (queue->urb[queue->curr_urb]->finished) {
  1445. void *ret = queue->urb[queue->curr_urb]->transfer_buffer;
  1446. queue->curr_urb++;
  1447. return ret;
  1448. }
  1449. return NULL;
  1450. }
  1451. static int _ohci_destroy_int_queue(ohci_t *ohci, struct usb_device *dev,
  1452. struct int_queue *queue)
  1453. {
  1454. int i;
  1455. for (i = 0; i < queue->queuesize; i++)
  1456. urb_free_priv(queue->urb[i]);
  1457. free(queue);
  1458. return 0;
  1459. }
  1460. #ifndef CONFIG_DM_USB
  1461. /* submit routines called from usb.c */
  1462. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1463. int transfer_len)
  1464. {
  1465. info("submit_bulk_msg");
  1466. return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len,
  1467. NULL, 0);
  1468. }
  1469. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1470. int transfer_len, int interval)
  1471. {
  1472. info("submit_int_msg");
  1473. return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL,
  1474. interval);
  1475. }
  1476. struct int_queue *create_int_queue(struct usb_device *dev,
  1477. unsigned long pipe, int queuesize, int elementsize,
  1478. void *buffer, int interval)
  1479. {
  1480. return _ohci_create_int_queue(&gohci, dev, pipe, queuesize,
  1481. elementsize, buffer, interval);
  1482. }
  1483. void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
  1484. {
  1485. return _ohci_poll_int_queue(&gohci, dev, queue);
  1486. }
  1487. int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
  1488. {
  1489. return _ohci_destroy_int_queue(&gohci, dev, queue);
  1490. }
  1491. #endif
  1492. static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev,
  1493. unsigned long pipe, void *buffer, int transfer_len,
  1494. struct devrequest *setup)
  1495. {
  1496. int maxsize = usb_maxpacket(dev, pipe);
  1497. info("submit_control_msg");
  1498. #ifdef DEBUG
  1499. pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
  1500. setup, "SUB", usb_pipein(pipe));
  1501. #else
  1502. ohci_mdelay(1);
  1503. #endif
  1504. if (!maxsize) {
  1505. err("submit_control_message: pipesize for pipe %lx is zero",
  1506. pipe);
  1507. return -1;
  1508. }
  1509. if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) {
  1510. ohci->rh.dev = dev;
  1511. /* root hub - redirect */
  1512. return ohci_submit_rh_msg(ohci, dev, pipe, buffer,
  1513. transfer_len, setup);
  1514. }
  1515. return submit_common_msg(ohci, dev, pipe, buffer, transfer_len,
  1516. setup, 0);
  1517. }
  1518. /*-------------------------------------------------------------------------*
  1519. * HC functions
  1520. *-------------------------------------------------------------------------*/
  1521. /* reset the HC and BUS */
  1522. static int hc_reset(ohci_t *ohci)
  1523. {
  1524. #ifdef CONFIG_PCI_EHCI_DEVNO
  1525. pci_dev_t pdev;
  1526. #endif
  1527. int timeout = 30;
  1528. int smm_timeout = 50; /* 0,5 sec */
  1529. dbg("%s\n", __FUNCTION__);
  1530. #ifdef CONFIG_PCI_EHCI_DEVNO
  1531. /*
  1532. * Some multi-function controllers (e.g. ISP1562) allow root hub
  1533. * resetting via EHCI registers only.
  1534. */
  1535. pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
  1536. if (pdev != -1) {
  1537. u32 base;
  1538. int timeout = 1000;
  1539. pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
  1540. base += EHCI_USBCMD_OFF;
  1541. ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base);
  1542. while (ohci_readl(base) & EHCI_USBCMD_HCRESET) {
  1543. if (timeout-- <= 0) {
  1544. printf("USB RootHub reset timed out!");
  1545. break;
  1546. }
  1547. udelay(1);
  1548. }
  1549. } else
  1550. printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
  1551. #endif
  1552. if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
  1553. /* SMM owns the HC, request ownership */
  1554. ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus);
  1555. info("USB HC TakeOver from SMM");
  1556. while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
  1557. mdelay(10);
  1558. if (--smm_timeout == 0) {
  1559. err("USB HC TakeOver failed!");
  1560. return -1;
  1561. }
  1562. }
  1563. }
  1564. /* Disable HC interrupts */
  1565. ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1566. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
  1567. ohci->slot_name,
  1568. ohci_readl(&ohci->regs->control));
  1569. /* Reset USB (needed by some controllers) */
  1570. ohci->hc_control = 0;
  1571. ohci_writel(ohci->hc_control, &ohci->regs->control);
  1572. /* HC Reset requires max 10 us delay */
  1573. ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus);
  1574. while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1575. if (--timeout == 0) {
  1576. err("USB HC reset timed out!");
  1577. return -1;
  1578. }
  1579. udelay(1);
  1580. }
  1581. return 0;
  1582. }
  1583. /*-------------------------------------------------------------------------*/
  1584. /* Start an OHCI controller, set the BUS operational
  1585. * enable interrupts
  1586. * connect the virtual root hub */
  1587. static int hc_start(ohci_t *ohci)
  1588. {
  1589. __u32 mask;
  1590. unsigned int fminterval;
  1591. int i;
  1592. ohci->disabled = 1;
  1593. for (i = 0; i < NUM_INT_DEVS; i++)
  1594. ohci->int_dev[i].devnum = -1;
  1595. /* Tell the controller where the control and bulk lists are
  1596. * The lists are empty now. */
  1597. ohci_writel(0, &ohci->regs->ed_controlhead);
  1598. ohci_writel(0, &ohci->regs->ed_bulkhead);
  1599. ohci_writel((uintptr_t)ohci->hcca,
  1600. &ohci->regs->hcca); /* reset clears this */
  1601. fminterval = 0x2edf;
  1602. ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1603. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1604. ohci_writel(fminterval, &ohci->regs->fminterval);
  1605. ohci_writel(0x628, &ohci->regs->lsthresh);
  1606. /* start controller operations */
  1607. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1608. ohci->disabled = 0;
  1609. ohci_writel(ohci->hc_control, &ohci->regs->control);
  1610. /* disable all interrupts */
  1611. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1612. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1613. OHCI_INTR_OC | OHCI_INTR_MIE);
  1614. ohci_writel(mask, &ohci->regs->intrdisable);
  1615. /* clear all interrupts */
  1616. mask &= ~OHCI_INTR_MIE;
  1617. ohci_writel(mask, &ohci->regs->intrstatus);
  1618. /* Choose the interrupts we care about now - but w/o MIE */
  1619. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1620. ohci_writel(mask, &ohci->regs->intrenable);
  1621. #ifdef OHCI_USE_NPS
  1622. /* required for AMD-756 and some Mac platforms */
  1623. ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
  1624. &ohci->regs->roothub.a);
  1625. ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status);
  1626. #endif /* OHCI_USE_NPS */
  1627. /* connect the virtual root hub */
  1628. ohci->rh.devnum = 0;
  1629. return 0;
  1630. }
  1631. /*-------------------------------------------------------------------------*/
  1632. /* an interrupt happens */
  1633. static int hc_interrupt(ohci_t *ohci)
  1634. {
  1635. struct ohci_regs *regs = ohci->regs;
  1636. int ints;
  1637. int stat = -1;
  1638. invalidate_dcache_hcca(ohci->hcca);
  1639. if ((ohci->hcca->done_head != 0) &&
  1640. !(m32_swap(ohci->hcca->done_head) & 0x01)) {
  1641. ints = OHCI_INTR_WDH;
  1642. } else {
  1643. ints = ohci_readl(&regs->intrstatus);
  1644. if (ints == ~(u32)0) {
  1645. ohci->disabled++;
  1646. err("%s device removed!", ohci->slot_name);
  1647. return -1;
  1648. } else {
  1649. ints &= ohci_readl(&regs->intrenable);
  1650. if (ints == 0) {
  1651. dbg("hc_interrupt: returning..\n");
  1652. return 0xff;
  1653. }
  1654. }
  1655. }
  1656. /* dbg("Interrupt: %x frame: %x", ints,
  1657. le16_to_cpu(ohci->hcca->frame_no)); */
  1658. if (ints & OHCI_INTR_RHSC)
  1659. stat = 0xff;
  1660. if (ints & OHCI_INTR_UE) {
  1661. ohci->disabled++;
  1662. err("OHCI Unrecoverable Error, controller usb-%s disabled",
  1663. ohci->slot_name);
  1664. /* e.g. due to PCI Master/Target Abort */
  1665. #ifdef DEBUG
  1666. ohci_dump(ohci, 1);
  1667. #else
  1668. ohci_mdelay(1);
  1669. #endif
  1670. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1671. /* Make some non-interrupt context restart the controller. */
  1672. /* Count and limit the retries though; either hardware or */
  1673. /* software errors can go forever... */
  1674. hc_reset(ohci);
  1675. return -1;
  1676. }
  1677. if (ints & OHCI_INTR_WDH) {
  1678. ohci_mdelay(1);
  1679. ohci_writel(OHCI_INTR_WDH, &regs->intrdisable);
  1680. (void)ohci_readl(&regs->intrdisable); /* flush */
  1681. stat = dl_done_list(ohci);
  1682. ohci_writel(OHCI_INTR_WDH, &regs->intrenable);
  1683. (void)ohci_readl(&regs->intrdisable); /* flush */
  1684. }
  1685. if (ints & OHCI_INTR_SO) {
  1686. dbg("USB Schedule overrun\n");
  1687. ohci_writel(OHCI_INTR_SO, &regs->intrenable);
  1688. stat = -1;
  1689. }
  1690. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1691. if (ints & OHCI_INTR_SF) {
  1692. unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
  1693. mdelay(1);
  1694. ohci_writel(OHCI_INTR_SF, &regs->intrdisable);
  1695. if (ohci->ed_rm_list[frame] != NULL)
  1696. ohci_writel(OHCI_INTR_SF, &regs->intrenable);
  1697. stat = 0xff;
  1698. }
  1699. ohci_writel(ints, &regs->intrstatus);
  1700. return stat;
  1701. }
  1702. /*-------------------------------------------------------------------------*/
  1703. #ifndef CONFIG_DM_USB
  1704. /*-------------------------------------------------------------------------*/
  1705. /* De-allocate all resources.. */
  1706. static void hc_release_ohci(ohci_t *ohci)
  1707. {
  1708. dbg("USB HC release ohci usb-%s", ohci->slot_name);
  1709. if (!ohci->disabled)
  1710. hc_reset(ohci);
  1711. }
  1712. /*-------------------------------------------------------------------------*/
  1713. /*
  1714. * low level initalisation routine, called from usb.c
  1715. */
  1716. static char ohci_inited = 0;
  1717. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1718. {
  1719. #ifdef CONFIG_PCI_OHCI
  1720. pci_dev_t pdev;
  1721. #endif
  1722. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1723. /* cpu dependant init */
  1724. if (usb_cpu_init())
  1725. return -1;
  1726. #endif
  1727. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1728. /* board dependant init */
  1729. if (board_usb_init(index, USB_INIT_HOST))
  1730. return -1;
  1731. #endif
  1732. memset(&gohci, 0, sizeof(ohci_t));
  1733. /* align the storage */
  1734. if ((__u32)&ghcca[0] & 0xff) {
  1735. err("HCCA not aligned!!");
  1736. return -1;
  1737. }
  1738. gohci.hcca = &ghcca[0];
  1739. info("aligned ghcca %p", gohci.hcca);
  1740. memset(gohci.hcca, 0, sizeof(struct ohci_hcca));
  1741. gohci.disabled = 1;
  1742. gohci.sleeping = 0;
  1743. gohci.irq = -1;
  1744. #ifdef CONFIG_PCI_OHCI
  1745. pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
  1746. if (pdev != -1) {
  1747. u16 vid, did;
  1748. u32 base;
  1749. pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
  1750. pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
  1751. printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
  1752. vid, did, (pdev >> 16) & 0xff,
  1753. (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
  1754. pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
  1755. printf("OHCI regs address 0x%08x\n", base);
  1756. gohci.regs = (struct ohci_regs *)base;
  1757. } else
  1758. return -1;
  1759. #else
  1760. gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
  1761. #endif
  1762. gohci.flags = 0;
  1763. gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
  1764. if (hc_reset (&gohci) < 0) {
  1765. hc_release_ohci (&gohci);
  1766. err ("can't reset usb-%s", gohci.slot_name);
  1767. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1768. /* board dependant cleanup */
  1769. board_usb_cleanup(index, USB_INIT_HOST);
  1770. #endif
  1771. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1772. /* cpu dependant cleanup */
  1773. usb_cpu_init_fail();
  1774. #endif
  1775. return -1;
  1776. }
  1777. if (hc_start(&gohci) < 0) {
  1778. err("can't start usb-%s", gohci.slot_name);
  1779. hc_release_ohci(&gohci);
  1780. /* Initialization failed */
  1781. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1782. /* board dependant cleanup */
  1783. usb_board_stop();
  1784. #endif
  1785. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1786. /* cpu dependant cleanup */
  1787. usb_cpu_stop();
  1788. #endif
  1789. return -1;
  1790. }
  1791. #ifdef DEBUG
  1792. ohci_dump(&gohci, 1);
  1793. #else
  1794. ohci_mdelay(1);
  1795. #endif
  1796. ohci_inited = 1;
  1797. return 0;
  1798. }
  1799. int usb_lowlevel_stop(int index)
  1800. {
  1801. /* this gets called really early - before the controller has */
  1802. /* even been initialized! */
  1803. if (!ohci_inited)
  1804. return 0;
  1805. /* TODO release any interrupts, etc. */
  1806. /* call hc_release_ohci() here ? */
  1807. hc_reset(&gohci);
  1808. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1809. /* board dependant cleanup */
  1810. if (usb_board_stop())
  1811. return -1;
  1812. #endif
  1813. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1814. /* cpu dependant cleanup */
  1815. if (usb_cpu_stop())
  1816. return -1;
  1817. #endif
  1818. /* This driver is no longer initialised. It needs a new low-level
  1819. * init (board/cpu) before it can be used again. */
  1820. ohci_inited = 0;
  1821. return 0;
  1822. }
  1823. int submit_control_msg(struct usb_device *dev, unsigned long pipe,
  1824. void *buffer, int transfer_len, struct devrequest *setup)
  1825. {
  1826. return _ohci_submit_control_msg(&gohci, dev, pipe, buffer,
  1827. transfer_len, setup);
  1828. }
  1829. #endif
  1830. #ifdef CONFIG_DM_USB
  1831. static int ohci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
  1832. unsigned long pipe, void *buffer, int length,
  1833. struct devrequest *setup)
  1834. {
  1835. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1836. return _ohci_submit_control_msg(ohci, udev, pipe, buffer,
  1837. length, setup);
  1838. }
  1839. static int ohci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
  1840. unsigned long pipe, void *buffer, int length)
  1841. {
  1842. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1843. return submit_common_msg(ohci, udev, pipe, buffer, length, NULL, 0);
  1844. }
  1845. static int ohci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
  1846. unsigned long pipe, void *buffer, int length,
  1847. int interval)
  1848. {
  1849. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1850. return submit_common_msg(ohci, udev, pipe, buffer, length,
  1851. NULL, interval);
  1852. }
  1853. static struct int_queue *ohci_create_int_queue(struct udevice *dev,
  1854. struct usb_device *udev, unsigned long pipe, int queuesize,
  1855. int elementsize, void *buffer, int interval)
  1856. {
  1857. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1858. return _ohci_create_int_queue(ohci, udev, pipe, queuesize, elementsize,
  1859. buffer, interval);
  1860. }
  1861. static void *ohci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
  1862. struct int_queue *queue)
  1863. {
  1864. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1865. return _ohci_poll_int_queue(ohci, udev, queue);
  1866. }
  1867. static int ohci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
  1868. struct int_queue *queue)
  1869. {
  1870. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1871. return _ohci_destroy_int_queue(ohci, udev, queue);
  1872. }
  1873. int ohci_register(struct udevice *dev, struct ohci_regs *regs)
  1874. {
  1875. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  1876. ohci_t *ohci = dev_get_priv(dev);
  1877. u32 reg;
  1878. priv->desc_before_addr = true;
  1879. ohci->regs = regs;
  1880. ohci->hcca = memalign(256, sizeof(struct ohci_hcca));
  1881. if (!ohci->hcca)
  1882. return -ENOMEM;
  1883. memset(ohci->hcca, 0, sizeof(struct ohci_hcca));
  1884. flush_dcache_hcca(ohci->hcca);
  1885. if (hc_reset(ohci) < 0)
  1886. return -EIO;
  1887. if (hc_start(ohci) < 0)
  1888. return -EIO;
  1889. reg = ohci_readl(&regs->revision);
  1890. printf("USB OHCI %x.%x\n", (reg >> 4) & 0xf, reg & 0xf);
  1891. return 0;
  1892. }
  1893. int ohci_deregister(struct udevice *dev)
  1894. {
  1895. ohci_t *ohci = dev_get_priv(dev);
  1896. if (hc_reset(ohci) < 0)
  1897. return -EIO;
  1898. free(ohci->hcca);
  1899. return 0;
  1900. }
  1901. struct dm_usb_ops ohci_usb_ops = {
  1902. .control = ohci_submit_control_msg,
  1903. .bulk = ohci_submit_bulk_msg,
  1904. .interrupt = ohci_submit_int_msg,
  1905. .create_int_queue = ohci_create_int_queue,
  1906. .poll_int_queue = ohci_poll_int_queue,
  1907. .destroy_int_queue = ohci_destroy_int_queue,
  1908. };
  1909. #endif