fsl-ls208xa-qds.dtsi 2.5 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree file for Freescale LS2080A QDS Board.
  4. *
  5. * Copyright 2016 Freescale Semiconductor, Inc.
  6. * Copyright 2017 NXP
  7. *
  8. * Abhimanyu Saini <abhimanyu.saini@nxp.com>
  9. *
  10. */
  11. &esdhc {
  12. mmc-hs200-1_8v;
  13. status = "okay";
  14. };
  15. &ifc {
  16. status = "okay";
  17. #address-cells = <2>;
  18. #size-cells = <1>;
  19. ranges = <0x0 0x0 0x5 0x80000000 0x08000000
  20. 0x2 0x0 0x5 0x30000000 0x00010000
  21. 0x3 0x0 0x5 0x20000000 0x00010000>;
  22. nor@0,0 {
  23. #address-cells = <1>;
  24. #size-cells = <1>;
  25. compatible = "cfi-flash";
  26. reg = <0x0 0x0 0x8000000>;
  27. bank-width = <2>;
  28. device-width = <1>;
  29. };
  30. nand@2,0 {
  31. compatible = "fsl,ifc-nand";
  32. reg = <0x2 0x0 0x10000>;
  33. };
  34. cpld@3,0 {
  35. reg = <0x3 0x0 0x10000>;
  36. compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
  37. };
  38. };
  39. &i2c0 {
  40. status = "okay";
  41. pca9547@77 {
  42. compatible = "nxp,pca9547";
  43. reg = <0x77>;
  44. #address-cells = <1>;
  45. #size-cells = <0>;
  46. i2c@0 {
  47. #address-cells = <1>;
  48. #size-cells = <0>;
  49. reg = <0x00>;
  50. rtc@68 {
  51. compatible = "dallas,ds3232";
  52. reg = <0x68>;
  53. };
  54. };
  55. i2c@2 {
  56. #address-cells = <1>;
  57. #size-cells = <0>;
  58. reg = <0x02>;
  59. ina220@40 {
  60. compatible = "ti,ina220";
  61. reg = <0x40>;
  62. shunt-resistor = <500>;
  63. };
  64. ina220@41 {
  65. compatible = "ti,ina220";
  66. reg = <0x41>;
  67. shunt-resistor = <1000>;
  68. };
  69. };
  70. i2c@3 {
  71. #address-cells = <1>;
  72. #size-cells = <0>;
  73. reg = <0x3>;
  74. adt7481@4c {
  75. compatible = "adi,adt7461";
  76. reg = <0x4c>;
  77. };
  78. };
  79. };
  80. };
  81. &i2c1 {
  82. status = "disabled";
  83. };
  84. &i2c2 {
  85. status = "disabled";
  86. };
  87. &i2c3 {
  88. status = "disabled";
  89. };
  90. &dspi {
  91. status = "okay";
  92. dflash0: n25q128a@0 {
  93. #address-cells = <1>;
  94. #size-cells = <1>;
  95. compatible = "st,m25p80";
  96. spi-max-frequency = <3000000>;
  97. reg = <0>;
  98. };
  99. dflash1: sst25wf040b@1 {
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. compatible = "st,m25p80";
  103. spi-max-frequency = <3000000>;
  104. reg = <1>;
  105. };
  106. dflash2: en25s64@2 {
  107. #address-cells = <1>;
  108. #size-cells = <1>;
  109. compatible = "st,m25p80";
  110. spi-max-frequency = <3000000>;
  111. reg = <2>;
  112. };
  113. };
  114. &qspi {
  115. status = "okay";
  116. flash0: s25fl256s1@0 {
  117. #address-cells = <1>;
  118. #size-cells = <1>;
  119. compatible = "st,m25p80";
  120. spi-max-frequency = <20000000>;
  121. reg = <0>;
  122. };
  123. flash2: s25fl256s1@2 {
  124. #address-cells = <1>;
  125. #size-cells = <1>;
  126. compatible = "st,m25p80";
  127. spi-max-frequency = <20000000>;
  128. reg = <2>;
  129. };
  130. };
  131. &sata0 {
  132. status = "okay";
  133. };
  134. &sata1 {
  135. status = "okay";
  136. };
  137. &usb0 {
  138. status = "okay";
  139. };
  140. &usb1 {
  141. status = "okay";
  142. };