ohci-tmio.c 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * OHCI HCD(Host Controller Driver) for USB.
  4. *
  5. *(C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  6. *(C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
  7. *(C) Copyright 2002 Hewlett-Packard Company
  8. *
  9. * Bus glue for Toshiba Mobile IO(TMIO) Controller's OHCI core
  10. * (C) Copyright 2005 Chris Humbert <mahadri-usb@drigon.com>
  11. * (C) Copyright 2007, 2008 Dmitry Baryshkov <dbaryshkov@gmail.com>
  12. *
  13. * This is known to work with the following variants:
  14. * TC6393XB revision 3 (32kB SRAM)
  15. *
  16. * The TMIO's OHCI core DMAs through a small internal buffer that
  17. * is directly addressable by the CPU.
  18. *
  19. * Written from sparse documentation from Toshiba and Sharp's driver
  20. * for the 2.4 kernel,
  21. * usb-ohci-tc6393.c(C) Copyright 2004 Lineo Solutions, Inc.
  22. */
  23. /*#include <linux/fs.h>
  24. #include <linux/mount.h>
  25. #include <linux/pagemap.h>
  26. #include <linux/namei.h>
  27. #include <linux/sched.h>*/
  28. #include <linux/platform_device.h>
  29. #include <linux/mfd/core.h>
  30. #include <linux/mfd/tmio.h>
  31. #include <linux/dma-mapping.h>
  32. /*-------------------------------------------------------------------------*/
  33. /*
  34. * USB Host Controller Configuration Register
  35. */
  36. #define CCR_REVID 0x08 /* b Revision ID */
  37. #define CCR_BASE 0x10 /* l USB Control Register Base Address Low */
  38. #define CCR_ILME 0x40 /* b Internal Local Memory Enable */
  39. #define CCR_PM 0x4c /* w Power Management */
  40. #define CCR_INTC 0x50 /* b INT Control */
  41. #define CCR_LMW1L 0x54 /* w Local Memory Window 1 LMADRS Low */
  42. #define CCR_LMW1H 0x56 /* w Local Memory Window 1 LMADRS High */
  43. #define CCR_LMW1BL 0x58 /* w Local Memory Window 1 Base Address Low */
  44. #define CCR_LMW1BH 0x5A /* w Local Memory Window 1 Base Address High */
  45. #define CCR_LMW2L 0x5C /* w Local Memory Window 2 LMADRS Low */
  46. #define CCR_LMW2H 0x5E /* w Local Memory Window 2 LMADRS High */
  47. #define CCR_LMW2BL 0x60 /* w Local Memory Window 2 Base Address Low */
  48. #define CCR_LMW2BH 0x62 /* w Local Memory Window 2 Base Address High */
  49. #define CCR_MISC 0xFC /* b MISC */
  50. #define CCR_PM_GKEN 0x0001
  51. #define CCR_PM_CKRNEN 0x0002
  52. #define CCR_PM_USBPW1 0x0004
  53. #define CCR_PM_USBPW2 0x0008
  54. #define CCR_PM_USBPW3 0x0010
  55. #define CCR_PM_PMEE 0x0100
  56. #define CCR_PM_PMES 0x8000
  57. /*-------------------------------------------------------------------------*/
  58. struct tmio_hcd {
  59. void __iomem *ccr;
  60. spinlock_t lock; /* protects RMW cycles */
  61. };
  62. #define hcd_to_tmio(hcd) ((struct tmio_hcd *)(hcd_to_ohci(hcd) + 1))
  63. /*-------------------------------------------------------------------------*/
  64. static void tmio_write_pm(struct platform_device *dev)
  65. {
  66. struct usb_hcd *hcd = platform_get_drvdata(dev);
  67. struct tmio_hcd *tmio = hcd_to_tmio(hcd);
  68. u16 pm;
  69. unsigned long flags;
  70. spin_lock_irqsave(&tmio->lock, flags);
  71. pm = CCR_PM_GKEN | CCR_PM_CKRNEN |
  72. CCR_PM_PMEE | CCR_PM_PMES;
  73. tmio_iowrite16(pm, tmio->ccr + CCR_PM);
  74. spin_unlock_irqrestore(&tmio->lock, flags);
  75. }
  76. static void tmio_stop_hc(struct platform_device *dev)
  77. {
  78. struct usb_hcd *hcd = platform_get_drvdata(dev);
  79. struct ohci_hcd *ohci = hcd_to_ohci(hcd);
  80. struct tmio_hcd *tmio = hcd_to_tmio(hcd);
  81. u16 pm;
  82. pm = CCR_PM_GKEN | CCR_PM_CKRNEN;
  83. switch (ohci->num_ports) {
  84. default:
  85. dev_err(&dev->dev, "Unsupported amount of ports: %d\n", ohci->num_ports);
  86. case 3:
  87. pm |= CCR_PM_USBPW3;
  88. case 2:
  89. pm |= CCR_PM_USBPW2;
  90. case 1:
  91. pm |= CCR_PM_USBPW1;
  92. }
  93. tmio_iowrite8(0, tmio->ccr + CCR_INTC);
  94. tmio_iowrite8(0, tmio->ccr + CCR_ILME);
  95. tmio_iowrite16(0, tmio->ccr + CCR_BASE);
  96. tmio_iowrite16(0, tmio->ccr + CCR_BASE + 2);
  97. tmio_iowrite16(pm, tmio->ccr + CCR_PM);
  98. }
  99. static void tmio_start_hc(struct platform_device *dev)
  100. {
  101. struct usb_hcd *hcd = platform_get_drvdata(dev);
  102. struct tmio_hcd *tmio = hcd_to_tmio(hcd);
  103. unsigned long base = hcd->rsrc_start;
  104. tmio_write_pm(dev);
  105. tmio_iowrite16(base, tmio->ccr + CCR_BASE);
  106. tmio_iowrite16(base >> 16, tmio->ccr + CCR_BASE + 2);
  107. tmio_iowrite8(1, tmio->ccr + CCR_ILME);
  108. tmio_iowrite8(2, tmio->ccr + CCR_INTC);
  109. dev_info(&dev->dev, "revision %d @ 0x%08llx, irq %d\n",
  110. tmio_ioread8(tmio->ccr + CCR_REVID),
  111. (u64) hcd->rsrc_start, hcd->irq);
  112. }
  113. static int ohci_tmio_start(struct usb_hcd *hcd)
  114. {
  115. struct ohci_hcd *ohci = hcd_to_ohci(hcd);
  116. int ret;
  117. if ((ret = ohci_init(ohci)) < 0)
  118. return ret;
  119. if ((ret = ohci_run(ohci)) < 0) {
  120. dev_err(hcd->self.controller, "can't start %s\n",
  121. hcd->self.bus_name);
  122. ohci_stop(hcd);
  123. return ret;
  124. }
  125. return 0;
  126. }
  127. static const struct hc_driver ohci_tmio_hc_driver = {
  128. .description = hcd_name,
  129. .product_desc = "TMIO OHCI USB Host Controller",
  130. .hcd_priv_size = sizeof(struct ohci_hcd) + sizeof (struct tmio_hcd),
  131. /* generic hardware linkage */
  132. .irq = ohci_irq,
  133. .flags = HCD_USB11 | HCD_MEMORY | HCD_LOCAL_MEM,
  134. /* basic lifecycle operations */
  135. .start = ohci_tmio_start,
  136. .stop = ohci_stop,
  137. .shutdown = ohci_shutdown,
  138. /* managing i/o requests and associated device resources */
  139. .urb_enqueue = ohci_urb_enqueue,
  140. .urb_dequeue = ohci_urb_dequeue,
  141. .endpoint_disable = ohci_endpoint_disable,
  142. /* scheduling support */
  143. .get_frame_number = ohci_get_frame,
  144. /* root hub support */
  145. .hub_status_data = ohci_hub_status_data,
  146. .hub_control = ohci_hub_control,
  147. #ifdef CONFIG_PM
  148. .bus_suspend = ohci_bus_suspend,
  149. .bus_resume = ohci_bus_resume,
  150. #endif
  151. .start_port_reset = ohci_start_port_reset,
  152. };
  153. /*-------------------------------------------------------------------------*/
  154. static struct platform_driver ohci_hcd_tmio_driver;
  155. static int ohci_hcd_tmio_drv_probe(struct platform_device *dev)
  156. {
  157. const struct mfd_cell *cell = mfd_get_cell(dev);
  158. struct resource *regs = platform_get_resource(dev, IORESOURCE_MEM, 0);
  159. struct resource *config = platform_get_resource(dev, IORESOURCE_MEM, 1);
  160. struct resource *sram = platform_get_resource(dev, IORESOURCE_MEM, 2);
  161. int irq = platform_get_irq(dev, 0);
  162. struct tmio_hcd *tmio;
  163. struct ohci_hcd *ohci;
  164. struct usb_hcd *hcd;
  165. int ret;
  166. if (usb_disabled())
  167. return -ENODEV;
  168. if (!cell)
  169. return -EINVAL;
  170. hcd = usb_create_hcd(&ohci_tmio_hc_driver, &dev->dev, dev_name(&dev->dev));
  171. if (!hcd) {
  172. ret = -ENOMEM;
  173. goto err_usb_create_hcd;
  174. }
  175. hcd->rsrc_start = regs->start;
  176. hcd->rsrc_len = resource_size(regs);
  177. tmio = hcd_to_tmio(hcd);
  178. spin_lock_init(&tmio->lock);
  179. tmio->ccr = ioremap(config->start, resource_size(config));
  180. if (!tmio->ccr) {
  181. ret = -ENOMEM;
  182. goto err_ioremap_ccr;
  183. }
  184. hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
  185. if (!hcd->regs) {
  186. ret = -ENOMEM;
  187. goto err_ioremap_regs;
  188. }
  189. ret = dma_declare_coherent_memory(&dev->dev, sram->start, sram->start,
  190. resource_size(sram), DMA_MEMORY_EXCLUSIVE);
  191. if (ret)
  192. goto err_dma_declare;
  193. if (cell->enable) {
  194. ret = cell->enable(dev);
  195. if (ret)
  196. goto err_enable;
  197. }
  198. tmio_start_hc(dev);
  199. ohci = hcd_to_ohci(hcd);
  200. ohci_hcd_init(ohci);
  201. ret = usb_add_hcd(hcd, irq, 0);
  202. if (ret)
  203. goto err_add_hcd;
  204. device_wakeup_enable(hcd->self.controller);
  205. if (ret == 0)
  206. return ret;
  207. usb_remove_hcd(hcd);
  208. err_add_hcd:
  209. tmio_stop_hc(dev);
  210. if (cell->disable)
  211. cell->disable(dev);
  212. err_enable:
  213. dma_release_declared_memory(&dev->dev);
  214. err_dma_declare:
  215. iounmap(hcd->regs);
  216. err_ioremap_regs:
  217. iounmap(tmio->ccr);
  218. err_ioremap_ccr:
  219. usb_put_hcd(hcd);
  220. err_usb_create_hcd:
  221. return ret;
  222. }
  223. static int ohci_hcd_tmio_drv_remove(struct platform_device *dev)
  224. {
  225. struct usb_hcd *hcd = platform_get_drvdata(dev);
  226. struct tmio_hcd *tmio = hcd_to_tmio(hcd);
  227. const struct mfd_cell *cell = mfd_get_cell(dev);
  228. usb_remove_hcd(hcd);
  229. tmio_stop_hc(dev);
  230. if (cell->disable)
  231. cell->disable(dev);
  232. dma_release_declared_memory(&dev->dev);
  233. iounmap(hcd->regs);
  234. iounmap(tmio->ccr);
  235. usb_put_hcd(hcd);
  236. return 0;
  237. }
  238. #ifdef CONFIG_PM
  239. static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t state)
  240. {
  241. const struct mfd_cell *cell = mfd_get_cell(dev);
  242. struct usb_hcd *hcd = platform_get_drvdata(dev);
  243. struct ohci_hcd *ohci = hcd_to_ohci(hcd);
  244. struct tmio_hcd *tmio = hcd_to_tmio(hcd);
  245. unsigned long flags;
  246. u8 misc;
  247. int ret;
  248. if (time_before(jiffies, ohci->next_statechange))
  249. msleep(5);
  250. ohci->next_statechange = jiffies;
  251. spin_lock_irqsave(&tmio->lock, flags);
  252. misc = tmio_ioread8(tmio->ccr + CCR_MISC);
  253. misc |= 1 << 3; /* USSUSP */
  254. tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
  255. spin_unlock_irqrestore(&tmio->lock, flags);
  256. if (cell->suspend) {
  257. ret = cell->suspend(dev);
  258. if (ret)
  259. return ret;
  260. }
  261. return 0;
  262. }
  263. static int ohci_hcd_tmio_drv_resume(struct platform_device *dev)
  264. {
  265. const struct mfd_cell *cell = mfd_get_cell(dev);
  266. struct usb_hcd *hcd = platform_get_drvdata(dev);
  267. struct ohci_hcd *ohci = hcd_to_ohci(hcd);
  268. struct tmio_hcd *tmio = hcd_to_tmio(hcd);
  269. unsigned long flags;
  270. u8 misc;
  271. int ret;
  272. if (time_before(jiffies, ohci->next_statechange))
  273. msleep(5);
  274. ohci->next_statechange = jiffies;
  275. if (cell->resume) {
  276. ret = cell->resume(dev);
  277. if (ret)
  278. return ret;
  279. }
  280. tmio_start_hc(dev);
  281. spin_lock_irqsave(&tmio->lock, flags);
  282. misc = tmio_ioread8(tmio->ccr + CCR_MISC);
  283. misc &= ~(1 << 3); /* USSUSP */
  284. tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
  285. spin_unlock_irqrestore(&tmio->lock, flags);
  286. ohci_resume(hcd, false);
  287. return 0;
  288. }
  289. #else
  290. #define ohci_hcd_tmio_drv_suspend NULL
  291. #define ohci_hcd_tmio_drv_resume NULL
  292. #endif
  293. static struct platform_driver ohci_hcd_tmio_driver = {
  294. .probe = ohci_hcd_tmio_drv_probe,
  295. .remove = ohci_hcd_tmio_drv_remove,
  296. .shutdown = usb_hcd_platform_shutdown,
  297. .suspend = ohci_hcd_tmio_drv_suspend,
  298. .resume = ohci_hcd_tmio_drv_resume,
  299. .driver = {
  300. .name = "tmio-ohci",
  301. },
  302. };