rza.c 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas USB driver RZ/A initialization and power control
  4. *
  5. * Copyright (C) 2018 Chris Brandt
  6. * Copyright (C) 2018 Renesas Electronics Corporation
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/io.h>
  10. #include <linux/of_device.h>
  11. #include "common.h"
  12. #include "rza.h"
  13. static int usbhs_rza1_hardware_init(struct platform_device *pdev)
  14. {
  15. struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
  16. struct device_node *usb_x1_clk, *extal_clk;
  17. u32 freq_usb = 0, freq_extal = 0;
  18. /* Input Clock Selection (NOTE: ch0 controls both ch0 and ch1) */
  19. usb_x1_clk = of_find_node_by_name(NULL, "usb_x1");
  20. extal_clk = of_find_node_by_name(NULL, "extal");
  21. of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb);
  22. of_property_read_u32(extal_clk, "clock-frequency", &freq_extal);
  23. if (freq_usb == 0) {
  24. if (freq_extal == 12000000) {
  25. /* Select 12MHz XTAL */
  26. usbhs_bset(priv, SYSCFG, UCKSEL, UCKSEL);
  27. } else {
  28. dev_err(usbhs_priv_to_dev(priv), "A 48MHz USB clock or 12MHz main clock is required.\n");
  29. return -EIO;
  30. }
  31. }
  32. /* Enable USB PLL (NOTE: ch0 controls both ch0 and ch1) */
  33. usbhs_bset(priv, SYSCFG, UPLLE, UPLLE);
  34. udelay(1000);
  35. usbhs_bset(priv, SUSPMODE, SUSPM, SUSPM);
  36. return 0;
  37. }
  38. static int usbhs_rza_get_id(struct platform_device *pdev)
  39. {
  40. return USBHS_GADGET;
  41. }
  42. const struct renesas_usbhs_platform_callback usbhs_rza1_ops = {
  43. .hardware_init = usbhs_rza1_hardware_init,
  44. .get_id = usbhs_rza_get_id,
  45. };