mxl5007t.c 21 KB

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  1. /*
  2. * mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner
  3. *
  4. * Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/i2c.h>
  17. #include <linux/types.h>
  18. #include <linux/videodev2.h>
  19. #include "tuner-i2c.h"
  20. #include "mxl5007t.h"
  21. static DEFINE_MUTEX(mxl5007t_list_mutex);
  22. static LIST_HEAD(hybrid_tuner_instance_list);
  23. static int mxl5007t_debug;
  24. module_param_named(debug, mxl5007t_debug, int, 0644);
  25. MODULE_PARM_DESC(debug, "set debug level");
  26. /* ------------------------------------------------------------------------- */
  27. #define mxl_printk(kern, fmt, arg...) \
  28. printk(kern "%s: " fmt "\n", __func__, ##arg)
  29. #define mxl_err(fmt, arg...) \
  30. mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg)
  31. #define mxl_warn(fmt, arg...) \
  32. mxl_printk(KERN_WARNING, fmt, ##arg)
  33. #define mxl_info(fmt, arg...) \
  34. mxl_printk(KERN_INFO, fmt, ##arg)
  35. #define mxl_debug(fmt, arg...) \
  36. ({ \
  37. if (mxl5007t_debug) \
  38. mxl_printk(KERN_DEBUG, fmt, ##arg); \
  39. })
  40. #define mxl_fail(ret) \
  41. ({ \
  42. int __ret; \
  43. __ret = (ret < 0); \
  44. if (__ret) \
  45. mxl_printk(KERN_ERR, "error %d on line %d", \
  46. ret, __LINE__); \
  47. __ret; \
  48. })
  49. /* ------------------------------------------------------------------------- */
  50. enum mxl5007t_mode {
  51. MxL_MODE_ISDBT = 0,
  52. MxL_MODE_DVBT = 1,
  53. MxL_MODE_ATSC = 2,
  54. MxL_MODE_CABLE = 0x10,
  55. };
  56. enum mxl5007t_chip_version {
  57. MxL_UNKNOWN_ID = 0x00,
  58. MxL_5007_V1_F1 = 0x11,
  59. MxL_5007_V1_F2 = 0x12,
  60. MxL_5007_V4 = 0x14,
  61. MxL_5007_V2_100_F1 = 0x21,
  62. MxL_5007_V2_100_F2 = 0x22,
  63. MxL_5007_V2_200_F1 = 0x23,
  64. MxL_5007_V2_200_F2 = 0x24,
  65. };
  66. struct reg_pair_t {
  67. u8 reg;
  68. u8 val;
  69. };
  70. /* ------------------------------------------------------------------------- */
  71. static struct reg_pair_t init_tab[] = {
  72. { 0x02, 0x06 },
  73. { 0x03, 0x48 },
  74. { 0x05, 0x04 },
  75. { 0x06, 0x10 },
  76. { 0x2e, 0x15 }, /* OVERRIDE */
  77. { 0x30, 0x10 }, /* OVERRIDE */
  78. { 0x45, 0x58 }, /* OVERRIDE */
  79. { 0x48, 0x19 }, /* OVERRIDE */
  80. { 0x52, 0x03 }, /* OVERRIDE */
  81. { 0x53, 0x44 }, /* OVERRIDE */
  82. { 0x6a, 0x4b }, /* OVERRIDE */
  83. { 0x76, 0x00 }, /* OVERRIDE */
  84. { 0x78, 0x18 }, /* OVERRIDE */
  85. { 0x7a, 0x17 }, /* OVERRIDE */
  86. { 0x85, 0x06 }, /* OVERRIDE */
  87. { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
  88. { 0, 0 }
  89. };
  90. static struct reg_pair_t init_tab_cable[] = {
  91. { 0x02, 0x06 },
  92. { 0x03, 0x48 },
  93. { 0x05, 0x04 },
  94. { 0x06, 0x10 },
  95. { 0x09, 0x3f },
  96. { 0x0a, 0x3f },
  97. { 0x0b, 0x3f },
  98. { 0x2e, 0x15 }, /* OVERRIDE */
  99. { 0x30, 0x10 }, /* OVERRIDE */
  100. { 0x45, 0x58 }, /* OVERRIDE */
  101. { 0x48, 0x19 }, /* OVERRIDE */
  102. { 0x52, 0x03 }, /* OVERRIDE */
  103. { 0x53, 0x44 }, /* OVERRIDE */
  104. { 0x6a, 0x4b }, /* OVERRIDE */
  105. { 0x76, 0x00 }, /* OVERRIDE */
  106. { 0x78, 0x18 }, /* OVERRIDE */
  107. { 0x7a, 0x17 }, /* OVERRIDE */
  108. { 0x85, 0x06 }, /* OVERRIDE */
  109. { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
  110. { 0, 0 }
  111. };
  112. /* ------------------------------------------------------------------------- */
  113. static struct reg_pair_t reg_pair_rftune[] = {
  114. { 0x0f, 0x00 }, /* abort tune */
  115. { 0x0c, 0x15 },
  116. { 0x0d, 0x40 },
  117. { 0x0e, 0x0e },
  118. { 0x1f, 0x87 }, /* OVERRIDE */
  119. { 0x20, 0x1f }, /* OVERRIDE */
  120. { 0x21, 0x87 }, /* OVERRIDE */
  121. { 0x22, 0x1f }, /* OVERRIDE */
  122. { 0x80, 0x01 }, /* freq dependent */
  123. { 0x0f, 0x01 }, /* start tune */
  124. { 0, 0 }
  125. };
  126. /* ------------------------------------------------------------------------- */
  127. struct mxl5007t_state {
  128. struct list_head hybrid_tuner_instance_list;
  129. struct tuner_i2c_props i2c_props;
  130. struct mutex lock;
  131. struct mxl5007t_config *config;
  132. enum mxl5007t_chip_version chip_id;
  133. struct reg_pair_t tab_init[ARRAY_SIZE(init_tab)];
  134. struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)];
  135. struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)];
  136. enum mxl5007t_if_freq if_freq;
  137. u32 frequency;
  138. u32 bandwidth;
  139. };
  140. /* ------------------------------------------------------------------------- */
  141. /* called by _init and _rftun to manipulate the register arrays */
  142. static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val)
  143. {
  144. unsigned int i = 0;
  145. while (reg_pair[i].reg || reg_pair[i].val) {
  146. if (reg_pair[i].reg == reg) {
  147. reg_pair[i].val &= ~mask;
  148. reg_pair[i].val |= val;
  149. }
  150. i++;
  151. }
  152. return;
  153. }
  154. static void copy_reg_bits(struct reg_pair_t *reg_pair1,
  155. struct reg_pair_t *reg_pair2)
  156. {
  157. unsigned int i, j;
  158. i = j = 0;
  159. while (reg_pair1[i].reg || reg_pair1[i].val) {
  160. while (reg_pair2[j].reg || reg_pair2[j].val) {
  161. if (reg_pair1[i].reg != reg_pair2[j].reg) {
  162. j++;
  163. continue;
  164. }
  165. reg_pair2[j].val = reg_pair1[i].val;
  166. break;
  167. }
  168. i++;
  169. }
  170. return;
  171. }
  172. /* ------------------------------------------------------------------------- */
  173. static void mxl5007t_set_mode_bits(struct mxl5007t_state *state,
  174. enum mxl5007t_mode mode,
  175. s32 if_diff_out_level)
  176. {
  177. switch (mode) {
  178. case MxL_MODE_ATSC:
  179. set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12);
  180. break;
  181. case MxL_MODE_DVBT:
  182. set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11);
  183. break;
  184. case MxL_MODE_ISDBT:
  185. set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10);
  186. break;
  187. case MxL_MODE_CABLE:
  188. set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1);
  189. set_reg_bits(state->tab_init_cable, 0x0a, 0xff,
  190. 8 - if_diff_out_level);
  191. set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17);
  192. break;
  193. default:
  194. mxl_fail(-EINVAL);
  195. }
  196. return;
  197. }
  198. static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state,
  199. enum mxl5007t_if_freq if_freq,
  200. int invert_if)
  201. {
  202. u8 val;
  203. switch (if_freq) {
  204. case MxL_IF_4_MHZ:
  205. val = 0x00;
  206. break;
  207. case MxL_IF_4_5_MHZ:
  208. val = 0x02;
  209. break;
  210. case MxL_IF_4_57_MHZ:
  211. val = 0x03;
  212. break;
  213. case MxL_IF_5_MHZ:
  214. val = 0x04;
  215. break;
  216. case MxL_IF_5_38_MHZ:
  217. val = 0x05;
  218. break;
  219. case MxL_IF_6_MHZ:
  220. val = 0x06;
  221. break;
  222. case MxL_IF_6_28_MHZ:
  223. val = 0x07;
  224. break;
  225. case MxL_IF_9_1915_MHZ:
  226. val = 0x08;
  227. break;
  228. case MxL_IF_35_25_MHZ:
  229. val = 0x09;
  230. break;
  231. case MxL_IF_36_15_MHZ:
  232. val = 0x0a;
  233. break;
  234. case MxL_IF_44_MHZ:
  235. val = 0x0b;
  236. break;
  237. default:
  238. mxl_fail(-EINVAL);
  239. return;
  240. }
  241. set_reg_bits(state->tab_init, 0x02, 0x0f, val);
  242. /* set inverted IF or normal IF */
  243. set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00);
  244. state->if_freq = if_freq;
  245. return;
  246. }
  247. static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state,
  248. enum mxl5007t_xtal_freq xtal_freq)
  249. {
  250. switch (xtal_freq) {
  251. case MxL_XTAL_16_MHZ:
  252. /* select xtal freq & ref freq */
  253. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00);
  254. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00);
  255. break;
  256. case MxL_XTAL_20_MHZ:
  257. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10);
  258. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01);
  259. break;
  260. case MxL_XTAL_20_25_MHZ:
  261. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20);
  262. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02);
  263. break;
  264. case MxL_XTAL_20_48_MHZ:
  265. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30);
  266. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03);
  267. break;
  268. case MxL_XTAL_24_MHZ:
  269. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40);
  270. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04);
  271. break;
  272. case MxL_XTAL_25_MHZ:
  273. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50);
  274. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05);
  275. break;
  276. case MxL_XTAL_25_14_MHZ:
  277. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60);
  278. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06);
  279. break;
  280. case MxL_XTAL_27_MHZ:
  281. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70);
  282. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07);
  283. break;
  284. case MxL_XTAL_28_8_MHZ:
  285. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80);
  286. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08);
  287. break;
  288. case MxL_XTAL_32_MHZ:
  289. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90);
  290. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09);
  291. break;
  292. case MxL_XTAL_40_MHZ:
  293. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0);
  294. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a);
  295. break;
  296. case MxL_XTAL_44_MHZ:
  297. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0);
  298. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b);
  299. break;
  300. case MxL_XTAL_48_MHZ:
  301. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0);
  302. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c);
  303. break;
  304. case MxL_XTAL_49_3811_MHZ:
  305. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0);
  306. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d);
  307. break;
  308. default:
  309. mxl_fail(-EINVAL);
  310. return;
  311. }
  312. return;
  313. }
  314. static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state,
  315. enum mxl5007t_mode mode)
  316. {
  317. struct mxl5007t_config *cfg = state->config;
  318. memcpy(&state->tab_init, &init_tab, sizeof(init_tab));
  319. memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable));
  320. mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level);
  321. mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if);
  322. mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz);
  323. set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3);
  324. set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp);
  325. if (mode >= MxL_MODE_CABLE) {
  326. copy_reg_bits(state->tab_init, state->tab_init_cable);
  327. return state->tab_init_cable;
  328. } else
  329. return state->tab_init;
  330. }
  331. /* ------------------------------------------------------------------------- */
  332. enum mxl5007t_bw_mhz {
  333. MxL_BW_6MHz = 6,
  334. MxL_BW_7MHz = 7,
  335. MxL_BW_8MHz = 8,
  336. };
  337. static void mxl5007t_set_bw_bits(struct mxl5007t_state *state,
  338. enum mxl5007t_bw_mhz bw)
  339. {
  340. u8 val;
  341. switch (bw) {
  342. case MxL_BW_6MHz:
  343. val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A,
  344. * and DIG_MODEINDEX_CSF */
  345. break;
  346. case MxL_BW_7MHz:
  347. val = 0x2a;
  348. break;
  349. case MxL_BW_8MHz:
  350. val = 0x3f;
  351. break;
  352. default:
  353. mxl_fail(-EINVAL);
  354. return;
  355. }
  356. set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val);
  357. return;
  358. }
  359. static struct
  360. reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state,
  361. u32 rf_freq, enum mxl5007t_bw_mhz bw)
  362. {
  363. u32 dig_rf_freq = 0;
  364. u32 temp;
  365. u32 frac_divider = 1000000;
  366. unsigned int i;
  367. memcpy(&state->tab_rftune, &reg_pair_rftune, sizeof(reg_pair_rftune));
  368. mxl5007t_set_bw_bits(state, bw);
  369. /* Convert RF frequency into 16 bits =>
  370. * 10 bit integer (MHz) + 6 bit fraction */
  371. dig_rf_freq = rf_freq / MHz;
  372. temp = rf_freq % MHz;
  373. for (i = 0; i < 6; i++) {
  374. dig_rf_freq <<= 1;
  375. frac_divider /= 2;
  376. if (temp > frac_divider) {
  377. temp -= frac_divider;
  378. dig_rf_freq++;
  379. }
  380. }
  381. /* add to have shift center point by 7.8124 kHz */
  382. if (temp > 7812)
  383. dig_rf_freq++;
  384. set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq);
  385. set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8));
  386. if (rf_freq >= 333000000)
  387. set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40);
  388. return state->tab_rftune;
  389. }
  390. /* ------------------------------------------------------------------------- */
  391. static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val)
  392. {
  393. u8 buf[] = { reg, val };
  394. struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0,
  395. .buf = buf, .len = 2 };
  396. int ret;
  397. ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
  398. if (ret != 1) {
  399. mxl_err("failed!");
  400. return -EREMOTEIO;
  401. }
  402. return 0;
  403. }
  404. static int mxl5007t_write_regs(struct mxl5007t_state *state,
  405. struct reg_pair_t *reg_pair)
  406. {
  407. unsigned int i = 0;
  408. int ret = 0;
  409. while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) {
  410. ret = mxl5007t_write_reg(state,
  411. reg_pair[i].reg, reg_pair[i].val);
  412. i++;
  413. }
  414. return ret;
  415. }
  416. static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val)
  417. {
  418. u8 buf[2] = { 0xfb, reg };
  419. struct i2c_msg msg[] = {
  420. { .addr = state->i2c_props.addr, .flags = 0,
  421. .buf = buf, .len = 2 },
  422. { .addr = state->i2c_props.addr, .flags = I2C_M_RD,
  423. .buf = val, .len = 1 },
  424. };
  425. int ret;
  426. ret = i2c_transfer(state->i2c_props.adap, msg, 2);
  427. if (ret != 2) {
  428. mxl_err("failed!");
  429. return -EREMOTEIO;
  430. }
  431. return 0;
  432. }
  433. static int mxl5007t_soft_reset(struct mxl5007t_state *state)
  434. {
  435. u8 d = 0xff;
  436. struct i2c_msg msg = {
  437. .addr = state->i2c_props.addr, .flags = 0,
  438. .buf = &d, .len = 1
  439. };
  440. int ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
  441. if (ret != 1) {
  442. mxl_err("failed!");
  443. return -EREMOTEIO;
  444. }
  445. return 0;
  446. }
  447. static int mxl5007t_tuner_init(struct mxl5007t_state *state,
  448. enum mxl5007t_mode mode)
  449. {
  450. struct reg_pair_t *init_regs;
  451. int ret;
  452. /* calculate initialization reg array */
  453. init_regs = mxl5007t_calc_init_regs(state, mode);
  454. ret = mxl5007t_write_regs(state, init_regs);
  455. if (mxl_fail(ret))
  456. goto fail;
  457. mdelay(1);
  458. fail:
  459. return ret;
  460. }
  461. static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz,
  462. enum mxl5007t_bw_mhz bw)
  463. {
  464. struct reg_pair_t *rf_tune_regs;
  465. int ret;
  466. /* calculate channel change reg array */
  467. rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw);
  468. ret = mxl5007t_write_regs(state, rf_tune_regs);
  469. if (mxl_fail(ret))
  470. goto fail;
  471. msleep(3);
  472. fail:
  473. return ret;
  474. }
  475. /* ------------------------------------------------------------------------- */
  476. static int mxl5007t_synth_lock_status(struct mxl5007t_state *state,
  477. int *rf_locked, int *ref_locked)
  478. {
  479. u8 d;
  480. int ret;
  481. *rf_locked = 0;
  482. *ref_locked = 0;
  483. ret = mxl5007t_read_reg(state, 0xd8, &d);
  484. if (mxl_fail(ret))
  485. goto fail;
  486. if ((d & 0x0c) == 0x0c)
  487. *rf_locked = 1;
  488. if ((d & 0x03) == 0x03)
  489. *ref_locked = 1;
  490. fail:
  491. return ret;
  492. }
  493. /* ------------------------------------------------------------------------- */
  494. static int mxl5007t_get_status(struct dvb_frontend *fe, u32 *status)
  495. {
  496. struct mxl5007t_state *state = fe->tuner_priv;
  497. int rf_locked, ref_locked, ret;
  498. *status = 0;
  499. if (fe->ops.i2c_gate_ctrl)
  500. fe->ops.i2c_gate_ctrl(fe, 1);
  501. ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked);
  502. if (mxl_fail(ret))
  503. goto fail;
  504. mxl_debug("%s%s", rf_locked ? "rf locked " : "",
  505. ref_locked ? "ref locked" : "");
  506. if ((rf_locked) || (ref_locked))
  507. *status |= TUNER_STATUS_LOCKED;
  508. fail:
  509. if (fe->ops.i2c_gate_ctrl)
  510. fe->ops.i2c_gate_ctrl(fe, 0);
  511. return ret;
  512. }
  513. /* ------------------------------------------------------------------------- */
  514. static int mxl5007t_set_params(struct dvb_frontend *fe)
  515. {
  516. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  517. u32 delsys = c->delivery_system;
  518. struct mxl5007t_state *state = fe->tuner_priv;
  519. enum mxl5007t_bw_mhz bw;
  520. enum mxl5007t_mode mode;
  521. int ret;
  522. u32 freq = c->frequency;
  523. switch (delsys) {
  524. case SYS_ATSC:
  525. mode = MxL_MODE_ATSC;
  526. bw = MxL_BW_6MHz;
  527. break;
  528. case SYS_DVBC_ANNEX_B:
  529. mode = MxL_MODE_CABLE;
  530. bw = MxL_BW_6MHz;
  531. break;
  532. case SYS_DVBT:
  533. case SYS_DVBT2:
  534. mode = MxL_MODE_DVBT;
  535. switch (c->bandwidth_hz) {
  536. case 6000000:
  537. bw = MxL_BW_6MHz;
  538. break;
  539. case 7000000:
  540. bw = MxL_BW_7MHz;
  541. break;
  542. case 8000000:
  543. bw = MxL_BW_8MHz;
  544. break;
  545. default:
  546. return -EINVAL;
  547. }
  548. break;
  549. default:
  550. mxl_err("modulation type not supported!");
  551. return -EINVAL;
  552. }
  553. if (fe->ops.i2c_gate_ctrl)
  554. fe->ops.i2c_gate_ctrl(fe, 1);
  555. mutex_lock(&state->lock);
  556. ret = mxl5007t_tuner_init(state, mode);
  557. if (mxl_fail(ret))
  558. goto fail;
  559. ret = mxl5007t_tuner_rf_tune(state, freq, bw);
  560. if (mxl_fail(ret))
  561. goto fail;
  562. state->frequency = freq;
  563. state->bandwidth = c->bandwidth_hz;
  564. fail:
  565. mutex_unlock(&state->lock);
  566. if (fe->ops.i2c_gate_ctrl)
  567. fe->ops.i2c_gate_ctrl(fe, 0);
  568. return ret;
  569. }
  570. /* ------------------------------------------------------------------------- */
  571. static int mxl5007t_init(struct dvb_frontend *fe)
  572. {
  573. struct mxl5007t_state *state = fe->tuner_priv;
  574. int ret;
  575. if (fe->ops.i2c_gate_ctrl)
  576. fe->ops.i2c_gate_ctrl(fe, 1);
  577. /* wake from standby */
  578. ret = mxl5007t_write_reg(state, 0x01, 0x01);
  579. mxl_fail(ret);
  580. if (fe->ops.i2c_gate_ctrl)
  581. fe->ops.i2c_gate_ctrl(fe, 0);
  582. return ret;
  583. }
  584. static int mxl5007t_sleep(struct dvb_frontend *fe)
  585. {
  586. struct mxl5007t_state *state = fe->tuner_priv;
  587. int ret;
  588. if (fe->ops.i2c_gate_ctrl)
  589. fe->ops.i2c_gate_ctrl(fe, 1);
  590. /* enter standby mode */
  591. ret = mxl5007t_write_reg(state, 0x01, 0x00);
  592. mxl_fail(ret);
  593. ret = mxl5007t_write_reg(state, 0x0f, 0x00);
  594. mxl_fail(ret);
  595. if (fe->ops.i2c_gate_ctrl)
  596. fe->ops.i2c_gate_ctrl(fe, 0);
  597. return ret;
  598. }
  599. /* ------------------------------------------------------------------------- */
  600. static int mxl5007t_get_frequency(struct dvb_frontend *fe, u32 *frequency)
  601. {
  602. struct mxl5007t_state *state = fe->tuner_priv;
  603. *frequency = state->frequency;
  604. return 0;
  605. }
  606. static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
  607. {
  608. struct mxl5007t_state *state = fe->tuner_priv;
  609. *bandwidth = state->bandwidth;
  610. return 0;
  611. }
  612. static int mxl5007t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
  613. {
  614. struct mxl5007t_state *state = fe->tuner_priv;
  615. *frequency = 0;
  616. switch (state->if_freq) {
  617. case MxL_IF_4_MHZ:
  618. *frequency = 4000000;
  619. break;
  620. case MxL_IF_4_5_MHZ:
  621. *frequency = 4500000;
  622. break;
  623. case MxL_IF_4_57_MHZ:
  624. *frequency = 4570000;
  625. break;
  626. case MxL_IF_5_MHZ:
  627. *frequency = 5000000;
  628. break;
  629. case MxL_IF_5_38_MHZ:
  630. *frequency = 5380000;
  631. break;
  632. case MxL_IF_6_MHZ:
  633. *frequency = 6000000;
  634. break;
  635. case MxL_IF_6_28_MHZ:
  636. *frequency = 6280000;
  637. break;
  638. case MxL_IF_9_1915_MHZ:
  639. *frequency = 9191500;
  640. break;
  641. case MxL_IF_35_25_MHZ:
  642. *frequency = 35250000;
  643. break;
  644. case MxL_IF_36_15_MHZ:
  645. *frequency = 36150000;
  646. break;
  647. case MxL_IF_44_MHZ:
  648. *frequency = 44000000;
  649. break;
  650. }
  651. return 0;
  652. }
  653. static void mxl5007t_release(struct dvb_frontend *fe)
  654. {
  655. struct mxl5007t_state *state = fe->tuner_priv;
  656. mutex_lock(&mxl5007t_list_mutex);
  657. if (state)
  658. hybrid_tuner_release_state(state);
  659. mutex_unlock(&mxl5007t_list_mutex);
  660. fe->tuner_priv = NULL;
  661. }
  662. /* ------------------------------------------------------------------------- */
  663. static const struct dvb_tuner_ops mxl5007t_tuner_ops = {
  664. .info = {
  665. .name = "MaxLinear MxL5007T",
  666. },
  667. .init = mxl5007t_init,
  668. .sleep = mxl5007t_sleep,
  669. .set_params = mxl5007t_set_params,
  670. .get_status = mxl5007t_get_status,
  671. .get_frequency = mxl5007t_get_frequency,
  672. .get_bandwidth = mxl5007t_get_bandwidth,
  673. .release = mxl5007t_release,
  674. .get_if_frequency = mxl5007t_get_if_frequency,
  675. };
  676. static int mxl5007t_get_chip_id(struct mxl5007t_state *state)
  677. {
  678. char *name;
  679. int ret;
  680. u8 id;
  681. ret = mxl5007t_read_reg(state, 0xd9, &id);
  682. if (mxl_fail(ret))
  683. goto fail;
  684. switch (id) {
  685. case MxL_5007_V1_F1:
  686. name = "MxL5007.v1.f1";
  687. break;
  688. case MxL_5007_V1_F2:
  689. name = "MxL5007.v1.f2";
  690. break;
  691. case MxL_5007_V2_100_F1:
  692. name = "MxL5007.v2.100.f1";
  693. break;
  694. case MxL_5007_V2_100_F2:
  695. name = "MxL5007.v2.100.f2";
  696. break;
  697. case MxL_5007_V2_200_F1:
  698. name = "MxL5007.v2.200.f1";
  699. break;
  700. case MxL_5007_V2_200_F2:
  701. name = "MxL5007.v2.200.f2";
  702. break;
  703. case MxL_5007_V4:
  704. name = "MxL5007T.v4";
  705. break;
  706. default:
  707. name = "MxL5007T";
  708. printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id);
  709. id = MxL_UNKNOWN_ID;
  710. }
  711. state->chip_id = id;
  712. mxl_info("%s detected @ %d-%04x", name,
  713. i2c_adapter_id(state->i2c_props.adap),
  714. state->i2c_props.addr);
  715. return 0;
  716. fail:
  717. mxl_warn("unable to identify device @ %d-%04x",
  718. i2c_adapter_id(state->i2c_props.adap),
  719. state->i2c_props.addr);
  720. state->chip_id = MxL_UNKNOWN_ID;
  721. return ret;
  722. }
  723. struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
  724. struct i2c_adapter *i2c, u8 addr,
  725. struct mxl5007t_config *cfg)
  726. {
  727. struct mxl5007t_state *state = NULL;
  728. int instance, ret;
  729. mutex_lock(&mxl5007t_list_mutex);
  730. instance = hybrid_tuner_request_state(struct mxl5007t_state, state,
  731. hybrid_tuner_instance_list,
  732. i2c, addr, "mxl5007t");
  733. switch (instance) {
  734. case 0:
  735. goto fail;
  736. case 1:
  737. /* new tuner instance */
  738. state->config = cfg;
  739. mutex_init(&state->lock);
  740. if (fe->ops.i2c_gate_ctrl)
  741. fe->ops.i2c_gate_ctrl(fe, 1);
  742. ret = mxl5007t_get_chip_id(state);
  743. if (fe->ops.i2c_gate_ctrl)
  744. fe->ops.i2c_gate_ctrl(fe, 0);
  745. /* check return value of mxl5007t_get_chip_id */
  746. if (mxl_fail(ret))
  747. goto fail;
  748. break;
  749. default:
  750. /* existing tuner instance */
  751. break;
  752. }
  753. if (fe->ops.i2c_gate_ctrl)
  754. fe->ops.i2c_gate_ctrl(fe, 1);
  755. ret = mxl5007t_soft_reset(state);
  756. if (fe->ops.i2c_gate_ctrl)
  757. fe->ops.i2c_gate_ctrl(fe, 0);
  758. if (mxl_fail(ret))
  759. goto fail;
  760. if (fe->ops.i2c_gate_ctrl)
  761. fe->ops.i2c_gate_ctrl(fe, 1);
  762. ret = mxl5007t_write_reg(state, 0x04,
  763. state->config->loop_thru_enable);
  764. if (fe->ops.i2c_gate_ctrl)
  765. fe->ops.i2c_gate_ctrl(fe, 0);
  766. if (mxl_fail(ret))
  767. goto fail;
  768. fe->tuner_priv = state;
  769. mutex_unlock(&mxl5007t_list_mutex);
  770. memcpy(&fe->ops.tuner_ops, &mxl5007t_tuner_ops,
  771. sizeof(struct dvb_tuner_ops));
  772. return fe;
  773. fail:
  774. mutex_unlock(&mxl5007t_list_mutex);
  775. mxl5007t_release(fe);
  776. return NULL;
  777. }
  778. EXPORT_SYMBOL_GPL(mxl5007t_attach);
  779. MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver");
  780. MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
  781. MODULE_LICENSE("GPL");
  782. MODULE_VERSION("0.2");