arkn141s_fpga.c 7.4 KB

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  1. #include <common.h>
  2. #include <dwmmc.h>
  3. #include <malloc.h>
  4. #include <debug_uart.h>
  5. #include <asm-generic/gpio.h>
  6. #include <asm/arch/ark-common.h>
  7. DECLARE_GLOBAL_DATA_PTR;
  8. #define ARK1668_UPDATE_MAGIC "ada7f0c6-7c86-11e9-8f9e-2a86e4085a59"
  9. #define rSYS_AHB_CLK_EN *((volatile unsigned int *)(0x40408044))
  10. #define rSYS_APB_CLK_EN *((volatile unsigned int *)(0x40408048))
  11. #define rSYS_PER_CLK_EN *((volatile unsigned int *)(0x40408050))
  12. #define rSYS_SD_CLK_CFG *((volatile unsigned int *)(0x40408058))
  13. #define rSYS_SD1_CLK_CFG *((volatile unsigned int *)(0x4040805C))
  14. #define rSYS_DEVICE_CLK_CFG1 *((volatile unsigned int *)(0x40408064))
  15. #define rSYS_SOFT_RSTNA *((volatile unsigned int *)(0x40408078))
  16. #define rSYS_PAD_CTRL00 *((volatile unsigned int *)(0x404080c0))
  17. #define rSYS_PAD_CTRL01 *((volatile unsigned int *)(0x404080c4))
  18. #define rSYS_PAD_CTRL02 *((volatile unsigned int *)(0x404080c8))
  19. #define rSYS_PAD_CTRL03 *((volatile unsigned int *)(0x404080cc))
  20. #define rSYS_PAD_CTRL04 *((volatile unsigned int *)(0x404080d0))
  21. #define rSYS_PAD_DRIVE00 *((volatile unsigned int *)(0x404080d4))
  22. #define rSYS_PAD_DRIVE01 *((volatile unsigned int *)(0x404080d8))
  23. #define rSYS_PAD_DRIVE02 *((volatile unsigned int *)(0x404080dc))
  24. #define rSYS_PAD_DRIVE03 *((volatile unsigned int *)(0x404080E0))
  25. #define rSYS_PAD_USB_CFG *((volatile unsigned int *)(0x404080E4))
  26. #define rSYS_PAD_USB_CFG1 *((volatile unsigned int *)(0x404080E8))
  27. #define rSYS_PAD_USB_CFG2 *((volatile unsigned int *)(0x404080Ec))
  28. static void dwmci_select_pad(void)
  29. {
  30. unsigned int val;
  31. /* use sd/mmc 0 */
  32. val = rSYS_PAD_CTRL02;
  33. val &= ~((0x3<<24)|(0x3<<22)|(0x3<<20)|(0x3<<18)|(0x3<<16)|(0x3<<14)|(0x3<<12));
  34. val |= ((0x1<<24)|(0x1<<22)|(0x1<<20)|(0x1<<18)|(0x1<<16)|(0x1<<14)|(0x1<<12));
  35. rSYS_PAD_CTRL02 = val;
  36. udelay(100);
  37. /* use emmc 1 */
  38. val = rSYS_PAD_CTRL03;
  39. val &= ~((0x3<<10)|(0x3<<8)|(0x3<<6)|(0x3<<4)|(0x3<<2)|(0x3<<0));
  40. val |= ((0x1<<10)|(0x1<<8)|(0x1<<6)|(0x1<<4)|(0x1<<2)|(0x1<<0));
  41. rSYS_PAD_CTRL03 = val;
  42. }
  43. static void dwmci_reset(void)
  44. {
  45. rSYS_SOFT_RSTNA &= ~((1<<29)|(1<<16));
  46. udelay(100);
  47. rSYS_SOFT_RSTNA |= ((1<<29)|(1<<16));
  48. }
  49. #define ARK_MMC_CLK 12000000
  50. static int ark_dwmci_init(char *name,u32 regbase, int bus_width, int index)
  51. {
  52. struct dwmci_host *host = NULL;
  53. host = malloc(sizeof(struct dwmci_host));
  54. if (!host) {
  55. printf("dwmci_host malloc fail!\n");
  56. return 1;
  57. }
  58. memset(host, 0, sizeof(struct dwmci_host));
  59. dwmci_select_pad();
  60. dwmci_reset();
  61. host->name = name;
  62. host->ioaddr = (void *)regbase;
  63. host->buswidth = bus_width;
  64. host->dev_index = index;
  65. host->bus_hz = ARK_MMC_CLK;
  66. host->fifoth_val = 64;
  67. host->fifo_mode = 1;
  68. add_dwmci(host, host->bus_hz, 400000);
  69. return 0;
  70. }
  71. int board_mmc_init(bd_t *bis)
  72. {
  73. ark_dwmci_init("ARK_MMC0", 0x70070000, 4, 0);
  74. ark_dwmci_init("ARK_MMC1", 0x70080000, 4, 0);
  75. return 0;
  76. }
  77. int dram_init(void)
  78. {
  79. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  80. CONFIG_SYS_SDRAM_SIZE);
  81. return 0;
  82. }
  83. int board_init(void)
  84. {
  85. unsigned int val;
  86. /* cpu1 disable */
  87. // rSYS_CPU_CTL &= ~(1 << 7);
  88. /* nand pad enable */
  89. // val = rSYS_PAD_CTRL08;
  90. // val &= ~((0x7<<27) | (0x7<<24) | (0x7<<21) | (0x7<<18) | (0x7<<15) | (0x7<<12) | (0x7<<9) | (0x7<<6));
  91. // val |= (0x1<<27) | (0x1<<24) | (0x1<<21) | (0x1<<18) | (0x1<<15) | (0x1<<12) | (0x1<<9) | (0x1<<6);
  92. // rSYS_PAD_CTRL08 = val;
  93. // val = rSYS_PAD_CTRL09;
  94. // val &= ~((0x7<<15) | (0x7<<12) | (0x7<<9) | (0x7<<6) | (0x7<<3) | (0x7<<0));
  95. // val |= (1<<15) | (1<<12) | (1<<9) | (1<<6) | (1<<3) | (1<<0);//enable nand cle, ale,ren,wen
  96. // rSYS_PAD_CTRL09 = val;
  97. /* spi pad enable */
  98. // val = rSYS_PAD_CTRL09;
  99. // val &= ~((0x7<<27) | (0x7<<24));
  100. // val |= (0x2<<27) | (0x2<<24);
  101. // rSYS_PAD_CTRL09 = val;
  102. // val = rSYS_PAD_CTRL0A;
  103. // val &= ~((0x7<<3) | (0x7<<0));
  104. // val |= (0x2<<0);
  105. // rSYS_PAD_CTRL0A = val;
  106. /* spi 0 pad enable */
  107. val = rSYS_PAD_CTRL01;
  108. val &= ~((0x3<<10) | (0x3 << 8)|(0x3 << 6)|(0x3 << 4));
  109. // val |= ((0x1<<10) |(0x1 << 8)|(0x1 << 6)|(0x1 << 4));
  110. val |= ((0x1 << 8)|(0x1 << 6)|(0x1 << 4));
  111. rSYS_PAD_CTRL01 = val;
  112. /* gmac pad enable */
  113. // rSYS_PAD_CTRL0C = (1 << 27) | (1 << 24) | (1 << 21) | (1 << 18) | (1 << 15) | (1 << 12) | (1 << 9) |
  114. // (1 << 6) | (1 << 3) | (1 << 0);
  115. // rSYS_PAD_CTRL0D = (1 << 24) | (1 << 21) | (1 << 18) | (1 << 15) | (1 << 12) | (1 << 9) |
  116. // (1 << 6) | (1 << 3) | (1 << 0);
  117. // rSYS_PAD_CTRL0F |= (1 << 31);
  118. /* select rgmii interface */
  119. // rSYS_MFC_GMAC_CTL &= ~(7 << 1);
  120. // rSYS_MFC_GMAC_CTL |= (1 << 1);
  121. /* mac tx clk inv */
  122. // rSYS_DEVICE_CLK_CFG7 |= 1;
  123. /* i2s0 sadata in */
  124. // rSYS_PAD_CTRL0F &= ~(1 << 28);
  125. /* i2s1 sadata out */
  126. // rSYS_PAD_CTRL0F |= (1 << 29);
  127. return 0;
  128. }
  129. #ifdef CONFIG_BOARD_EARLY_INIT_F
  130. int board_early_init_f(void)
  131. {
  132. #ifdef CONFIG_DEBUG_UART
  133. debug_uart_init();
  134. #endif
  135. return 0;
  136. }
  137. #endif
  138. int board_late_init(void)
  139. {
  140. char cmd[128];
  141. char *need_update,*update_flash;
  142. unsigned int loadaddr;
  143. int do_update = 0, update_from_mmc = 1;
  144. run_command("sf probe", 0);
  145. printf("+++++++++board_late_init+++++++\n");
  146. need_update = env_get("need_update");
  147. if (!strcmp(need_update, "yes")) {
  148. loadaddr = env_get_hex("loadaddr", 0);
  149. sprintf(cmd, "fatload %s %s %s update-magic", "mmc", env_get("sd_dev_part"), env_get("loadaddr"));
  150. run_command(cmd, 0);
  151. if (loadaddr && !memcmp((void *)loadaddr, ARK1668_UPDATE_MAGIC, strlen(ARK1668_UPDATE_MAGIC))) {
  152. do_update = 1;
  153. goto update_done;
  154. } else {
  155. printf("Wrong update magic, do not update from mmc.\n");
  156. }
  157. #ifdef CONFIG_USB_MUSB_HCD
  158. //use old musb driver
  159. run_command("usb start", 0);
  160. #endif
  161. sprintf(cmd, "fatload %s %s %s update-magic", "usb", "0", env_get("loadaddr"));
  162. run_command(cmd, 0);
  163. if (loadaddr && !memcmp((void *)loadaddr, ARK1668_UPDATE_MAGIC, strlen(ARK1668_UPDATE_MAGIC))) {
  164. do_update = 1;
  165. update_from_mmc = 0;
  166. } else {
  167. printf("Wrong update magic, do not update from usb.\n");
  168. }
  169. }
  170. else if (!strcmp(update_flash, "yes")){
  171. sprintf(cmd, "run updatefromflash");
  172. printf("cmd=%s\n", cmd);
  173. run_command(cmd, 0);
  174. }
  175. update_done:
  176. if (do_update) {
  177. //run_command("nand erase.part userdata", 0);
  178. env_set("need_update", "no");
  179. env_set("do_update", "yes");
  180. if (update_from_mmc) {
  181. printf("update form mmc...\n");
  182. env_set("update_dev_type", "mmc");
  183. env_set("update_dev_part", env_get("sd_dev_part"));
  184. } else {
  185. printf("update form usb...\n");
  186. env_set("update_dev_type", "usb");
  187. env_set("update_dev_part", "0");
  188. }
  189. } else {
  190. env_set("do_update", "no");
  191. }
  192. return 0;
  193. }
  194. #if 0
  195. #ifdef CONFIG_SPL_BUILD
  196. static inline void ApbWriteFun(unsigned int addr, unsigned int data)
  197. {
  198. * (volatile unsigned int *) addr = data;
  199. }
  200. void mem_init(void)
  201. {
  202. ApbWriteFun(0xE490006c, 0x80000); //device_cfg for ddr2_ref_clk
  203. udelay(20);
  204. ApbWriteFun(0xE4900214, 0x0);
  205. //softa
  206. ApbWriteFun(0xE4900078, 0xfffffffd);
  207. udelay(2);
  208. ApbWriteFun(0xE4900214, 0xFFF0BFFF);//PLL_PDN=[13]=1
  209. udelay(20); // > 50us
  210. ApbWriteFun(0xE4900214, 0xFFF8BFFF);//PLL_RSTN=[19]=1
  211. udelay(10);
  212. ApbWriteFun(0xE4900214, 0xFFF8FFFF);//DLL_PDN=[14]=1
  213. udelay(50);//> 100us
  214. ApbWriteFun(0xE4900214, 0xFFFBFFFF);//DDR_PHY_RSTN=[16]=[17]=1
  215. udelay(10);
  216. ApbWriteFun(0xE4900214, 0xFFFFFFFF);//DDR_DPHY_RSTN=[18]=1
  217. udelay(10);
  218. ApbWriteFun(0xE4900214, 0xFFFFEFFF);//=[12]=ddr_srf_req=0;
  219. udelay(10);
  220. ApbWriteFun(0xE4900210, 0x70000800);
  221. ApbWriteFun(0xE4900214, 0xFFEFE074);
  222. udelay(10);
  223. ApbWriteFun(0xE4900078, 0xffffffff);
  224. ddr3_sdramc_init();
  225. }
  226. #endif
  227. #endif