eeh.c 48 KB

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  1. /*
  2. * Copyright IBM Corporation 2001, 2005, 2006
  3. * Copyright Dave Engebretsen & Todd Inglett 2001
  4. * Copyright Linas Vepstas 2005, 2006
  5. * Copyright 2001-2012 IBM Corporation.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. *
  21. * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com>
  22. */
  23. #include <linux/delay.h>
  24. #include <linux/sched.h>
  25. #include <linux/init.h>
  26. #include <linux/list.h>
  27. #include <linux/pci.h>
  28. #include <linux/iommu.h>
  29. #include <linux/proc_fs.h>
  30. #include <linux/rbtree.h>
  31. #include <linux/reboot.h>
  32. #include <linux/seq_file.h>
  33. #include <linux/spinlock.h>
  34. #include <linux/export.h>
  35. #include <linux/of.h>
  36. #include <linux/atomic.h>
  37. #include <asm/debugfs.h>
  38. #include <asm/eeh.h>
  39. #include <asm/eeh_event.h>
  40. #include <asm/io.h>
  41. #include <asm/iommu.h>
  42. #include <asm/machdep.h>
  43. #include <asm/ppc-pci.h>
  44. #include <asm/rtas.h>
  45. #include <asm/pte-walk.h>
  46. /** Overview:
  47. * EEH, or "Enhanced Error Handling" is a PCI bridge technology for
  48. * dealing with PCI bus errors that can't be dealt with within the
  49. * usual PCI framework, except by check-stopping the CPU. Systems
  50. * that are designed for high-availability/reliability cannot afford
  51. * to crash due to a "mere" PCI error, thus the need for EEH.
  52. * An EEH-capable bridge operates by converting a detected error
  53. * into a "slot freeze", taking the PCI adapter off-line, making
  54. * the slot behave, from the OS'es point of view, as if the slot
  55. * were "empty": all reads return 0xff's and all writes are silently
  56. * ignored. EEH slot isolation events can be triggered by parity
  57. * errors on the address or data busses (e.g. during posted writes),
  58. * which in turn might be caused by low voltage on the bus, dust,
  59. * vibration, humidity, radioactivity or plain-old failed hardware.
  60. *
  61. * Note, however, that one of the leading causes of EEH slot
  62. * freeze events are buggy device drivers, buggy device microcode,
  63. * or buggy device hardware. This is because any attempt by the
  64. * device to bus-master data to a memory address that is not
  65. * assigned to the device will trigger a slot freeze. (The idea
  66. * is to prevent devices-gone-wild from corrupting system memory).
  67. * Buggy hardware/drivers will have a miserable time co-existing
  68. * with EEH.
  69. *
  70. * Ideally, a PCI device driver, when suspecting that an isolation
  71. * event has occurred (e.g. by reading 0xff's), will then ask EEH
  72. * whether this is the case, and then take appropriate steps to
  73. * reset the PCI slot, the PCI device, and then resume operations.
  74. * However, until that day, the checking is done here, with the
  75. * eeh_check_failure() routine embedded in the MMIO macros. If
  76. * the slot is found to be isolated, an "EEH Event" is synthesized
  77. * and sent out for processing.
  78. */
  79. /* If a device driver keeps reading an MMIO register in an interrupt
  80. * handler after a slot isolation event, it might be broken.
  81. * This sets the threshold for how many read attempts we allow
  82. * before printing an error message.
  83. */
  84. #define EEH_MAX_FAILS 2100000
  85. /* Time to wait for a PCI slot to report status, in milliseconds */
  86. #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
  87. /*
  88. * EEH probe mode support, which is part of the flags,
  89. * is to support multiple platforms for EEH. Some platforms
  90. * like pSeries do PCI emunation based on device tree.
  91. * However, other platforms like powernv probe PCI devices
  92. * from hardware. The flag is used to distinguish that.
  93. * In addition, struct eeh_ops::probe would be invoked for
  94. * particular OF node or PCI device so that the corresponding
  95. * PE would be created there.
  96. */
  97. int eeh_subsystem_flags;
  98. EXPORT_SYMBOL(eeh_subsystem_flags);
  99. /*
  100. * EEH allowed maximal frozen times. If one particular PE's
  101. * frozen count in last hour exceeds this limit, the PE will
  102. * be forced to be offline permanently.
  103. */
  104. int eeh_max_freezes = 5;
  105. /* Platform dependent EEH operations */
  106. struct eeh_ops *eeh_ops = NULL;
  107. /* Lock to avoid races due to multiple reports of an error */
  108. DEFINE_RAW_SPINLOCK(confirm_error_lock);
  109. EXPORT_SYMBOL_GPL(confirm_error_lock);
  110. /* Lock to protect passed flags */
  111. static DEFINE_MUTEX(eeh_dev_mutex);
  112. /* Buffer for reporting pci register dumps. Its here in BSS, and
  113. * not dynamically alloced, so that it ends up in RMO where RTAS
  114. * can access it.
  115. */
  116. #define EEH_PCI_REGS_LOG_LEN 8192
  117. static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
  118. /*
  119. * The struct is used to maintain the EEH global statistic
  120. * information. Besides, the EEH global statistics will be
  121. * exported to user space through procfs
  122. */
  123. struct eeh_stats {
  124. u64 no_device; /* PCI device not found */
  125. u64 no_dn; /* OF node not found */
  126. u64 no_cfg_addr; /* Config address not found */
  127. u64 ignored_check; /* EEH check skipped */
  128. u64 total_mmio_ffs; /* Total EEH checks */
  129. u64 false_positives; /* Unnecessary EEH checks */
  130. u64 slot_resets; /* PE reset */
  131. };
  132. static struct eeh_stats eeh_stats;
  133. static int __init eeh_setup(char *str)
  134. {
  135. if (!strcmp(str, "off"))
  136. eeh_add_flag(EEH_FORCE_DISABLED);
  137. else if (!strcmp(str, "early_log"))
  138. eeh_add_flag(EEH_EARLY_DUMP_LOG);
  139. return 1;
  140. }
  141. __setup("eeh=", eeh_setup);
  142. /*
  143. * This routine captures assorted PCI configuration space data
  144. * for the indicated PCI device, and puts them into a buffer
  145. * for RTAS error logging.
  146. */
  147. static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
  148. {
  149. struct pci_dn *pdn = eeh_dev_to_pdn(edev);
  150. u32 cfg;
  151. int cap, i;
  152. int n = 0, l = 0;
  153. char buffer[128];
  154. if (!pdn) {
  155. pr_warn("EEH: Note: No error log for absent device.\n");
  156. return 0;
  157. }
  158. n += scnprintf(buf+n, len-n, "%04x:%02x:%02x.%01x\n",
  159. pdn->phb->global_number, pdn->busno,
  160. PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
  161. pr_warn("EEH: of node=%04x:%02x:%02x.%01x\n",
  162. pdn->phb->global_number, pdn->busno,
  163. PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
  164. eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
  165. n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
  166. pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
  167. eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg);
  168. n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
  169. pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
  170. /* Gather bridge-specific registers */
  171. if (edev->mode & EEH_DEV_BRIDGE) {
  172. eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
  173. n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
  174. pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
  175. eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
  176. n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
  177. pr_warn("EEH: Bridge control: %04x\n", cfg);
  178. }
  179. /* Dump out the PCI-X command and status regs */
  180. cap = edev->pcix_cap;
  181. if (cap) {
  182. eeh_ops->read_config(pdn, cap, 4, &cfg);
  183. n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
  184. pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
  185. eeh_ops->read_config(pdn, cap+4, 4, &cfg);
  186. n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
  187. pr_warn("EEH: PCI-X status: %08x\n", cfg);
  188. }
  189. /* If PCI-E capable, dump PCI-E cap 10 */
  190. cap = edev->pcie_cap;
  191. if (cap) {
  192. n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
  193. pr_warn("EEH: PCI-E capabilities and status follow:\n");
  194. for (i=0; i<=8; i++) {
  195. eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
  196. n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
  197. if ((i % 4) == 0) {
  198. if (i != 0)
  199. pr_warn("%s\n", buffer);
  200. l = scnprintf(buffer, sizeof(buffer),
  201. "EEH: PCI-E %02x: %08x ",
  202. 4*i, cfg);
  203. } else {
  204. l += scnprintf(buffer+l, sizeof(buffer)-l,
  205. "%08x ", cfg);
  206. }
  207. }
  208. pr_warn("%s\n", buffer);
  209. }
  210. /* If AER capable, dump it */
  211. cap = edev->aer_cap;
  212. if (cap) {
  213. n += scnprintf(buf+n, len-n, "pci-e AER:\n");
  214. pr_warn("EEH: PCI-E AER capability register set follows:\n");
  215. for (i=0; i<=13; i++) {
  216. eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
  217. n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
  218. if ((i % 4) == 0) {
  219. if (i != 0)
  220. pr_warn("%s\n", buffer);
  221. l = scnprintf(buffer, sizeof(buffer),
  222. "EEH: PCI-E AER %02x: %08x ",
  223. 4*i, cfg);
  224. } else {
  225. l += scnprintf(buffer+l, sizeof(buffer)-l,
  226. "%08x ", cfg);
  227. }
  228. }
  229. pr_warn("%s\n", buffer);
  230. }
  231. return n;
  232. }
  233. static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag)
  234. {
  235. struct eeh_dev *edev, *tmp;
  236. size_t *plen = flag;
  237. eeh_pe_for_each_dev(pe, edev, tmp)
  238. *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen,
  239. EEH_PCI_REGS_LOG_LEN - *plen);
  240. return NULL;
  241. }
  242. /**
  243. * eeh_slot_error_detail - Generate combined log including driver log and error log
  244. * @pe: EEH PE
  245. * @severity: temporary or permanent error log
  246. *
  247. * This routine should be called to generate the combined log, which
  248. * is comprised of driver log and error log. The driver log is figured
  249. * out from the config space of the corresponding PCI device, while
  250. * the error log is fetched through platform dependent function call.
  251. */
  252. void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
  253. {
  254. size_t loglen = 0;
  255. /*
  256. * When the PHB is fenced or dead, it's pointless to collect
  257. * the data from PCI config space because it should return
  258. * 0xFF's. For ER, we still retrieve the data from the PCI
  259. * config space.
  260. *
  261. * For pHyp, we have to enable IO for log retrieval. Otherwise,
  262. * 0xFF's is always returned from PCI config space.
  263. *
  264. * When the @severity is EEH_LOG_PERM, the PE is going to be
  265. * removed. Prior to that, the drivers for devices included in
  266. * the PE will be closed. The drivers rely on working IO path
  267. * to bring the devices to quiet state. Otherwise, PCI traffic
  268. * from those devices after they are removed is like to cause
  269. * another unexpected EEH error.
  270. */
  271. if (!(pe->type & EEH_PE_PHB)) {
  272. if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) ||
  273. severity == EEH_LOG_PERM)
  274. eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
  275. /*
  276. * The config space of some PCI devices can't be accessed
  277. * when their PEs are in frozen state. Otherwise, fenced
  278. * PHB might be seen. Those PEs are identified with flag
  279. * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED
  280. * is set automatically when the PE is put to EEH_PE_ISOLATED.
  281. *
  282. * Restoring BARs possibly triggers PCI config access in
  283. * (OPAL) firmware and then causes fenced PHB. If the
  284. * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's
  285. * pointless to restore BARs and dump config space.
  286. */
  287. eeh_ops->configure_bridge(pe);
  288. if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
  289. eeh_pe_restore_bars(pe);
  290. pci_regs_buf[0] = 0;
  291. eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
  292. }
  293. }
  294. eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
  295. }
  296. /**
  297. * eeh_token_to_phys - Convert EEH address token to phys address
  298. * @token: I/O token, should be address in the form 0xA....
  299. *
  300. * This routine should be called to convert virtual I/O address
  301. * to physical one.
  302. */
  303. static inline unsigned long eeh_token_to_phys(unsigned long token)
  304. {
  305. pte_t *ptep;
  306. unsigned long pa;
  307. int hugepage_shift;
  308. /*
  309. * We won't find hugepages here(this is iomem). Hence we are not
  310. * worried about _PAGE_SPLITTING/collapse. Also we will not hit
  311. * page table free, because of init_mm.
  312. */
  313. ptep = find_init_mm_pte(token, &hugepage_shift);
  314. if (!ptep)
  315. return token;
  316. pa = pte_pfn(*ptep);
  317. /* On radix we can do hugepage mappings for io, so handle that */
  318. if (!hugepage_shift)
  319. hugepage_shift = PAGE_SHIFT;
  320. pa <<= PAGE_SHIFT;
  321. pa |= token & ((1ul << hugepage_shift) - 1);
  322. return pa;
  323. }
  324. /*
  325. * On PowerNV platform, we might already have fenced PHB there.
  326. * For that case, it's meaningless to recover frozen PE. Intead,
  327. * We have to handle fenced PHB firstly.
  328. */
  329. static int eeh_phb_check_failure(struct eeh_pe *pe)
  330. {
  331. struct eeh_pe *phb_pe;
  332. unsigned long flags;
  333. int ret;
  334. if (!eeh_has_flag(EEH_PROBE_MODE_DEV))
  335. return -EPERM;
  336. /* Find the PHB PE */
  337. phb_pe = eeh_phb_pe_get(pe->phb);
  338. if (!phb_pe) {
  339. pr_warn("%s Can't find PE for PHB#%x\n",
  340. __func__, pe->phb->global_number);
  341. return -EEXIST;
  342. }
  343. /* If the PHB has been in problematic state */
  344. eeh_serialize_lock(&flags);
  345. if (phb_pe->state & EEH_PE_ISOLATED) {
  346. ret = 0;
  347. goto out;
  348. }
  349. /* Check PHB state */
  350. ret = eeh_ops->get_state(phb_pe, NULL);
  351. if ((ret < 0) ||
  352. (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
  353. ret = 0;
  354. goto out;
  355. }
  356. /* Isolate the PHB and send event */
  357. eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED);
  358. eeh_serialize_unlock(flags);
  359. pr_err("EEH: PHB#%x failure detected, location: %s\n",
  360. phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe));
  361. dump_stack();
  362. eeh_send_failure_event(phb_pe);
  363. return 1;
  364. out:
  365. eeh_serialize_unlock(flags);
  366. return ret;
  367. }
  368. /**
  369. * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
  370. * @edev: eeh device
  371. *
  372. * Check for an EEH failure for the given device node. Call this
  373. * routine if the result of a read was all 0xff's and you want to
  374. * find out if this is due to an EEH slot freeze. This routine
  375. * will query firmware for the EEH status.
  376. *
  377. * Returns 0 if there has not been an EEH error; otherwise returns
  378. * a non-zero value and queues up a slot isolation event notification.
  379. *
  380. * It is safe to call this routine in an interrupt context.
  381. */
  382. int eeh_dev_check_failure(struct eeh_dev *edev)
  383. {
  384. int ret;
  385. unsigned long flags;
  386. struct device_node *dn;
  387. struct pci_dev *dev;
  388. struct eeh_pe *pe, *parent_pe, *phb_pe;
  389. int rc = 0;
  390. const char *location = NULL;
  391. eeh_stats.total_mmio_ffs++;
  392. if (!eeh_enabled())
  393. return 0;
  394. if (!edev) {
  395. eeh_stats.no_dn++;
  396. return 0;
  397. }
  398. dev = eeh_dev_to_pci_dev(edev);
  399. pe = eeh_dev_to_pe(edev);
  400. /* Access to IO BARs might get this far and still not want checking. */
  401. if (!pe) {
  402. eeh_stats.ignored_check++;
  403. pr_debug("EEH: Ignored check for %s\n",
  404. eeh_pci_name(dev));
  405. return 0;
  406. }
  407. if (!pe->addr && !pe->config_addr) {
  408. eeh_stats.no_cfg_addr++;
  409. return 0;
  410. }
  411. /*
  412. * On PowerNV platform, we might already have fenced PHB
  413. * there and we need take care of that firstly.
  414. */
  415. ret = eeh_phb_check_failure(pe);
  416. if (ret > 0)
  417. return ret;
  418. /*
  419. * If the PE isn't owned by us, we shouldn't check the
  420. * state. Instead, let the owner handle it if the PE has
  421. * been frozen.
  422. */
  423. if (eeh_pe_passed(pe))
  424. return 0;
  425. /* If we already have a pending isolation event for this
  426. * slot, we know it's bad already, we don't need to check.
  427. * Do this checking under a lock; as multiple PCI devices
  428. * in one slot might report errors simultaneously, and we
  429. * only want one error recovery routine running.
  430. */
  431. eeh_serialize_lock(&flags);
  432. rc = 1;
  433. if (pe->state & EEH_PE_ISOLATED) {
  434. pe->check_count++;
  435. if (pe->check_count == EEH_MAX_FAILS) {
  436. dn = pci_device_to_OF_node(dev);
  437. if (dn)
  438. location = of_get_property(dn, "ibm,loc-code",
  439. NULL);
  440. printk(KERN_ERR "EEH: %d reads ignored for recovering device at "
  441. "location=%s driver=%s pci addr=%s\n",
  442. pe->check_count,
  443. location ? location : "unknown",
  444. eeh_driver_name(dev), eeh_pci_name(dev));
  445. printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n",
  446. eeh_driver_name(dev));
  447. dump_stack();
  448. }
  449. goto dn_unlock;
  450. }
  451. /*
  452. * Now test for an EEH failure. This is VERY expensive.
  453. * Note that the eeh_config_addr may be a parent device
  454. * in the case of a device behind a bridge, or it may be
  455. * function zero of a multi-function device.
  456. * In any case they must share a common PHB.
  457. */
  458. ret = eeh_ops->get_state(pe, NULL);
  459. /* Note that config-io to empty slots may fail;
  460. * they are empty when they don't have children.
  461. * We will punt with the following conditions: Failure to get
  462. * PE's state, EEH not support and Permanently unavailable
  463. * state, PE is in good state.
  464. */
  465. if ((ret < 0) ||
  466. (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
  467. eeh_stats.false_positives++;
  468. pe->false_positives++;
  469. rc = 0;
  470. goto dn_unlock;
  471. }
  472. /*
  473. * It should be corner case that the parent PE has been
  474. * put into frozen state as well. We should take care
  475. * that at first.
  476. */
  477. parent_pe = pe->parent;
  478. while (parent_pe) {
  479. /* Hit the ceiling ? */
  480. if (parent_pe->type & EEH_PE_PHB)
  481. break;
  482. /* Frozen parent PE ? */
  483. ret = eeh_ops->get_state(parent_pe, NULL);
  484. if (ret > 0 && !eeh_state_active(ret)) {
  485. pe = parent_pe;
  486. pr_err("EEH: Failure of PHB#%x-PE#%x will be handled at parent PHB#%x-PE#%x.\n",
  487. pe->phb->global_number, pe->addr,
  488. pe->phb->global_number, parent_pe->addr);
  489. }
  490. /* Next parent level */
  491. parent_pe = parent_pe->parent;
  492. }
  493. eeh_stats.slot_resets++;
  494. /* Avoid repeated reports of this failure, including problems
  495. * with other functions on this device, and functions under
  496. * bridges.
  497. */
  498. eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
  499. eeh_serialize_unlock(flags);
  500. /* Most EEH events are due to device driver bugs. Having
  501. * a stack trace will help the device-driver authors figure
  502. * out what happened. So print that out.
  503. */
  504. phb_pe = eeh_phb_pe_get(pe->phb);
  505. pr_err("EEH: Frozen PHB#%x-PE#%x detected\n",
  506. pe->phb->global_number, pe->addr);
  507. pr_err("EEH: PE location: %s, PHB location: %s\n",
  508. eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe));
  509. dump_stack();
  510. eeh_send_failure_event(pe);
  511. return 1;
  512. dn_unlock:
  513. eeh_serialize_unlock(flags);
  514. return rc;
  515. }
  516. EXPORT_SYMBOL_GPL(eeh_dev_check_failure);
  517. /**
  518. * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
  519. * @token: I/O address
  520. *
  521. * Check for an EEH failure at the given I/O address. Call this
  522. * routine if the result of a read was all 0xff's and you want to
  523. * find out if this is due to an EEH slot freeze event. This routine
  524. * will query firmware for the EEH status.
  525. *
  526. * Note this routine is safe to call in an interrupt context.
  527. */
  528. int eeh_check_failure(const volatile void __iomem *token)
  529. {
  530. unsigned long addr;
  531. struct eeh_dev *edev;
  532. /* Finding the phys addr + pci device; this is pretty quick. */
  533. addr = eeh_token_to_phys((unsigned long __force) token);
  534. edev = eeh_addr_cache_get_dev(addr);
  535. if (!edev) {
  536. eeh_stats.no_device++;
  537. return 0;
  538. }
  539. return eeh_dev_check_failure(edev);
  540. }
  541. EXPORT_SYMBOL(eeh_check_failure);
  542. /**
  543. * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
  544. * @pe: EEH PE
  545. *
  546. * This routine should be called to reenable frozen MMIO or DMA
  547. * so that it would work correctly again. It's useful while doing
  548. * recovery or log collection on the indicated device.
  549. */
  550. int eeh_pci_enable(struct eeh_pe *pe, int function)
  551. {
  552. int active_flag, rc;
  553. /*
  554. * pHyp doesn't allow to enable IO or DMA on unfrozen PE.
  555. * Also, it's pointless to enable them on unfrozen PE. So
  556. * we have to check before enabling IO or DMA.
  557. */
  558. switch (function) {
  559. case EEH_OPT_THAW_MMIO:
  560. active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED;
  561. break;
  562. case EEH_OPT_THAW_DMA:
  563. active_flag = EEH_STATE_DMA_ACTIVE;
  564. break;
  565. case EEH_OPT_DISABLE:
  566. case EEH_OPT_ENABLE:
  567. case EEH_OPT_FREEZE_PE:
  568. active_flag = 0;
  569. break;
  570. default:
  571. pr_warn("%s: Invalid function %d\n",
  572. __func__, function);
  573. return -EINVAL;
  574. }
  575. /*
  576. * Check if IO or DMA has been enabled before
  577. * enabling them.
  578. */
  579. if (active_flag) {
  580. rc = eeh_ops->get_state(pe, NULL);
  581. if (rc < 0)
  582. return rc;
  583. /* Needn't enable it at all */
  584. if (rc == EEH_STATE_NOT_SUPPORT)
  585. return 0;
  586. /* It's already enabled */
  587. if (rc & active_flag)
  588. return 0;
  589. }
  590. /* Issue the request */
  591. rc = eeh_ops->set_option(pe, function);
  592. if (rc)
  593. pr_warn("%s: Unexpected state change %d on "
  594. "PHB#%x-PE#%x, err=%d\n",
  595. __func__, function, pe->phb->global_number,
  596. pe->addr, rc);
  597. /* Check if the request is finished successfully */
  598. if (active_flag) {
  599. rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
  600. if (rc < 0)
  601. return rc;
  602. if (rc & active_flag)
  603. return 0;
  604. return -EIO;
  605. }
  606. return rc;
  607. }
  608. static void *eeh_disable_and_save_dev_state(struct eeh_dev *edev,
  609. void *userdata)
  610. {
  611. struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
  612. struct pci_dev *dev = userdata;
  613. /*
  614. * The caller should have disabled and saved the
  615. * state for the specified device
  616. */
  617. if (!pdev || pdev == dev)
  618. return NULL;
  619. /* Ensure we have D0 power state */
  620. pci_set_power_state(pdev, PCI_D0);
  621. /* Save device state */
  622. pci_save_state(pdev);
  623. /*
  624. * Disable device to avoid any DMA traffic and
  625. * interrupt from the device
  626. */
  627. pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
  628. return NULL;
  629. }
  630. static void *eeh_restore_dev_state(struct eeh_dev *edev, void *userdata)
  631. {
  632. struct pci_dn *pdn = eeh_dev_to_pdn(edev);
  633. struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
  634. struct pci_dev *dev = userdata;
  635. if (!pdev)
  636. return NULL;
  637. /* Apply customization from firmware */
  638. if (pdn && eeh_ops->restore_config)
  639. eeh_ops->restore_config(pdn);
  640. /* The caller should restore state for the specified device */
  641. if (pdev != dev)
  642. pci_restore_state(pdev);
  643. return NULL;
  644. }
  645. int eeh_restore_vf_config(struct pci_dn *pdn)
  646. {
  647. struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
  648. u32 devctl, cmd, cap2, aer_capctl;
  649. int old_mps;
  650. if (edev->pcie_cap) {
  651. /* Restore MPS */
  652. old_mps = (ffs(pdn->mps) - 8) << 5;
  653. eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
  654. 2, &devctl);
  655. devctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
  656. devctl |= old_mps;
  657. eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
  658. 2, devctl);
  659. /* Disable Completion Timeout if possible */
  660. eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2,
  661. 4, &cap2);
  662. if (cap2 & PCI_EXP_DEVCAP2_COMP_TMOUT_DIS) {
  663. eeh_ops->read_config(pdn,
  664. edev->pcie_cap + PCI_EXP_DEVCTL2,
  665. 4, &cap2);
  666. cap2 |= PCI_EXP_DEVCTL2_COMP_TMOUT_DIS;
  667. eeh_ops->write_config(pdn,
  668. edev->pcie_cap + PCI_EXP_DEVCTL2,
  669. 4, cap2);
  670. }
  671. }
  672. /* Enable SERR and parity checking */
  673. eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd);
  674. cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  675. eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd);
  676. /* Enable report various errors */
  677. if (edev->pcie_cap) {
  678. eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
  679. 2, &devctl);
  680. devctl &= ~PCI_EXP_DEVCTL_CERE;
  681. devctl |= (PCI_EXP_DEVCTL_NFERE |
  682. PCI_EXP_DEVCTL_FERE |
  683. PCI_EXP_DEVCTL_URRE);
  684. eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
  685. 2, devctl);
  686. }
  687. /* Enable ECRC generation and check */
  688. if (edev->pcie_cap && edev->aer_cap) {
  689. eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP,
  690. 4, &aer_capctl);
  691. aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
  692. eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP,
  693. 4, aer_capctl);
  694. }
  695. return 0;
  696. }
  697. /**
  698. * pcibios_set_pcie_reset_state - Set PCI-E reset state
  699. * @dev: pci device struct
  700. * @state: reset state to enter
  701. *
  702. * Return value:
  703. * 0 if success
  704. */
  705. int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
  706. {
  707. struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
  708. struct eeh_pe *pe = eeh_dev_to_pe(edev);
  709. if (!pe) {
  710. pr_err("%s: No PE found on PCI device %s\n",
  711. __func__, pci_name(dev));
  712. return -EINVAL;
  713. }
  714. switch (state) {
  715. case pcie_deassert_reset:
  716. eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
  717. eeh_unfreeze_pe(pe, false);
  718. if (!(pe->type & EEH_PE_VF))
  719. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
  720. eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
  721. eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
  722. break;
  723. case pcie_hot_reset:
  724. eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
  725. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  726. eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
  727. if (!(pe->type & EEH_PE_VF))
  728. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  729. eeh_ops->reset(pe, EEH_RESET_HOT);
  730. break;
  731. case pcie_warm_reset:
  732. eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
  733. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  734. eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
  735. if (!(pe->type & EEH_PE_VF))
  736. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  737. eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
  738. break;
  739. default:
  740. eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED);
  741. return -EINVAL;
  742. };
  743. return 0;
  744. }
  745. /**
  746. * eeh_set_pe_freset - Check the required reset for the indicated device
  747. * @data: EEH device
  748. * @flag: return value
  749. *
  750. * Each device might have its preferred reset type: fundamental or
  751. * hot reset. The routine is used to collected the information for
  752. * the indicated device and its children so that the bunch of the
  753. * devices could be reset properly.
  754. */
  755. static void *eeh_set_dev_freset(struct eeh_dev *edev, void *flag)
  756. {
  757. struct pci_dev *dev;
  758. unsigned int *freset = (unsigned int *)flag;
  759. dev = eeh_dev_to_pci_dev(edev);
  760. if (dev)
  761. *freset |= dev->needs_freset;
  762. return NULL;
  763. }
  764. /**
  765. * eeh_pe_reset_full - Complete a full reset process on the indicated PE
  766. * @pe: EEH PE
  767. *
  768. * This function executes a full reset procedure on a PE, including setting
  769. * the appropriate flags, performing a fundamental or hot reset, and then
  770. * deactivating the reset status. It is designed to be used within the EEH
  771. * subsystem, as opposed to eeh_pe_reset which is exported to drivers and
  772. * only performs a single operation at a time.
  773. *
  774. * This function will attempt to reset a PE three times before failing.
  775. */
  776. int eeh_pe_reset_full(struct eeh_pe *pe)
  777. {
  778. int reset_state = (EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
  779. int type = EEH_RESET_HOT;
  780. unsigned int freset = 0;
  781. int i, state, ret;
  782. /*
  783. * Determine the type of reset to perform - hot or fundamental.
  784. * Hot reset is the default operation, unless any device under the
  785. * PE requires a fundamental reset.
  786. */
  787. eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
  788. if (freset)
  789. type = EEH_RESET_FUNDAMENTAL;
  790. /* Mark the PE as in reset state and block config space accesses */
  791. eeh_pe_state_mark(pe, reset_state);
  792. /* Make three attempts at resetting the bus */
  793. for (i = 0; i < 3; i++) {
  794. ret = eeh_pe_reset(pe, type);
  795. if (ret)
  796. break;
  797. ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE);
  798. if (ret)
  799. break;
  800. /* Wait until the PE is in a functioning state */
  801. state = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
  802. if (eeh_state_active(state))
  803. break;
  804. if (state < 0) {
  805. pr_warn("%s: Unrecoverable slot failure on PHB#%x-PE#%x",
  806. __func__, pe->phb->global_number, pe->addr);
  807. ret = -ENOTRECOVERABLE;
  808. break;
  809. }
  810. /* Set error in case this is our last attempt */
  811. ret = -EIO;
  812. pr_warn("%s: Failure %d resetting PHB#%x-PE#%x\n (%d)\n",
  813. __func__, state, pe->phb->global_number, pe->addr, (i + 1));
  814. }
  815. eeh_pe_state_clear(pe, reset_state);
  816. return ret;
  817. }
  818. /**
  819. * eeh_save_bars - Save device bars
  820. * @edev: PCI device associated EEH device
  821. *
  822. * Save the values of the device bars. Unlike the restore
  823. * routine, this routine is *not* recursive. This is because
  824. * PCI devices are added individually; but, for the restore,
  825. * an entire slot is reset at a time.
  826. */
  827. void eeh_save_bars(struct eeh_dev *edev)
  828. {
  829. struct pci_dn *pdn;
  830. int i;
  831. pdn = eeh_dev_to_pdn(edev);
  832. if (!pdn)
  833. return;
  834. for (i = 0; i < 16; i++)
  835. eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]);
  836. /*
  837. * For PCI bridges including root port, we need enable bus
  838. * master explicitly. Otherwise, it can't fetch IODA table
  839. * entries correctly. So we cache the bit in advance so that
  840. * we can restore it after reset, either PHB range or PE range.
  841. */
  842. if (edev->mode & EEH_DEV_BRIDGE)
  843. edev->config_space[1] |= PCI_COMMAND_MASTER;
  844. }
  845. /**
  846. * eeh_ops_register - Register platform dependent EEH operations
  847. * @ops: platform dependent EEH operations
  848. *
  849. * Register the platform dependent EEH operation callback
  850. * functions. The platform should call this function before
  851. * any other EEH operations.
  852. */
  853. int __init eeh_ops_register(struct eeh_ops *ops)
  854. {
  855. if (!ops->name) {
  856. pr_warn("%s: Invalid EEH ops name for %p\n",
  857. __func__, ops);
  858. return -EINVAL;
  859. }
  860. if (eeh_ops && eeh_ops != ops) {
  861. pr_warn("%s: EEH ops of platform %s already existing (%s)\n",
  862. __func__, eeh_ops->name, ops->name);
  863. return -EEXIST;
  864. }
  865. eeh_ops = ops;
  866. return 0;
  867. }
  868. /**
  869. * eeh_ops_unregister - Unreigster platform dependent EEH operations
  870. * @name: name of EEH platform operations
  871. *
  872. * Unregister the platform dependent EEH operation callback
  873. * functions.
  874. */
  875. int __exit eeh_ops_unregister(const char *name)
  876. {
  877. if (!name || !strlen(name)) {
  878. pr_warn("%s: Invalid EEH ops name\n",
  879. __func__);
  880. return -EINVAL;
  881. }
  882. if (eeh_ops && !strcmp(eeh_ops->name, name)) {
  883. eeh_ops = NULL;
  884. return 0;
  885. }
  886. return -EEXIST;
  887. }
  888. static int eeh_reboot_notifier(struct notifier_block *nb,
  889. unsigned long action, void *unused)
  890. {
  891. eeh_clear_flag(EEH_ENABLED);
  892. return NOTIFY_DONE;
  893. }
  894. static struct notifier_block eeh_reboot_nb = {
  895. .notifier_call = eeh_reboot_notifier,
  896. };
  897. void eeh_probe_devices(void)
  898. {
  899. struct pci_controller *hose, *tmp;
  900. struct pci_dn *pdn;
  901. /* Enable EEH for all adapters */
  902. list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
  903. pdn = hose->pci_data;
  904. traverse_pci_dn(pdn, eeh_ops->probe, NULL);
  905. }
  906. }
  907. /**
  908. * eeh_init - EEH initialization
  909. *
  910. * Initialize EEH by trying to enable it for all of the adapters in the system.
  911. * As a side effect we can determine here if eeh is supported at all.
  912. * Note that we leave EEH on so failed config cycles won't cause a machine
  913. * check. If a user turns off EEH for a particular adapter they are really
  914. * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't
  915. * grant access to a slot if EEH isn't enabled, and so we always enable
  916. * EEH for all slots/all devices.
  917. *
  918. * The eeh-force-off option disables EEH checking globally, for all slots.
  919. * Even if force-off is set, the EEH hardware is still enabled, so that
  920. * newer systems can boot.
  921. */
  922. static int eeh_init(void)
  923. {
  924. struct pci_controller *hose, *tmp;
  925. int ret = 0;
  926. /* Register reboot notifier */
  927. ret = register_reboot_notifier(&eeh_reboot_nb);
  928. if (ret) {
  929. pr_warn("%s: Failed to register notifier (%d)\n",
  930. __func__, ret);
  931. return ret;
  932. }
  933. /* call platform initialization function */
  934. if (!eeh_ops) {
  935. pr_warn("%s: Platform EEH operation not found\n",
  936. __func__);
  937. return -EEXIST;
  938. } else if ((ret = eeh_ops->init()))
  939. return ret;
  940. /* Initialize PHB PEs */
  941. list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  942. eeh_dev_phb_init_dynamic(hose);
  943. /* Initialize EEH event */
  944. ret = eeh_event_init();
  945. if (ret)
  946. return ret;
  947. eeh_probe_devices();
  948. if (eeh_enabled())
  949. pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n");
  950. else if (!eeh_has_flag(EEH_POSTPONED_PROBE))
  951. pr_info("EEH: No capable adapters found\n");
  952. return ret;
  953. }
  954. core_initcall_sync(eeh_init);
  955. /**
  956. * eeh_add_device_early - Enable EEH for the indicated device node
  957. * @pdn: PCI device node for which to set up EEH
  958. *
  959. * This routine must be used to perform EEH initialization for PCI
  960. * devices that were added after system boot (e.g. hotplug, dlpar).
  961. * This routine must be called before any i/o is performed to the
  962. * adapter (inluding any config-space i/o).
  963. * Whether this actually enables EEH or not for this device depends
  964. * on the CEC architecture, type of the device, on earlier boot
  965. * command-line arguments & etc.
  966. */
  967. void eeh_add_device_early(struct pci_dn *pdn)
  968. {
  969. struct pci_controller *phb = pdn ? pdn->phb : NULL;
  970. struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
  971. if (!edev)
  972. return;
  973. if (!eeh_has_flag(EEH_PROBE_MODE_DEVTREE))
  974. return;
  975. /* USB Bus children of PCI devices will not have BUID's */
  976. if (NULL == phb ||
  977. (eeh_has_flag(EEH_PROBE_MODE_DEVTREE) && 0 == phb->buid))
  978. return;
  979. eeh_ops->probe(pdn, NULL);
  980. }
  981. /**
  982. * eeh_add_device_tree_early - Enable EEH for the indicated device
  983. * @pdn: PCI device node
  984. *
  985. * This routine must be used to perform EEH initialization for the
  986. * indicated PCI device that was added after system boot (e.g.
  987. * hotplug, dlpar).
  988. */
  989. void eeh_add_device_tree_early(struct pci_dn *pdn)
  990. {
  991. struct pci_dn *n;
  992. if (!pdn)
  993. return;
  994. list_for_each_entry(n, &pdn->child_list, list)
  995. eeh_add_device_tree_early(n);
  996. eeh_add_device_early(pdn);
  997. }
  998. EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
  999. /**
  1000. * eeh_add_device_late - Perform EEH initialization for the indicated pci device
  1001. * @dev: pci device for which to set up EEH
  1002. *
  1003. * This routine must be used to complete EEH initialization for PCI
  1004. * devices that were added after system boot (e.g. hotplug, dlpar).
  1005. */
  1006. void eeh_add_device_late(struct pci_dev *dev)
  1007. {
  1008. struct pci_dn *pdn;
  1009. struct eeh_dev *edev;
  1010. if (!dev || !eeh_enabled())
  1011. return;
  1012. pr_debug("EEH: Adding device %s\n", pci_name(dev));
  1013. pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
  1014. edev = pdn_to_eeh_dev(pdn);
  1015. if (edev->pdev == dev) {
  1016. pr_debug("EEH: Already referenced !\n");
  1017. return;
  1018. }
  1019. /*
  1020. * The EEH cache might not be removed correctly because of
  1021. * unbalanced kref to the device during unplug time, which
  1022. * relies on pcibios_release_device(). So we have to remove
  1023. * that here explicitly.
  1024. */
  1025. if (edev->pdev) {
  1026. eeh_rmv_from_parent_pe(edev);
  1027. eeh_addr_cache_rmv_dev(edev->pdev);
  1028. eeh_sysfs_remove_device(edev->pdev);
  1029. edev->mode &= ~EEH_DEV_SYSFS;
  1030. /*
  1031. * We definitely should have the PCI device removed
  1032. * though it wasn't correctly. So we needn't call
  1033. * into error handler afterwards.
  1034. */
  1035. edev->mode |= EEH_DEV_NO_HANDLER;
  1036. edev->pdev = NULL;
  1037. dev->dev.archdata.edev = NULL;
  1038. }
  1039. if (eeh_has_flag(EEH_PROBE_MODE_DEV))
  1040. eeh_ops->probe(pdn, NULL);
  1041. edev->pdev = dev;
  1042. dev->dev.archdata.edev = edev;
  1043. eeh_addr_cache_insert_dev(dev);
  1044. }
  1045. /**
  1046. * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus
  1047. * @bus: PCI bus
  1048. *
  1049. * This routine must be used to perform EEH initialization for PCI
  1050. * devices which are attached to the indicated PCI bus. The PCI bus
  1051. * is added after system boot through hotplug or dlpar.
  1052. */
  1053. void eeh_add_device_tree_late(struct pci_bus *bus)
  1054. {
  1055. struct pci_dev *dev;
  1056. list_for_each_entry(dev, &bus->devices, bus_list) {
  1057. eeh_add_device_late(dev);
  1058. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  1059. struct pci_bus *subbus = dev->subordinate;
  1060. if (subbus)
  1061. eeh_add_device_tree_late(subbus);
  1062. }
  1063. }
  1064. }
  1065. EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
  1066. /**
  1067. * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus
  1068. * @bus: PCI bus
  1069. *
  1070. * This routine must be used to add EEH sysfs files for PCI
  1071. * devices which are attached to the indicated PCI bus. The PCI bus
  1072. * is added after system boot through hotplug or dlpar.
  1073. */
  1074. void eeh_add_sysfs_files(struct pci_bus *bus)
  1075. {
  1076. struct pci_dev *dev;
  1077. list_for_each_entry(dev, &bus->devices, bus_list) {
  1078. eeh_sysfs_add_device(dev);
  1079. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  1080. struct pci_bus *subbus = dev->subordinate;
  1081. if (subbus)
  1082. eeh_add_sysfs_files(subbus);
  1083. }
  1084. }
  1085. }
  1086. EXPORT_SYMBOL_GPL(eeh_add_sysfs_files);
  1087. /**
  1088. * eeh_remove_device - Undo EEH setup for the indicated pci device
  1089. * @dev: pci device to be removed
  1090. *
  1091. * This routine should be called when a device is removed from
  1092. * a running system (e.g. by hotplug or dlpar). It unregisters
  1093. * the PCI device from the EEH subsystem. I/O errors affecting
  1094. * this device will no longer be detected after this call; thus,
  1095. * i/o errors affecting this slot may leave this device unusable.
  1096. */
  1097. void eeh_remove_device(struct pci_dev *dev)
  1098. {
  1099. struct eeh_dev *edev;
  1100. if (!dev || !eeh_enabled())
  1101. return;
  1102. edev = pci_dev_to_eeh_dev(dev);
  1103. /* Unregister the device with the EEH/PCI address search system */
  1104. pr_debug("EEH: Removing device %s\n", pci_name(dev));
  1105. if (!edev || !edev->pdev || !edev->pe) {
  1106. pr_debug("EEH: Not referenced !\n");
  1107. return;
  1108. }
  1109. /*
  1110. * During the hotplug for EEH error recovery, we need the EEH
  1111. * device attached to the parent PE in order for BAR restore
  1112. * a bit later. So we keep it for BAR restore and remove it
  1113. * from the parent PE during the BAR resotre.
  1114. */
  1115. edev->pdev = NULL;
  1116. /*
  1117. * The flag "in_error" is used to trace EEH devices for VFs
  1118. * in error state or not. It's set in eeh_report_error(). If
  1119. * it's not set, eeh_report_{reset,resume}() won't be called
  1120. * for the VF EEH device.
  1121. */
  1122. edev->in_error = false;
  1123. dev->dev.archdata.edev = NULL;
  1124. if (!(edev->pe->state & EEH_PE_KEEP))
  1125. eeh_rmv_from_parent_pe(edev);
  1126. else
  1127. edev->mode |= EEH_DEV_DISCONNECTED;
  1128. /*
  1129. * We're removing from the PCI subsystem, that means
  1130. * the PCI device driver can't support EEH or not
  1131. * well. So we rely on hotplug completely to do recovery
  1132. * for the specific PCI device.
  1133. */
  1134. edev->mode |= EEH_DEV_NO_HANDLER;
  1135. eeh_addr_cache_rmv_dev(dev);
  1136. eeh_sysfs_remove_device(dev);
  1137. edev->mode &= ~EEH_DEV_SYSFS;
  1138. }
  1139. int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state)
  1140. {
  1141. int ret;
  1142. ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
  1143. if (ret) {
  1144. pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n",
  1145. __func__, ret, pe->phb->global_number, pe->addr);
  1146. return ret;
  1147. }
  1148. ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
  1149. if (ret) {
  1150. pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n",
  1151. __func__, ret, pe->phb->global_number, pe->addr);
  1152. return ret;
  1153. }
  1154. /* Clear software isolated state */
  1155. if (sw_state && (pe->state & EEH_PE_ISOLATED))
  1156. eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
  1157. return ret;
  1158. }
  1159. static struct pci_device_id eeh_reset_ids[] = {
  1160. { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */
  1161. { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */
  1162. { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */
  1163. { 0 }
  1164. };
  1165. static int eeh_pe_change_owner(struct eeh_pe *pe)
  1166. {
  1167. struct eeh_dev *edev, *tmp;
  1168. struct pci_dev *pdev;
  1169. struct pci_device_id *id;
  1170. int ret;
  1171. /* Check PE state */
  1172. ret = eeh_ops->get_state(pe, NULL);
  1173. if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT)
  1174. return 0;
  1175. /* Unfrozen PE, nothing to do */
  1176. if (eeh_state_active(ret))
  1177. return 0;
  1178. /* Frozen PE, check if it needs PE level reset */
  1179. eeh_pe_for_each_dev(pe, edev, tmp) {
  1180. pdev = eeh_dev_to_pci_dev(edev);
  1181. if (!pdev)
  1182. continue;
  1183. for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) {
  1184. if (id->vendor != PCI_ANY_ID &&
  1185. id->vendor != pdev->vendor)
  1186. continue;
  1187. if (id->device != PCI_ANY_ID &&
  1188. id->device != pdev->device)
  1189. continue;
  1190. if (id->subvendor != PCI_ANY_ID &&
  1191. id->subvendor != pdev->subsystem_vendor)
  1192. continue;
  1193. if (id->subdevice != PCI_ANY_ID &&
  1194. id->subdevice != pdev->subsystem_device)
  1195. continue;
  1196. return eeh_pe_reset_and_recover(pe);
  1197. }
  1198. }
  1199. return eeh_unfreeze_pe(pe, true);
  1200. }
  1201. /**
  1202. * eeh_dev_open - Increase count of pass through devices for PE
  1203. * @pdev: PCI device
  1204. *
  1205. * Increase count of passed through devices for the indicated
  1206. * PE. In the result, the EEH errors detected on the PE won't be
  1207. * reported. The PE owner will be responsible for detection
  1208. * and recovery.
  1209. */
  1210. int eeh_dev_open(struct pci_dev *pdev)
  1211. {
  1212. struct eeh_dev *edev;
  1213. int ret = -ENODEV;
  1214. mutex_lock(&eeh_dev_mutex);
  1215. /* No PCI device ? */
  1216. if (!pdev)
  1217. goto out;
  1218. /* No EEH device or PE ? */
  1219. edev = pci_dev_to_eeh_dev(pdev);
  1220. if (!edev || !edev->pe)
  1221. goto out;
  1222. /*
  1223. * The PE might have been put into frozen state, but we
  1224. * didn't detect that yet. The passed through PCI devices
  1225. * in frozen PE won't work properly. Clear the frozen state
  1226. * in advance.
  1227. */
  1228. ret = eeh_pe_change_owner(edev->pe);
  1229. if (ret)
  1230. goto out;
  1231. /* Increase PE's pass through count */
  1232. atomic_inc(&edev->pe->pass_dev_cnt);
  1233. mutex_unlock(&eeh_dev_mutex);
  1234. return 0;
  1235. out:
  1236. mutex_unlock(&eeh_dev_mutex);
  1237. return ret;
  1238. }
  1239. EXPORT_SYMBOL_GPL(eeh_dev_open);
  1240. /**
  1241. * eeh_dev_release - Decrease count of pass through devices for PE
  1242. * @pdev: PCI device
  1243. *
  1244. * Decrease count of pass through devices for the indicated PE. If
  1245. * there is no passed through device in PE, the EEH errors detected
  1246. * on the PE will be reported and handled as usual.
  1247. */
  1248. void eeh_dev_release(struct pci_dev *pdev)
  1249. {
  1250. struct eeh_dev *edev;
  1251. mutex_lock(&eeh_dev_mutex);
  1252. /* No PCI device ? */
  1253. if (!pdev)
  1254. goto out;
  1255. /* No EEH device ? */
  1256. edev = pci_dev_to_eeh_dev(pdev);
  1257. if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))
  1258. goto out;
  1259. /* Decrease PE's pass through count */
  1260. WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);
  1261. eeh_pe_change_owner(edev->pe);
  1262. out:
  1263. mutex_unlock(&eeh_dev_mutex);
  1264. }
  1265. EXPORT_SYMBOL(eeh_dev_release);
  1266. #ifdef CONFIG_IOMMU_API
  1267. static int dev_has_iommu_table(struct device *dev, void *data)
  1268. {
  1269. struct pci_dev *pdev = to_pci_dev(dev);
  1270. struct pci_dev **ppdev = data;
  1271. if (!dev)
  1272. return 0;
  1273. if (dev->iommu_group) {
  1274. *ppdev = pdev;
  1275. return 1;
  1276. }
  1277. return 0;
  1278. }
  1279. /**
  1280. * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE
  1281. * @group: IOMMU group
  1282. *
  1283. * The routine is called to convert IOMMU group to EEH PE.
  1284. */
  1285. struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group)
  1286. {
  1287. struct pci_dev *pdev = NULL;
  1288. struct eeh_dev *edev;
  1289. int ret;
  1290. /* No IOMMU group ? */
  1291. if (!group)
  1292. return NULL;
  1293. ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table);
  1294. if (!ret || !pdev)
  1295. return NULL;
  1296. /* No EEH device or PE ? */
  1297. edev = pci_dev_to_eeh_dev(pdev);
  1298. if (!edev || !edev->pe)
  1299. return NULL;
  1300. return edev->pe;
  1301. }
  1302. EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe);
  1303. #endif /* CONFIG_IOMMU_API */
  1304. /**
  1305. * eeh_pe_set_option - Set options for the indicated PE
  1306. * @pe: EEH PE
  1307. * @option: requested option
  1308. *
  1309. * The routine is called to enable or disable EEH functionality
  1310. * on the indicated PE, to enable IO or DMA for the frozen PE.
  1311. */
  1312. int eeh_pe_set_option(struct eeh_pe *pe, int option)
  1313. {
  1314. int ret = 0;
  1315. /* Invalid PE ? */
  1316. if (!pe)
  1317. return -ENODEV;
  1318. /*
  1319. * EEH functionality could possibly be disabled, just
  1320. * return error for the case. And the EEH functinality
  1321. * isn't expected to be disabled on one specific PE.
  1322. */
  1323. switch (option) {
  1324. case EEH_OPT_ENABLE:
  1325. if (eeh_enabled()) {
  1326. ret = eeh_pe_change_owner(pe);
  1327. break;
  1328. }
  1329. ret = -EIO;
  1330. break;
  1331. case EEH_OPT_DISABLE:
  1332. break;
  1333. case EEH_OPT_THAW_MMIO:
  1334. case EEH_OPT_THAW_DMA:
  1335. case EEH_OPT_FREEZE_PE:
  1336. if (!eeh_ops || !eeh_ops->set_option) {
  1337. ret = -ENOENT;
  1338. break;
  1339. }
  1340. ret = eeh_pci_enable(pe, option);
  1341. break;
  1342. default:
  1343. pr_debug("%s: Option %d out of range (%d, %d)\n",
  1344. __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA);
  1345. ret = -EINVAL;
  1346. }
  1347. return ret;
  1348. }
  1349. EXPORT_SYMBOL_GPL(eeh_pe_set_option);
  1350. /**
  1351. * eeh_pe_get_state - Retrieve PE's state
  1352. * @pe: EEH PE
  1353. *
  1354. * Retrieve the PE's state, which includes 3 aspects: enabled
  1355. * DMA, enabled IO and asserted reset.
  1356. */
  1357. int eeh_pe_get_state(struct eeh_pe *pe)
  1358. {
  1359. int result, ret = 0;
  1360. bool rst_active, dma_en, mmio_en;
  1361. /* Existing PE ? */
  1362. if (!pe)
  1363. return -ENODEV;
  1364. if (!eeh_ops || !eeh_ops->get_state)
  1365. return -ENOENT;
  1366. /*
  1367. * If the parent PE is owned by the host kernel and is undergoing
  1368. * error recovery, we should return the PE state as temporarily
  1369. * unavailable so that the error recovery on the guest is suspended
  1370. * until the recovery completes on the host.
  1371. */
  1372. if (pe->parent &&
  1373. !(pe->state & EEH_PE_REMOVED) &&
  1374. (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))
  1375. return EEH_PE_STATE_UNAVAIL;
  1376. result = eeh_ops->get_state(pe, NULL);
  1377. rst_active = !!(result & EEH_STATE_RESET_ACTIVE);
  1378. dma_en = !!(result & EEH_STATE_DMA_ENABLED);
  1379. mmio_en = !!(result & EEH_STATE_MMIO_ENABLED);
  1380. if (rst_active)
  1381. ret = EEH_PE_STATE_RESET;
  1382. else if (dma_en && mmio_en)
  1383. ret = EEH_PE_STATE_NORMAL;
  1384. else if (!dma_en && !mmio_en)
  1385. ret = EEH_PE_STATE_STOPPED_IO_DMA;
  1386. else if (!dma_en && mmio_en)
  1387. ret = EEH_PE_STATE_STOPPED_DMA;
  1388. else
  1389. ret = EEH_PE_STATE_UNAVAIL;
  1390. return ret;
  1391. }
  1392. EXPORT_SYMBOL_GPL(eeh_pe_get_state);
  1393. static int eeh_pe_reenable_devices(struct eeh_pe *pe)
  1394. {
  1395. struct eeh_dev *edev, *tmp;
  1396. struct pci_dev *pdev;
  1397. int ret = 0;
  1398. /* Restore config space */
  1399. eeh_pe_restore_bars(pe);
  1400. /*
  1401. * Reenable PCI devices as the devices passed
  1402. * through are always enabled before the reset.
  1403. */
  1404. eeh_pe_for_each_dev(pe, edev, tmp) {
  1405. pdev = eeh_dev_to_pci_dev(edev);
  1406. if (!pdev)
  1407. continue;
  1408. ret = pci_reenable_device(pdev);
  1409. if (ret) {
  1410. pr_warn("%s: Failure %d reenabling %s\n",
  1411. __func__, ret, pci_name(pdev));
  1412. return ret;
  1413. }
  1414. }
  1415. /* The PE is still in frozen state */
  1416. return eeh_unfreeze_pe(pe, true);
  1417. }
  1418. /**
  1419. * eeh_pe_reset - Issue PE reset according to specified type
  1420. * @pe: EEH PE
  1421. * @option: reset type
  1422. *
  1423. * The routine is called to reset the specified PE with the
  1424. * indicated type, either fundamental reset or hot reset.
  1425. * PE reset is the most important part for error recovery.
  1426. */
  1427. int eeh_pe_reset(struct eeh_pe *pe, int option)
  1428. {
  1429. int ret = 0;
  1430. /* Invalid PE ? */
  1431. if (!pe)
  1432. return -ENODEV;
  1433. if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
  1434. return -ENOENT;
  1435. switch (option) {
  1436. case EEH_RESET_DEACTIVATE:
  1437. ret = eeh_ops->reset(pe, option);
  1438. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
  1439. if (ret)
  1440. break;
  1441. ret = eeh_pe_reenable_devices(pe);
  1442. break;
  1443. case EEH_RESET_HOT:
  1444. case EEH_RESET_FUNDAMENTAL:
  1445. /*
  1446. * Proactively freeze the PE to drop all MMIO access
  1447. * during reset, which should be banned as it's always
  1448. * cause recursive EEH error.
  1449. */
  1450. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  1451. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  1452. ret = eeh_ops->reset(pe, option);
  1453. break;
  1454. default:
  1455. pr_debug("%s: Unsupported option %d\n",
  1456. __func__, option);
  1457. ret = -EINVAL;
  1458. }
  1459. return ret;
  1460. }
  1461. EXPORT_SYMBOL_GPL(eeh_pe_reset);
  1462. /**
  1463. * eeh_pe_configure - Configure PCI bridges after PE reset
  1464. * @pe: EEH PE
  1465. *
  1466. * The routine is called to restore the PCI config space for
  1467. * those PCI devices, especially PCI bridges affected by PE
  1468. * reset issued previously.
  1469. */
  1470. int eeh_pe_configure(struct eeh_pe *pe)
  1471. {
  1472. int ret = 0;
  1473. /* Invalid PE ? */
  1474. if (!pe)
  1475. return -ENODEV;
  1476. return ret;
  1477. }
  1478. EXPORT_SYMBOL_GPL(eeh_pe_configure);
  1479. /**
  1480. * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE
  1481. * @pe: the indicated PE
  1482. * @type: error type
  1483. * @function: error function
  1484. * @addr: address
  1485. * @mask: address mask
  1486. *
  1487. * The routine is called to inject the specified PCI error, which
  1488. * is determined by @type and @function, to the indicated PE for
  1489. * testing purpose.
  1490. */
  1491. int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
  1492. unsigned long addr, unsigned long mask)
  1493. {
  1494. /* Invalid PE ? */
  1495. if (!pe)
  1496. return -ENODEV;
  1497. /* Unsupported operation ? */
  1498. if (!eeh_ops || !eeh_ops->err_inject)
  1499. return -ENOENT;
  1500. /* Check on PCI error type */
  1501. if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64)
  1502. return -EINVAL;
  1503. /* Check on PCI error function */
  1504. if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX)
  1505. return -EINVAL;
  1506. return eeh_ops->err_inject(pe, type, func, addr, mask);
  1507. }
  1508. EXPORT_SYMBOL_GPL(eeh_pe_inject_err);
  1509. static int proc_eeh_show(struct seq_file *m, void *v)
  1510. {
  1511. if (!eeh_enabled()) {
  1512. seq_printf(m, "EEH Subsystem is globally disabled\n");
  1513. seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
  1514. } else {
  1515. seq_printf(m, "EEH Subsystem is enabled\n");
  1516. seq_printf(m,
  1517. "no device=%llu\n"
  1518. "no device node=%llu\n"
  1519. "no config address=%llu\n"
  1520. "check not wanted=%llu\n"
  1521. "eeh_total_mmio_ffs=%llu\n"
  1522. "eeh_false_positives=%llu\n"
  1523. "eeh_slot_resets=%llu\n",
  1524. eeh_stats.no_device,
  1525. eeh_stats.no_dn,
  1526. eeh_stats.no_cfg_addr,
  1527. eeh_stats.ignored_check,
  1528. eeh_stats.total_mmio_ffs,
  1529. eeh_stats.false_positives,
  1530. eeh_stats.slot_resets);
  1531. }
  1532. return 0;
  1533. }
  1534. #ifdef CONFIG_DEBUG_FS
  1535. static int eeh_enable_dbgfs_set(void *data, u64 val)
  1536. {
  1537. if (val)
  1538. eeh_clear_flag(EEH_FORCE_DISABLED);
  1539. else
  1540. eeh_add_flag(EEH_FORCE_DISABLED);
  1541. return 0;
  1542. }
  1543. static int eeh_enable_dbgfs_get(void *data, u64 *val)
  1544. {
  1545. if (eeh_enabled())
  1546. *val = 0x1ul;
  1547. else
  1548. *val = 0x0ul;
  1549. return 0;
  1550. }
  1551. static int eeh_freeze_dbgfs_set(void *data, u64 val)
  1552. {
  1553. eeh_max_freezes = val;
  1554. return 0;
  1555. }
  1556. static int eeh_freeze_dbgfs_get(void *data, u64 *val)
  1557. {
  1558. *val = eeh_max_freezes;
  1559. return 0;
  1560. }
  1561. DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
  1562. eeh_enable_dbgfs_set, "0x%llx\n");
  1563. DEFINE_SIMPLE_ATTRIBUTE(eeh_freeze_dbgfs_ops, eeh_freeze_dbgfs_get,
  1564. eeh_freeze_dbgfs_set, "0x%llx\n");
  1565. #endif
  1566. static int __init eeh_init_proc(void)
  1567. {
  1568. if (machine_is(pseries) || machine_is(powernv)) {
  1569. proc_create_single("powerpc/eeh", 0, NULL, proc_eeh_show);
  1570. #ifdef CONFIG_DEBUG_FS
  1571. debugfs_create_file("eeh_enable", 0600,
  1572. powerpc_debugfs_root, NULL,
  1573. &eeh_enable_dbgfs_ops);
  1574. debugfs_create_file("eeh_max_freezes", 0600,
  1575. powerpc_debugfs_root, NULL,
  1576. &eeh_freeze_dbgfs_ops);
  1577. #endif
  1578. }
  1579. return 0;
  1580. }
  1581. __initcall(eeh_init_proc);