rtas_pci.c 6.0 KB

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  1. /*
  2. * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
  3. * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
  4. *
  5. * RTAS specific routines for PCI.
  6. *
  7. * Based on code from pci.c, chrp_pci.c and pSeries_pci.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/threads.h>
  25. #include <linux/pci.h>
  26. #include <linux/string.h>
  27. #include <linux/init.h>
  28. #include <asm/io.h>
  29. #include <asm/pgtable.h>
  30. #include <asm/irq.h>
  31. #include <asm/prom.h>
  32. #include <asm/machdep.h>
  33. #include <asm/pci-bridge.h>
  34. #include <asm/iommu.h>
  35. #include <asm/rtas.h>
  36. #include <asm/mpic.h>
  37. #include <asm/ppc-pci.h>
  38. #include <asm/eeh.h>
  39. /* RTAS tokens */
  40. static int read_pci_config;
  41. static int write_pci_config;
  42. static int ibm_read_pci_config;
  43. static int ibm_write_pci_config;
  44. static inline int config_access_valid(struct pci_dn *dn, int where)
  45. {
  46. if (where < 256)
  47. return 1;
  48. if (where < 4096 && dn->pci_ext_config_space)
  49. return 1;
  50. return 0;
  51. }
  52. int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
  53. {
  54. int returnval = -1;
  55. unsigned long buid, addr;
  56. int ret;
  57. if (!pdn)
  58. return PCIBIOS_DEVICE_NOT_FOUND;
  59. if (!config_access_valid(pdn, where))
  60. return PCIBIOS_BAD_REGISTER_NUMBER;
  61. #ifdef CONFIG_EEH
  62. if (pdn->edev && pdn->edev->pe &&
  63. (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
  64. return PCIBIOS_SET_FAILED;
  65. #endif
  66. addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
  67. buid = pdn->phb->buid;
  68. if (buid) {
  69. ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
  70. addr, BUID_HI(buid), BUID_LO(buid), size);
  71. } else {
  72. ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
  73. }
  74. *val = returnval;
  75. if (ret)
  76. return PCIBIOS_DEVICE_NOT_FOUND;
  77. return PCIBIOS_SUCCESSFUL;
  78. }
  79. static int rtas_pci_read_config(struct pci_bus *bus,
  80. unsigned int devfn,
  81. int where, int size, u32 *val)
  82. {
  83. struct pci_dn *pdn;
  84. int ret;
  85. *val = 0xFFFFFFFF;
  86. pdn = pci_get_pdn_by_devfn(bus, devfn);
  87. /* Validity of pdn is checked in here */
  88. ret = rtas_read_config(pdn, where, size, val);
  89. if (*val == EEH_IO_ERROR_VALUE(size) &&
  90. eeh_dev_check_failure(pdn_to_eeh_dev(pdn)))
  91. return PCIBIOS_DEVICE_NOT_FOUND;
  92. return ret;
  93. }
  94. int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
  95. {
  96. unsigned long buid, addr;
  97. int ret;
  98. if (!pdn)
  99. return PCIBIOS_DEVICE_NOT_FOUND;
  100. if (!config_access_valid(pdn, where))
  101. return PCIBIOS_BAD_REGISTER_NUMBER;
  102. #ifdef CONFIG_EEH
  103. if (pdn->edev && pdn->edev->pe &&
  104. (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
  105. return PCIBIOS_SET_FAILED;
  106. #endif
  107. addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
  108. buid = pdn->phb->buid;
  109. if (buid) {
  110. ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
  111. BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
  112. } else {
  113. ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
  114. }
  115. if (ret)
  116. return PCIBIOS_DEVICE_NOT_FOUND;
  117. return PCIBIOS_SUCCESSFUL;
  118. }
  119. static int rtas_pci_write_config(struct pci_bus *bus,
  120. unsigned int devfn,
  121. int where, int size, u32 val)
  122. {
  123. struct pci_dn *pdn;
  124. pdn = pci_get_pdn_by_devfn(bus, devfn);
  125. /* Validity of pdn is checked in here. */
  126. return rtas_write_config(pdn, where, size, val);
  127. }
  128. static struct pci_ops rtas_pci_ops = {
  129. .read = rtas_pci_read_config,
  130. .write = rtas_pci_write_config,
  131. };
  132. static int is_python(struct device_node *dev)
  133. {
  134. const char *model = of_get_property(dev, "model", NULL);
  135. if (model && strstr(model, "Python"))
  136. return 1;
  137. return 0;
  138. }
  139. static void python_countermeasures(struct device_node *dev)
  140. {
  141. struct resource registers;
  142. void __iomem *chip_regs;
  143. volatile u32 val;
  144. if (of_address_to_resource(dev, 0, &registers)) {
  145. printk(KERN_ERR "Can't get address for Python workarounds !\n");
  146. return;
  147. }
  148. /* Python's register file is 1 MB in size. */
  149. chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);
  150. /*
  151. * Firmware doesn't always clear this bit which is critical
  152. * for good performance - Anton
  153. */
  154. #define PRG_CL_RESET_VALID 0x00010000
  155. val = in_be32(chip_regs + 0xf6030);
  156. if (val & PRG_CL_RESET_VALID) {
  157. printk(KERN_INFO "Python workaround: ");
  158. val &= ~PRG_CL_RESET_VALID;
  159. out_be32(chip_regs + 0xf6030, val);
  160. /*
  161. * We must read it back for changes to
  162. * take effect
  163. */
  164. val = in_be32(chip_regs + 0xf6030);
  165. printk("reg0: %x\n", val);
  166. }
  167. iounmap(chip_regs);
  168. }
  169. void __init init_pci_config_tokens(void)
  170. {
  171. read_pci_config = rtas_token("read-pci-config");
  172. write_pci_config = rtas_token("write-pci-config");
  173. ibm_read_pci_config = rtas_token("ibm,read-pci-config");
  174. ibm_write_pci_config = rtas_token("ibm,write-pci-config");
  175. }
  176. unsigned long get_phb_buid(struct device_node *phb)
  177. {
  178. struct resource r;
  179. if (ibm_read_pci_config == -1)
  180. return 0;
  181. if (of_address_to_resource(phb, 0, &r))
  182. return 0;
  183. return r.start;
  184. }
  185. static int phb_set_bus_ranges(struct device_node *dev,
  186. struct pci_controller *phb)
  187. {
  188. const __be32 *bus_range;
  189. unsigned int len;
  190. bus_range = of_get_property(dev, "bus-range", &len);
  191. if (bus_range == NULL || len < 2 * sizeof(int)) {
  192. return 1;
  193. }
  194. phb->first_busno = be32_to_cpu(bus_range[0]);
  195. phb->last_busno = be32_to_cpu(bus_range[1]);
  196. return 0;
  197. }
  198. int rtas_setup_phb(struct pci_controller *phb)
  199. {
  200. struct device_node *dev = phb->dn;
  201. if (is_python(dev))
  202. python_countermeasures(dev);
  203. if (phb_set_bus_ranges(dev, phb))
  204. return 1;
  205. phb->ops = &rtas_pci_ops;
  206. phb->buid = get_phb_buid(dev);
  207. return 0;
  208. }