cpm1.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * General Purpose functions for the global management of the
  4. * Communication Processor Module.
  5. * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
  6. *
  7. * In addition to the individual control of the communication
  8. * channels, there are a few functions that globally affect the
  9. * communication processor.
  10. *
  11. * Buffer descriptors must be allocated from the dual ported memory
  12. * space. The allocator for that is here. When the communication
  13. * process is reset, we reclaim the memory available. There is
  14. * currently no deallocator for this memory.
  15. * The amount of space available is platform dependent. On the
  16. * MBX, the EPPC software loads additional microcode into the
  17. * communication processor, and uses some of the DP ram for this
  18. * purpose. Current, the first 512 bytes and the last 256 bytes of
  19. * memory are used. Right now I am conservative and only use the
  20. * memory that can never be used for microcode. If there are
  21. * applications that require more DP ram, we can expand the boundaries
  22. * but then we have to be careful of any downloaded microcode.
  23. */
  24. #include <linux/errno.h>
  25. #include <linux/sched.h>
  26. #include <linux/kernel.h>
  27. #include <linux/dma-mapping.h>
  28. #include <linux/param.h>
  29. #include <linux/string.h>
  30. #include <linux/mm.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/irq.h>
  33. #include <linux/module.h>
  34. #include <linux/spinlock.h>
  35. #include <linux/slab.h>
  36. #include <asm/page.h>
  37. #include <asm/pgtable.h>
  38. #include <asm/8xx_immap.h>
  39. #include <asm/cpm1.h>
  40. #include <asm/io.h>
  41. #include <asm/rheap.h>
  42. #include <asm/prom.h>
  43. #include <asm/cpm.h>
  44. #include <asm/fs_pd.h>
  45. #ifdef CONFIG_8xx_GPIO
  46. #include <linux/of_gpio.h>
  47. #endif
  48. #define CPM_MAP_SIZE (0x4000)
  49. cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */
  50. immap_t __iomem *mpc8xx_immr;
  51. static cpic8xx_t __iomem *cpic_reg;
  52. static struct irq_domain *cpm_pic_host;
  53. static void cpm_mask_irq(struct irq_data *d)
  54. {
  55. unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
  56. clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  57. }
  58. static void cpm_unmask_irq(struct irq_data *d)
  59. {
  60. unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
  61. setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  62. }
  63. static void cpm_end_irq(struct irq_data *d)
  64. {
  65. unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
  66. out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
  67. }
  68. static struct irq_chip cpm_pic = {
  69. .name = "CPM PIC",
  70. .irq_mask = cpm_mask_irq,
  71. .irq_unmask = cpm_unmask_irq,
  72. .irq_eoi = cpm_end_irq,
  73. };
  74. int cpm_get_irq(void)
  75. {
  76. int cpm_vec;
  77. /* Get the vector by setting the ACK bit and then reading
  78. * the register.
  79. */
  80. out_be16(&cpic_reg->cpic_civr, 1);
  81. cpm_vec = in_be16(&cpic_reg->cpic_civr);
  82. cpm_vec >>= 11;
  83. return irq_linear_revmap(cpm_pic_host, cpm_vec);
  84. }
  85. static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq,
  86. irq_hw_number_t hw)
  87. {
  88. pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
  89. irq_set_status_flags(virq, IRQ_LEVEL);
  90. irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
  91. return 0;
  92. }
  93. /* The CPM can generate the error interrupt when there is a race condition
  94. * between generating and masking interrupts. All we have to do is ACK it
  95. * and return. This is a no-op function so we don't need any special
  96. * tests in the interrupt handler.
  97. */
  98. static irqreturn_t cpm_error_interrupt(int irq, void *dev)
  99. {
  100. return IRQ_HANDLED;
  101. }
  102. static struct irqaction cpm_error_irqaction = {
  103. .handler = cpm_error_interrupt,
  104. .flags = IRQF_NO_THREAD,
  105. .name = "error",
  106. };
  107. static const struct irq_domain_ops cpm_pic_host_ops = {
  108. .map = cpm_pic_host_map,
  109. };
  110. unsigned int cpm_pic_init(void)
  111. {
  112. struct device_node *np = NULL;
  113. struct resource res;
  114. unsigned int sirq = 0, hwirq, eirq;
  115. int ret;
  116. pr_debug("cpm_pic_init\n");
  117. np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
  118. if (np == NULL)
  119. np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
  120. if (np == NULL) {
  121. printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
  122. return sirq;
  123. }
  124. ret = of_address_to_resource(np, 0, &res);
  125. if (ret)
  126. goto end;
  127. cpic_reg = ioremap(res.start, resource_size(&res));
  128. if (cpic_reg == NULL)
  129. goto end;
  130. sirq = irq_of_parse_and_map(np, 0);
  131. if (!sirq)
  132. goto end;
  133. /* Initialize the CPM interrupt controller. */
  134. hwirq = (unsigned int)virq_to_hw(sirq);
  135. out_be32(&cpic_reg->cpic_cicr,
  136. (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
  137. ((hwirq/2) << 13) | CICR_HP_MASK);
  138. out_be32(&cpic_reg->cpic_cimr, 0);
  139. cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL);
  140. if (cpm_pic_host == NULL) {
  141. printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
  142. sirq = 0;
  143. goto end;
  144. }
  145. /* Install our own error handler. */
  146. np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
  147. if (np == NULL)
  148. np = of_find_node_by_type(NULL, "cpm");
  149. if (np == NULL) {
  150. printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
  151. goto end;
  152. }
  153. eirq = irq_of_parse_and_map(np, 0);
  154. if (!eirq)
  155. goto end;
  156. if (setup_irq(eirq, &cpm_error_irqaction))
  157. printk(KERN_ERR "Could not allocate CPM error IRQ!");
  158. setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
  159. end:
  160. of_node_put(np);
  161. return sirq;
  162. }
  163. void __init cpm_reset(void)
  164. {
  165. sysconf8xx_t __iomem *siu_conf;
  166. mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
  167. if (!mpc8xx_immr) {
  168. printk(KERN_CRIT "Could not map IMMR\n");
  169. return;
  170. }
  171. cpmp = &mpc8xx_immr->im_cpm;
  172. #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
  173. /* Perform a reset.
  174. */
  175. out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
  176. /* Wait for it.
  177. */
  178. while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
  179. #endif
  180. #ifdef CONFIG_UCODE_PATCH
  181. cpm_load_patch(cpmp);
  182. #endif
  183. /* Set SDMA Bus Request priority 5.
  184. * On 860T, this also enables FEC priority 6. I am not sure
  185. * this is what we really want for some applications, but the
  186. * manual recommends it.
  187. * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
  188. */
  189. siu_conf = immr_map(im_siu_conf);
  190. if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
  191. out_be32(&siu_conf->sc_sdcr, 0x40);
  192. else
  193. out_be32(&siu_conf->sc_sdcr, 1);
  194. immr_unmap(siu_conf);
  195. }
  196. static DEFINE_SPINLOCK(cmd_lock);
  197. #define MAX_CR_CMD_LOOPS 10000
  198. int cpm_command(u32 command, u8 opcode)
  199. {
  200. int i, ret;
  201. unsigned long flags;
  202. if (command & 0xffffff0f)
  203. return -EINVAL;
  204. spin_lock_irqsave(&cmd_lock, flags);
  205. ret = 0;
  206. out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
  207. for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
  208. if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
  209. goto out;
  210. printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
  211. ret = -EIO;
  212. out:
  213. spin_unlock_irqrestore(&cmd_lock, flags);
  214. return ret;
  215. }
  216. EXPORT_SYMBOL(cpm_command);
  217. /* Set a baud rate generator. This needs lots of work. There are
  218. * four BRGs, any of which can be wired to any channel.
  219. * The internal baud rate clock is the system clock divided by 16.
  220. * This assumes the baudrate is 16x oversampled by the uart.
  221. */
  222. #define BRG_INT_CLK (get_brgfreq())
  223. #define BRG_UART_CLK (BRG_INT_CLK/16)
  224. #define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
  225. void
  226. cpm_setbrg(uint brg, uint rate)
  227. {
  228. u32 __iomem *bp;
  229. /* This is good enough to get SMCs running.....
  230. */
  231. bp = &cpmp->cp_brgc1;
  232. bp += brg;
  233. /* The BRG has a 12-bit counter. For really slow baud rates (or
  234. * really fast processors), we may have to further divide by 16.
  235. */
  236. if (((BRG_UART_CLK / rate) - 1) < 4096)
  237. out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
  238. else
  239. out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
  240. CPM_BRG_EN | CPM_BRG_DIV16);
  241. }
  242. struct cpm_ioport16 {
  243. __be16 dir, par, odr_sor, dat, intr;
  244. __be16 res[3];
  245. };
  246. struct cpm_ioport32b {
  247. __be32 dir, par, odr, dat;
  248. };
  249. struct cpm_ioport32e {
  250. __be32 dir, par, sor, odr, dat;
  251. };
  252. static void cpm1_set_pin32(int port, int pin, int flags)
  253. {
  254. struct cpm_ioport32e __iomem *iop;
  255. pin = 1 << (31 - pin);
  256. if (port == CPM_PORTB)
  257. iop = (struct cpm_ioport32e __iomem *)
  258. &mpc8xx_immr->im_cpm.cp_pbdir;
  259. else
  260. iop = (struct cpm_ioport32e __iomem *)
  261. &mpc8xx_immr->im_cpm.cp_pedir;
  262. if (flags & CPM_PIN_OUTPUT)
  263. setbits32(&iop->dir, pin);
  264. else
  265. clrbits32(&iop->dir, pin);
  266. if (!(flags & CPM_PIN_GPIO))
  267. setbits32(&iop->par, pin);
  268. else
  269. clrbits32(&iop->par, pin);
  270. if (port == CPM_PORTB) {
  271. if (flags & CPM_PIN_OPENDRAIN)
  272. setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
  273. else
  274. clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
  275. }
  276. if (port == CPM_PORTE) {
  277. if (flags & CPM_PIN_SECONDARY)
  278. setbits32(&iop->sor, pin);
  279. else
  280. clrbits32(&iop->sor, pin);
  281. if (flags & CPM_PIN_OPENDRAIN)
  282. setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
  283. else
  284. clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
  285. }
  286. }
  287. static void cpm1_set_pin16(int port, int pin, int flags)
  288. {
  289. struct cpm_ioport16 __iomem *iop =
  290. (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
  291. pin = 1 << (15 - pin);
  292. if (port != 0)
  293. iop += port - 1;
  294. if (flags & CPM_PIN_OUTPUT)
  295. setbits16(&iop->dir, pin);
  296. else
  297. clrbits16(&iop->dir, pin);
  298. if (!(flags & CPM_PIN_GPIO))
  299. setbits16(&iop->par, pin);
  300. else
  301. clrbits16(&iop->par, pin);
  302. if (port == CPM_PORTA) {
  303. if (flags & CPM_PIN_OPENDRAIN)
  304. setbits16(&iop->odr_sor, pin);
  305. else
  306. clrbits16(&iop->odr_sor, pin);
  307. }
  308. if (port == CPM_PORTC) {
  309. if (flags & CPM_PIN_SECONDARY)
  310. setbits16(&iop->odr_sor, pin);
  311. else
  312. clrbits16(&iop->odr_sor, pin);
  313. if (flags & CPM_PIN_FALLEDGE)
  314. setbits16(&iop->intr, pin);
  315. else
  316. clrbits16(&iop->intr, pin);
  317. }
  318. }
  319. void cpm1_set_pin(enum cpm_port port, int pin, int flags)
  320. {
  321. if (port == CPM_PORTB || port == CPM_PORTE)
  322. cpm1_set_pin32(port, pin, flags);
  323. else
  324. cpm1_set_pin16(port, pin, flags);
  325. }
  326. int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
  327. {
  328. int shift;
  329. int i, bits = 0;
  330. u32 __iomem *reg;
  331. u32 mask = 7;
  332. u8 clk_map[][3] = {
  333. {CPM_CLK_SCC1, CPM_BRG1, 0},
  334. {CPM_CLK_SCC1, CPM_BRG2, 1},
  335. {CPM_CLK_SCC1, CPM_BRG3, 2},
  336. {CPM_CLK_SCC1, CPM_BRG4, 3},
  337. {CPM_CLK_SCC1, CPM_CLK1, 4},
  338. {CPM_CLK_SCC1, CPM_CLK2, 5},
  339. {CPM_CLK_SCC1, CPM_CLK3, 6},
  340. {CPM_CLK_SCC1, CPM_CLK4, 7},
  341. {CPM_CLK_SCC2, CPM_BRG1, 0},
  342. {CPM_CLK_SCC2, CPM_BRG2, 1},
  343. {CPM_CLK_SCC2, CPM_BRG3, 2},
  344. {CPM_CLK_SCC2, CPM_BRG4, 3},
  345. {CPM_CLK_SCC2, CPM_CLK1, 4},
  346. {CPM_CLK_SCC2, CPM_CLK2, 5},
  347. {CPM_CLK_SCC2, CPM_CLK3, 6},
  348. {CPM_CLK_SCC2, CPM_CLK4, 7},
  349. {CPM_CLK_SCC3, CPM_BRG1, 0},
  350. {CPM_CLK_SCC3, CPM_BRG2, 1},
  351. {CPM_CLK_SCC3, CPM_BRG3, 2},
  352. {CPM_CLK_SCC3, CPM_BRG4, 3},
  353. {CPM_CLK_SCC3, CPM_CLK5, 4},
  354. {CPM_CLK_SCC3, CPM_CLK6, 5},
  355. {CPM_CLK_SCC3, CPM_CLK7, 6},
  356. {CPM_CLK_SCC3, CPM_CLK8, 7},
  357. {CPM_CLK_SCC4, CPM_BRG1, 0},
  358. {CPM_CLK_SCC4, CPM_BRG2, 1},
  359. {CPM_CLK_SCC4, CPM_BRG3, 2},
  360. {CPM_CLK_SCC4, CPM_BRG4, 3},
  361. {CPM_CLK_SCC4, CPM_CLK5, 4},
  362. {CPM_CLK_SCC4, CPM_CLK6, 5},
  363. {CPM_CLK_SCC4, CPM_CLK7, 6},
  364. {CPM_CLK_SCC4, CPM_CLK8, 7},
  365. {CPM_CLK_SMC1, CPM_BRG1, 0},
  366. {CPM_CLK_SMC1, CPM_BRG2, 1},
  367. {CPM_CLK_SMC1, CPM_BRG3, 2},
  368. {CPM_CLK_SMC1, CPM_BRG4, 3},
  369. {CPM_CLK_SMC1, CPM_CLK1, 4},
  370. {CPM_CLK_SMC1, CPM_CLK2, 5},
  371. {CPM_CLK_SMC1, CPM_CLK3, 6},
  372. {CPM_CLK_SMC1, CPM_CLK4, 7},
  373. {CPM_CLK_SMC2, CPM_BRG1, 0},
  374. {CPM_CLK_SMC2, CPM_BRG2, 1},
  375. {CPM_CLK_SMC2, CPM_BRG3, 2},
  376. {CPM_CLK_SMC2, CPM_BRG4, 3},
  377. {CPM_CLK_SMC2, CPM_CLK5, 4},
  378. {CPM_CLK_SMC2, CPM_CLK6, 5},
  379. {CPM_CLK_SMC2, CPM_CLK7, 6},
  380. {CPM_CLK_SMC2, CPM_CLK8, 7},
  381. };
  382. switch (target) {
  383. case CPM_CLK_SCC1:
  384. reg = &mpc8xx_immr->im_cpm.cp_sicr;
  385. shift = 0;
  386. break;
  387. case CPM_CLK_SCC2:
  388. reg = &mpc8xx_immr->im_cpm.cp_sicr;
  389. shift = 8;
  390. break;
  391. case CPM_CLK_SCC3:
  392. reg = &mpc8xx_immr->im_cpm.cp_sicr;
  393. shift = 16;
  394. break;
  395. case CPM_CLK_SCC4:
  396. reg = &mpc8xx_immr->im_cpm.cp_sicr;
  397. shift = 24;
  398. break;
  399. case CPM_CLK_SMC1:
  400. reg = &mpc8xx_immr->im_cpm.cp_simode;
  401. shift = 12;
  402. break;
  403. case CPM_CLK_SMC2:
  404. reg = &mpc8xx_immr->im_cpm.cp_simode;
  405. shift = 28;
  406. break;
  407. default:
  408. printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
  409. return -EINVAL;
  410. }
  411. for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
  412. if (clk_map[i][0] == target && clk_map[i][1] == clock) {
  413. bits = clk_map[i][2];
  414. break;
  415. }
  416. }
  417. if (i == ARRAY_SIZE(clk_map)) {
  418. printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
  419. return -EINVAL;
  420. }
  421. bits <<= shift;
  422. mask <<= shift;
  423. if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
  424. if (mode == CPM_CLK_RTX) {
  425. bits |= bits << 3;
  426. mask |= mask << 3;
  427. } else if (mode == CPM_CLK_RX) {
  428. bits <<= 3;
  429. mask <<= 3;
  430. }
  431. }
  432. out_be32(reg, (in_be32(reg) & ~mask) | bits);
  433. return 0;
  434. }
  435. /*
  436. * GPIO LIB API implementation
  437. */
  438. #ifdef CONFIG_8xx_GPIO
  439. struct cpm1_gpio16_chip {
  440. struct of_mm_gpio_chip mm_gc;
  441. spinlock_t lock;
  442. /* shadowed data register to clear/set bits safely */
  443. u16 cpdata;
  444. /* IRQ associated with Pins when relevant */
  445. int irq[16];
  446. };
  447. static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
  448. {
  449. struct cpm1_gpio16_chip *cpm1_gc =
  450. container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
  451. struct cpm_ioport16 __iomem *iop = mm_gc->regs;
  452. cpm1_gc->cpdata = in_be16(&iop->dat);
  453. }
  454. static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
  455. {
  456. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  457. struct cpm_ioport16 __iomem *iop = mm_gc->regs;
  458. u16 pin_mask;
  459. pin_mask = 1 << (15 - gpio);
  460. return !!(in_be16(&iop->dat) & pin_mask);
  461. }
  462. static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
  463. int value)
  464. {
  465. struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
  466. struct cpm_ioport16 __iomem *iop = mm_gc->regs;
  467. if (value)
  468. cpm1_gc->cpdata |= pin_mask;
  469. else
  470. cpm1_gc->cpdata &= ~pin_mask;
  471. out_be16(&iop->dat, cpm1_gc->cpdata);
  472. }
  473. static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
  474. {
  475. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  476. struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
  477. unsigned long flags;
  478. u16 pin_mask = 1 << (15 - gpio);
  479. spin_lock_irqsave(&cpm1_gc->lock, flags);
  480. __cpm1_gpio16_set(mm_gc, pin_mask, value);
  481. spin_unlock_irqrestore(&cpm1_gc->lock, flags);
  482. }
  483. static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
  484. {
  485. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  486. struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
  487. return cpm1_gc->irq[gpio] ? : -ENXIO;
  488. }
  489. static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
  490. {
  491. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  492. struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
  493. struct cpm_ioport16 __iomem *iop = mm_gc->regs;
  494. unsigned long flags;
  495. u16 pin_mask = 1 << (15 - gpio);
  496. spin_lock_irqsave(&cpm1_gc->lock, flags);
  497. setbits16(&iop->dir, pin_mask);
  498. __cpm1_gpio16_set(mm_gc, pin_mask, val);
  499. spin_unlock_irqrestore(&cpm1_gc->lock, flags);
  500. return 0;
  501. }
  502. static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
  503. {
  504. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  505. struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
  506. struct cpm_ioport16 __iomem *iop = mm_gc->regs;
  507. unsigned long flags;
  508. u16 pin_mask = 1 << (15 - gpio);
  509. spin_lock_irqsave(&cpm1_gc->lock, flags);
  510. clrbits16(&iop->dir, pin_mask);
  511. spin_unlock_irqrestore(&cpm1_gc->lock, flags);
  512. return 0;
  513. }
  514. int cpm1_gpiochip_add16(struct device *dev)
  515. {
  516. struct device_node *np = dev->of_node;
  517. struct cpm1_gpio16_chip *cpm1_gc;
  518. struct of_mm_gpio_chip *mm_gc;
  519. struct gpio_chip *gc;
  520. u16 mask;
  521. cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
  522. if (!cpm1_gc)
  523. return -ENOMEM;
  524. spin_lock_init(&cpm1_gc->lock);
  525. if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
  526. int i, j;
  527. for (i = 0, j = 0; i < 16; i++)
  528. if (mask & (1 << (15 - i)))
  529. cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
  530. }
  531. mm_gc = &cpm1_gc->mm_gc;
  532. gc = &mm_gc->gc;
  533. mm_gc->save_regs = cpm1_gpio16_save_regs;
  534. gc->ngpio = 16;
  535. gc->direction_input = cpm1_gpio16_dir_in;
  536. gc->direction_output = cpm1_gpio16_dir_out;
  537. gc->get = cpm1_gpio16_get;
  538. gc->set = cpm1_gpio16_set;
  539. gc->to_irq = cpm1_gpio16_to_irq;
  540. gc->parent = dev;
  541. gc->owner = THIS_MODULE;
  542. return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
  543. }
  544. struct cpm1_gpio32_chip {
  545. struct of_mm_gpio_chip mm_gc;
  546. spinlock_t lock;
  547. /* shadowed data register to clear/set bits safely */
  548. u32 cpdata;
  549. };
  550. static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
  551. {
  552. struct cpm1_gpio32_chip *cpm1_gc =
  553. container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
  554. struct cpm_ioport32b __iomem *iop = mm_gc->regs;
  555. cpm1_gc->cpdata = in_be32(&iop->dat);
  556. }
  557. static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
  558. {
  559. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  560. struct cpm_ioport32b __iomem *iop = mm_gc->regs;
  561. u32 pin_mask;
  562. pin_mask = 1 << (31 - gpio);
  563. return !!(in_be32(&iop->dat) & pin_mask);
  564. }
  565. static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
  566. int value)
  567. {
  568. struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
  569. struct cpm_ioport32b __iomem *iop = mm_gc->regs;
  570. if (value)
  571. cpm1_gc->cpdata |= pin_mask;
  572. else
  573. cpm1_gc->cpdata &= ~pin_mask;
  574. out_be32(&iop->dat, cpm1_gc->cpdata);
  575. }
  576. static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
  577. {
  578. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  579. struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
  580. unsigned long flags;
  581. u32 pin_mask = 1 << (31 - gpio);
  582. spin_lock_irqsave(&cpm1_gc->lock, flags);
  583. __cpm1_gpio32_set(mm_gc, pin_mask, value);
  584. spin_unlock_irqrestore(&cpm1_gc->lock, flags);
  585. }
  586. static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
  587. {
  588. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  589. struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
  590. struct cpm_ioport32b __iomem *iop = mm_gc->regs;
  591. unsigned long flags;
  592. u32 pin_mask = 1 << (31 - gpio);
  593. spin_lock_irqsave(&cpm1_gc->lock, flags);
  594. setbits32(&iop->dir, pin_mask);
  595. __cpm1_gpio32_set(mm_gc, pin_mask, val);
  596. spin_unlock_irqrestore(&cpm1_gc->lock, flags);
  597. return 0;
  598. }
  599. static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
  600. {
  601. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  602. struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
  603. struct cpm_ioport32b __iomem *iop = mm_gc->regs;
  604. unsigned long flags;
  605. u32 pin_mask = 1 << (31 - gpio);
  606. spin_lock_irqsave(&cpm1_gc->lock, flags);
  607. clrbits32(&iop->dir, pin_mask);
  608. spin_unlock_irqrestore(&cpm1_gc->lock, flags);
  609. return 0;
  610. }
  611. int cpm1_gpiochip_add32(struct device *dev)
  612. {
  613. struct device_node *np = dev->of_node;
  614. struct cpm1_gpio32_chip *cpm1_gc;
  615. struct of_mm_gpio_chip *mm_gc;
  616. struct gpio_chip *gc;
  617. cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
  618. if (!cpm1_gc)
  619. return -ENOMEM;
  620. spin_lock_init(&cpm1_gc->lock);
  621. mm_gc = &cpm1_gc->mm_gc;
  622. gc = &mm_gc->gc;
  623. mm_gc->save_regs = cpm1_gpio32_save_regs;
  624. gc->ngpio = 32;
  625. gc->direction_input = cpm1_gpio32_dir_in;
  626. gc->direction_output = cpm1_gpio32_dir_out;
  627. gc->get = cpm1_gpio32_get;
  628. gc->set = cpm1_gpio32_set;
  629. gc->parent = dev;
  630. gc->owner = THIS_MODULE;
  631. return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
  632. }
  633. #endif /* CONFIG_8xx_GPIO */