devicetree.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Architecture specific OF callbacks.
  4. */
  5. #include <linux/export.h>
  6. #include <linux/io.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/list.h>
  9. #include <linux/of.h>
  10. #include <linux/of_fdt.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/libfdt.h>
  15. #include <linux/slab.h>
  16. #include <linux/pci.h>
  17. #include <linux/of_pci.h>
  18. #include <linux/initrd.h>
  19. #include <asm/irqdomain.h>
  20. #include <asm/hpet.h>
  21. #include <asm/apic.h>
  22. #include <asm/pci_x86.h>
  23. #include <asm/setup.h>
  24. #include <asm/i8259.h>
  25. __initdata u64 initial_dtb;
  26. char __initdata cmd_line[COMMAND_LINE_SIZE];
  27. int __initdata of_ioapic;
  28. void __init early_init_dt_scan_chosen_arch(unsigned long node)
  29. {
  30. BUG();
  31. }
  32. void __init early_init_dt_add_memory_arch(u64 base, u64 size)
  33. {
  34. BUG();
  35. }
  36. void __init add_dtb(u64 data)
  37. {
  38. initial_dtb = data + offsetof(struct setup_data, data);
  39. }
  40. /*
  41. * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
  42. */
  43. static struct of_device_id __initdata ce4100_ids[] = {
  44. { .compatible = "intel,ce4100-cp", },
  45. { .compatible = "isa", },
  46. { .compatible = "pci", },
  47. {},
  48. };
  49. static int __init add_bus_probe(void)
  50. {
  51. if (!of_have_populated_dt())
  52. return 0;
  53. return of_platform_bus_probe(NULL, ce4100_ids, NULL);
  54. }
  55. device_initcall(add_bus_probe);
  56. #ifdef CONFIG_PCI
  57. struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
  58. {
  59. struct device_node *np;
  60. for_each_node_by_type(np, "pci") {
  61. const void *prop;
  62. unsigned int bus_min;
  63. prop = of_get_property(np, "bus-range", NULL);
  64. if (!prop)
  65. continue;
  66. bus_min = be32_to_cpup(prop);
  67. if (bus->number == bus_min)
  68. return np;
  69. }
  70. return NULL;
  71. }
  72. static int x86_of_pci_irq_enable(struct pci_dev *dev)
  73. {
  74. u32 virq;
  75. int ret;
  76. u8 pin;
  77. ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
  78. if (ret)
  79. return ret;
  80. if (!pin)
  81. return 0;
  82. virq = of_irq_parse_and_map_pci(dev, 0, 0);
  83. if (virq == 0)
  84. return -EINVAL;
  85. dev->irq = virq;
  86. return 0;
  87. }
  88. static void x86_of_pci_irq_disable(struct pci_dev *dev)
  89. {
  90. }
  91. void x86_of_pci_init(void)
  92. {
  93. pcibios_enable_irq = x86_of_pci_irq_enable;
  94. pcibios_disable_irq = x86_of_pci_irq_disable;
  95. }
  96. #endif
  97. static void __init dtb_setup_hpet(void)
  98. {
  99. #ifdef CONFIG_HPET_TIMER
  100. struct device_node *dn;
  101. struct resource r;
  102. int ret;
  103. dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
  104. if (!dn)
  105. return;
  106. ret = of_address_to_resource(dn, 0, &r);
  107. if (ret) {
  108. WARN_ON(1);
  109. return;
  110. }
  111. hpet_address = r.start;
  112. #endif
  113. }
  114. #ifdef CONFIG_X86_LOCAL_APIC
  115. static void __init dtb_cpu_setup(void)
  116. {
  117. struct device_node *dn;
  118. u32 apic_id, version;
  119. int ret;
  120. version = GET_APIC_VERSION(apic_read(APIC_LVR));
  121. for_each_node_by_type(dn, "cpu") {
  122. ret = of_property_read_u32(dn, "reg", &apic_id);
  123. if (ret < 0) {
  124. pr_warn("%pOF: missing local APIC ID\n", dn);
  125. continue;
  126. }
  127. generic_processor_info(apic_id, version);
  128. }
  129. }
  130. static void __init dtb_lapic_setup(void)
  131. {
  132. struct device_node *dn;
  133. struct resource r;
  134. unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
  135. int ret;
  136. dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
  137. if (dn) {
  138. ret = of_address_to_resource(dn, 0, &r);
  139. if (WARN_ON(ret))
  140. return;
  141. lapic_addr = r.start;
  142. }
  143. /* Did the boot loader setup the local APIC ? */
  144. if (!boot_cpu_has(X86_FEATURE_APIC)) {
  145. if (apic_force_enable(lapic_addr))
  146. return;
  147. }
  148. smp_found_config = 1;
  149. pic_mode = 1;
  150. register_lapic_address(lapic_addr);
  151. }
  152. #endif /* CONFIG_X86_LOCAL_APIC */
  153. #ifdef CONFIG_X86_IO_APIC
  154. static unsigned int ioapic_id;
  155. struct of_ioapic_type {
  156. u32 out_type;
  157. u32 trigger;
  158. u32 polarity;
  159. };
  160. static struct of_ioapic_type of_ioapic_type[] =
  161. {
  162. {
  163. .out_type = IRQ_TYPE_EDGE_RISING,
  164. .trigger = IOAPIC_EDGE,
  165. .polarity = 1,
  166. },
  167. {
  168. .out_type = IRQ_TYPE_LEVEL_LOW,
  169. .trigger = IOAPIC_LEVEL,
  170. .polarity = 0,
  171. },
  172. {
  173. .out_type = IRQ_TYPE_LEVEL_HIGH,
  174. .trigger = IOAPIC_LEVEL,
  175. .polarity = 1,
  176. },
  177. {
  178. .out_type = IRQ_TYPE_EDGE_FALLING,
  179. .trigger = IOAPIC_EDGE,
  180. .polarity = 0,
  181. },
  182. };
  183. static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
  184. unsigned int nr_irqs, void *arg)
  185. {
  186. struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
  187. struct of_ioapic_type *it;
  188. struct irq_alloc_info tmp;
  189. int type_index;
  190. if (WARN_ON(fwspec->param_count < 2))
  191. return -EINVAL;
  192. type_index = fwspec->param[1];
  193. if (type_index >= ARRAY_SIZE(of_ioapic_type))
  194. return -EINVAL;
  195. it = &of_ioapic_type[type_index];
  196. ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
  197. tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
  198. tmp.ioapic_pin = fwspec->param[0];
  199. return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
  200. }
  201. static const struct irq_domain_ops ioapic_irq_domain_ops = {
  202. .alloc = dt_irqdomain_alloc,
  203. .free = mp_irqdomain_free,
  204. .activate = mp_irqdomain_activate,
  205. .deactivate = mp_irqdomain_deactivate,
  206. };
  207. static void __init dtb_add_ioapic(struct device_node *dn)
  208. {
  209. struct resource r;
  210. int ret;
  211. struct ioapic_domain_cfg cfg = {
  212. .type = IOAPIC_DOMAIN_DYNAMIC,
  213. .ops = &ioapic_irq_domain_ops,
  214. .dev = dn,
  215. };
  216. ret = of_address_to_resource(dn, 0, &r);
  217. if (ret) {
  218. printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn);
  219. return;
  220. }
  221. mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
  222. }
  223. static void __init dtb_ioapic_setup(void)
  224. {
  225. struct device_node *dn;
  226. for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
  227. dtb_add_ioapic(dn);
  228. if (nr_ioapics) {
  229. of_ioapic = 1;
  230. return;
  231. }
  232. printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
  233. }
  234. #else
  235. static void __init dtb_ioapic_setup(void) {}
  236. #endif
  237. static void __init dtb_apic_setup(void)
  238. {
  239. #ifdef CONFIG_X86_LOCAL_APIC
  240. dtb_lapic_setup();
  241. dtb_cpu_setup();
  242. #endif
  243. dtb_ioapic_setup();
  244. }
  245. #ifdef CONFIG_OF_EARLY_FLATTREE
  246. static void __init x86_flattree_get_config(void)
  247. {
  248. u32 size, map_len;
  249. void *dt;
  250. if (!initial_dtb)
  251. return;
  252. map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
  253. dt = early_memremap(initial_dtb, map_len);
  254. size = fdt_totalsize(dt);
  255. if (map_len < size) {
  256. early_memunmap(dt, map_len);
  257. dt = early_memremap(initial_dtb, size);
  258. map_len = size;
  259. }
  260. early_init_dt_verify(dt);
  261. unflatten_and_copy_device_tree();
  262. early_memunmap(dt, map_len);
  263. }
  264. #else
  265. static inline void x86_flattree_get_config(void) { }
  266. #endif
  267. void __init x86_dtb_init(void)
  268. {
  269. x86_flattree_get_config();
  270. if (!of_have_populated_dt())
  271. return;
  272. dtb_setup_hpet();
  273. dtb_apic_setup();
  274. }