smpboot.c 41 KB

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  1. /*
  2. * x86 SMP booting functions
  3. *
  4. * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
  5. * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
  6. * Copyright 2001 Andi Kleen, SuSE Labs.
  7. *
  8. * Much of the core SMP work is based on previous work by Thomas Radke, to
  9. * whom a great many thanks are extended.
  10. *
  11. * Thanks to Intel for making available several different Pentium,
  12. * Pentium Pro and Pentium-II/Xeon MP machines.
  13. * Original development of Linux SMP code supported by Caldera.
  14. *
  15. * This code is released under the GNU General Public License version 2 or
  16. * later.
  17. *
  18. * Fixes
  19. * Felix Koop : NR_CPUS used properly
  20. * Jose Renau : Handle single CPU case.
  21. * Alan Cox : By repeated request 8) - Total BogoMIPS report.
  22. * Greg Wright : Fix for kernel stacks panic.
  23. * Erich Boleyn : MP v1.4 and additional changes.
  24. * Matthias Sattler : Changes for 2.1 kernel map.
  25. * Michel Lespinasse : Changes for 2.1 kernel map.
  26. * Michael Chastain : Change trampoline.S to gnu as.
  27. * Alan Cox : Dumb bug: 'B' step PPro's are fine
  28. * Ingo Molnar : Added APIC timers, based on code
  29. * from Jose Renau
  30. * Ingo Molnar : various cleanups and rewrites
  31. * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
  32. * Maciej W. Rozycki : Bits for genuine 82489DX APICs
  33. * Andi Kleen : Changed for SMP boot into long mode.
  34. * Martin J. Bligh : Added support for multi-quad systems
  35. * Dave Jones : Report invalid combinations of Athlon CPUs.
  36. * Rusty Russell : Hacked into shape for new "hotplug" boot process.
  37. * Andi Kleen : Converted to new state machine.
  38. * Ashok Raj : CPU hotplug support
  39. * Glauber Costa : i386 and x86_64 integration
  40. */
  41. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  42. #include <linux/init.h>
  43. #include <linux/smp.h>
  44. #include <linux/export.h>
  45. #include <linux/sched.h>
  46. #include <linux/sched/topology.h>
  47. #include <linux/sched/hotplug.h>
  48. #include <linux/sched/task_stack.h>
  49. #include <linux/percpu.h>
  50. #include <linux/bootmem.h>
  51. #include <linux/err.h>
  52. #include <linux/nmi.h>
  53. #include <linux/tboot.h>
  54. #include <linux/stackprotector.h>
  55. #include <linux/gfp.h>
  56. #include <linux/cpuidle.h>
  57. #include <asm/acpi.h>
  58. #include <asm/desc.h>
  59. #include <asm/nmi.h>
  60. #include <asm/irq.h>
  61. #include <asm/realmode.h>
  62. #include <asm/cpu.h>
  63. #include <asm/numa.h>
  64. #include <asm/pgtable.h>
  65. #include <asm/tlbflush.h>
  66. #include <asm/mtrr.h>
  67. #include <asm/mwait.h>
  68. #include <asm/apic.h>
  69. #include <asm/io_apic.h>
  70. #include <asm/fpu/internal.h>
  71. #include <asm/setup.h>
  72. #include <asm/uv/uv.h>
  73. #include <linux/mc146818rtc.h>
  74. #include <asm/i8259.h>
  75. #include <asm/misc.h>
  76. #include <asm/qspinlock.h>
  77. #include <asm/intel-family.h>
  78. #include <asm/cpu_device_id.h>
  79. #include <asm/spec-ctrl.h>
  80. #include <asm/hw_irq.h>
  81. /* representing HT siblings of each logical CPU */
  82. DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
  83. EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  84. /* representing HT and core siblings of each logical CPU */
  85. DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
  86. EXPORT_PER_CPU_SYMBOL(cpu_core_map);
  87. DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
  88. /* Per CPU bogomips and other parameters */
  89. DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
  90. EXPORT_PER_CPU_SYMBOL(cpu_info);
  91. /* Logical package management. We might want to allocate that dynamically */
  92. unsigned int __max_logical_packages __read_mostly;
  93. EXPORT_SYMBOL(__max_logical_packages);
  94. static unsigned int logical_packages __read_mostly;
  95. /* Maximum number of SMT threads on any online core */
  96. int __read_mostly __max_smt_threads = 1;
  97. /* Flag to indicate if a complete sched domain rebuild is required */
  98. bool x86_topology_update;
  99. int arch_update_cpu_topology(void)
  100. {
  101. int retval = x86_topology_update;
  102. x86_topology_update = false;
  103. return retval;
  104. }
  105. static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
  106. {
  107. unsigned long flags;
  108. spin_lock_irqsave(&rtc_lock, flags);
  109. CMOS_WRITE(0xa, 0xf);
  110. spin_unlock_irqrestore(&rtc_lock, flags);
  111. *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
  112. start_eip >> 4;
  113. *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
  114. start_eip & 0xf;
  115. }
  116. static inline void smpboot_restore_warm_reset_vector(void)
  117. {
  118. unsigned long flags;
  119. /*
  120. * Paranoid: Set warm reset code and vector here back
  121. * to default values.
  122. */
  123. spin_lock_irqsave(&rtc_lock, flags);
  124. CMOS_WRITE(0, 0xf);
  125. spin_unlock_irqrestore(&rtc_lock, flags);
  126. *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
  127. }
  128. /*
  129. * Report back to the Boot Processor during boot time or to the caller processor
  130. * during CPU online.
  131. */
  132. static void smp_callin(void)
  133. {
  134. int cpuid, phys_id;
  135. /*
  136. * If waken up by an INIT in an 82489DX configuration
  137. * cpu_callout_mask guarantees we don't get here before
  138. * an INIT_deassert IPI reaches our local APIC, so it is
  139. * now safe to touch our local APIC.
  140. */
  141. cpuid = smp_processor_id();
  142. /*
  143. * (This works even if the APIC is not enabled.)
  144. */
  145. phys_id = read_apic_id();
  146. /*
  147. * the boot CPU has finished the init stage and is spinning
  148. * on callin_map until we finish. We are free to set up this
  149. * CPU, first the APIC. (this is probably redundant on most
  150. * boards)
  151. */
  152. apic_ap_setup();
  153. /*
  154. * Save our processor parameters. Note: this information
  155. * is needed for clock calibration.
  156. */
  157. smp_store_cpu_info(cpuid);
  158. /*
  159. * The topology information must be up to date before
  160. * calibrate_delay() and notify_cpu_starting().
  161. */
  162. set_cpu_sibling_map(raw_smp_processor_id());
  163. /*
  164. * Get our bogomips.
  165. * Update loops_per_jiffy in cpu_data. Previous call to
  166. * smp_store_cpu_info() stored a value that is close but not as
  167. * accurate as the value just calculated.
  168. */
  169. calibrate_delay();
  170. cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
  171. pr_debug("Stack at about %p\n", &cpuid);
  172. wmb();
  173. notify_cpu_starting(cpuid);
  174. /*
  175. * Allow the master to continue.
  176. */
  177. cpumask_set_cpu(cpuid, cpu_callin_mask);
  178. }
  179. static int cpu0_logical_apicid;
  180. static int enable_start_cpu0;
  181. /*
  182. * Activate a secondary processor.
  183. */
  184. static void notrace start_secondary(void *unused)
  185. {
  186. /*
  187. * Don't put *anything* except direct CPU state initialization
  188. * before cpu_init(), SMP booting is too fragile that we want to
  189. * limit the things done here to the most necessary things.
  190. */
  191. if (boot_cpu_has(X86_FEATURE_PCID))
  192. __write_cr4(__read_cr4() | X86_CR4_PCIDE);
  193. #ifdef CONFIG_X86_32
  194. /* switch away from the initial page table */
  195. load_cr3(swapper_pg_dir);
  196. /*
  197. * Initialize the CR4 shadow before doing anything that could
  198. * try to read it.
  199. */
  200. cr4_init_shadow();
  201. __flush_tlb_all();
  202. #endif
  203. load_current_idt();
  204. cpu_init();
  205. x86_cpuinit.early_percpu_clock_init();
  206. preempt_disable();
  207. smp_callin();
  208. enable_start_cpu0 = 0;
  209. /* otherwise gcc will move up smp_processor_id before the cpu_init */
  210. barrier();
  211. /*
  212. * Check TSC synchronization with the boot CPU:
  213. */
  214. check_tsc_sync_target();
  215. speculative_store_bypass_ht_init();
  216. /*
  217. * Lock vector_lock, set CPU online and bring the vector
  218. * allocator online. Online must be set with vector_lock held
  219. * to prevent a concurrent irq setup/teardown from seeing a
  220. * half valid vector space.
  221. */
  222. lock_vector_lock();
  223. set_cpu_online(smp_processor_id(), true);
  224. lapic_online();
  225. unlock_vector_lock();
  226. cpu_set_state_online(smp_processor_id());
  227. x86_platform.nmi_init();
  228. /* enable local interrupts */
  229. local_irq_enable();
  230. /* to prevent fake stack check failure in clock setup */
  231. boot_init_stack_canary();
  232. x86_cpuinit.setup_percpu_clockev();
  233. wmb();
  234. cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
  235. /*
  236. * Prevent tail call to cpu_startup_entry() because the stack protector
  237. * guard has been changed a couple of function calls up, in
  238. * boot_init_stack_canary() and must not be checked before tail calling
  239. * another function.
  240. */
  241. prevent_tail_call_optimization();
  242. }
  243. /**
  244. * topology_is_primary_thread - Check whether CPU is the primary SMT thread
  245. * @cpu: CPU to check
  246. */
  247. bool topology_is_primary_thread(unsigned int cpu)
  248. {
  249. return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
  250. }
  251. /**
  252. * topology_smt_supported - Check whether SMT is supported by the CPUs
  253. */
  254. bool topology_smt_supported(void)
  255. {
  256. return smp_num_siblings > 1;
  257. }
  258. /**
  259. * topology_phys_to_logical_pkg - Map a physical package id to a logical
  260. *
  261. * Returns logical package id or -1 if not found
  262. */
  263. int topology_phys_to_logical_pkg(unsigned int phys_pkg)
  264. {
  265. int cpu;
  266. for_each_possible_cpu(cpu) {
  267. struct cpuinfo_x86 *c = &cpu_data(cpu);
  268. if (c->initialized && c->phys_proc_id == phys_pkg)
  269. return c->logical_proc_id;
  270. }
  271. return -1;
  272. }
  273. EXPORT_SYMBOL(topology_phys_to_logical_pkg);
  274. /**
  275. * topology_update_package_map - Update the physical to logical package map
  276. * @pkg: The physical package id as retrieved via CPUID
  277. * @cpu: The cpu for which this is updated
  278. */
  279. int topology_update_package_map(unsigned int pkg, unsigned int cpu)
  280. {
  281. int new;
  282. /* Already available somewhere? */
  283. new = topology_phys_to_logical_pkg(pkg);
  284. if (new >= 0)
  285. goto found;
  286. new = logical_packages++;
  287. if (new != pkg) {
  288. pr_info("CPU %u Converting physical %u to logical package %u\n",
  289. cpu, pkg, new);
  290. }
  291. found:
  292. cpu_data(cpu).logical_proc_id = new;
  293. return 0;
  294. }
  295. void __init smp_store_boot_cpu_info(void)
  296. {
  297. int id = 0; /* CPU 0 */
  298. struct cpuinfo_x86 *c = &cpu_data(id);
  299. *c = boot_cpu_data;
  300. c->cpu_index = id;
  301. topology_update_package_map(c->phys_proc_id, id);
  302. c->initialized = true;
  303. }
  304. /*
  305. * The bootstrap kernel entry code has set these up. Save them for
  306. * a given CPU
  307. */
  308. void smp_store_cpu_info(int id)
  309. {
  310. struct cpuinfo_x86 *c = &cpu_data(id);
  311. /* Copy boot_cpu_data only on the first bringup */
  312. if (!c->initialized)
  313. *c = boot_cpu_data;
  314. c->cpu_index = id;
  315. /*
  316. * During boot time, CPU0 has this setup already. Save the info when
  317. * bringing up AP or offlined CPU0.
  318. */
  319. identify_secondary_cpu(c);
  320. c->initialized = true;
  321. }
  322. static bool
  323. topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
  324. {
  325. int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
  326. return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
  327. }
  328. static bool
  329. topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
  330. {
  331. int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
  332. return !WARN_ONCE(!topology_same_node(c, o),
  333. "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
  334. "[node: %d != %d]. Ignoring dependency.\n",
  335. cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
  336. }
  337. #define link_mask(mfunc, c1, c2) \
  338. do { \
  339. cpumask_set_cpu((c1), mfunc(c2)); \
  340. cpumask_set_cpu((c2), mfunc(c1)); \
  341. } while (0)
  342. static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
  343. {
  344. if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
  345. int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
  346. if (c->phys_proc_id == o->phys_proc_id &&
  347. per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
  348. if (c->cpu_core_id == o->cpu_core_id)
  349. return topology_sane(c, o, "smt");
  350. if ((c->cu_id != 0xff) &&
  351. (o->cu_id != 0xff) &&
  352. (c->cu_id == o->cu_id))
  353. return topology_sane(c, o, "smt");
  354. }
  355. } else if (c->phys_proc_id == o->phys_proc_id &&
  356. c->cpu_core_id == o->cpu_core_id) {
  357. return topology_sane(c, o, "smt");
  358. }
  359. return false;
  360. }
  361. /*
  362. * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
  363. *
  364. * These are Intel CPUs that enumerate an LLC that is shared by
  365. * multiple NUMA nodes. The LLC on these systems is shared for
  366. * off-package data access but private to the NUMA node (half
  367. * of the package) for on-package access.
  368. *
  369. * CPUID (the source of the information about the LLC) can only
  370. * enumerate the cache as being shared *or* unshared, but not
  371. * this particular configuration. The CPU in this case enumerates
  372. * the cache to be shared across the entire package (spanning both
  373. * NUMA nodes).
  374. */
  375. static const struct x86_cpu_id snc_cpu[] = {
  376. { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
  377. {}
  378. };
  379. static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
  380. {
  381. int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
  382. /* Do not match if we do not have a valid APICID for cpu: */
  383. if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
  384. return false;
  385. /* Do not match if LLC id does not match: */
  386. if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
  387. return false;
  388. /*
  389. * Allow the SNC topology without warning. Return of false
  390. * means 'c' does not share the LLC of 'o'. This will be
  391. * reflected to userspace.
  392. */
  393. if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
  394. return false;
  395. return topology_sane(c, o, "llc");
  396. }
  397. /*
  398. * Unlike the other levels, we do not enforce keeping a
  399. * multicore group inside a NUMA node. If this happens, we will
  400. * discard the MC level of the topology later.
  401. */
  402. static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
  403. {
  404. if (c->phys_proc_id == o->phys_proc_id)
  405. return true;
  406. return false;
  407. }
  408. #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
  409. static inline int x86_sched_itmt_flags(void)
  410. {
  411. return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
  412. }
  413. #ifdef CONFIG_SCHED_MC
  414. static int x86_core_flags(void)
  415. {
  416. return cpu_core_flags() | x86_sched_itmt_flags();
  417. }
  418. #endif
  419. #ifdef CONFIG_SCHED_SMT
  420. static int x86_smt_flags(void)
  421. {
  422. return cpu_smt_flags() | x86_sched_itmt_flags();
  423. }
  424. #endif
  425. #endif
  426. static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
  427. #ifdef CONFIG_SCHED_SMT
  428. { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
  429. #endif
  430. #ifdef CONFIG_SCHED_MC
  431. { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
  432. #endif
  433. { NULL, },
  434. };
  435. static struct sched_domain_topology_level x86_topology[] = {
  436. #ifdef CONFIG_SCHED_SMT
  437. { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
  438. #endif
  439. #ifdef CONFIG_SCHED_MC
  440. { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
  441. #endif
  442. { cpu_cpu_mask, SD_INIT_NAME(DIE) },
  443. { NULL, },
  444. };
  445. /*
  446. * Set if a package/die has multiple NUMA nodes inside.
  447. * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
  448. * Sub-NUMA Clustering have this.
  449. */
  450. static bool x86_has_numa_in_package;
  451. void set_cpu_sibling_map(int cpu)
  452. {
  453. bool has_smt = smp_num_siblings > 1;
  454. bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
  455. struct cpuinfo_x86 *c = &cpu_data(cpu);
  456. struct cpuinfo_x86 *o;
  457. int i, threads;
  458. cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
  459. if (!has_mp) {
  460. cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
  461. cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
  462. cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
  463. c->booted_cores = 1;
  464. return;
  465. }
  466. for_each_cpu(i, cpu_sibling_setup_mask) {
  467. o = &cpu_data(i);
  468. if ((i == cpu) || (has_smt && match_smt(c, o)))
  469. link_mask(topology_sibling_cpumask, cpu, i);
  470. if ((i == cpu) || (has_mp && match_llc(c, o)))
  471. link_mask(cpu_llc_shared_mask, cpu, i);
  472. }
  473. /*
  474. * This needs a separate iteration over the cpus because we rely on all
  475. * topology_sibling_cpumask links to be set-up.
  476. */
  477. for_each_cpu(i, cpu_sibling_setup_mask) {
  478. o = &cpu_data(i);
  479. if ((i == cpu) || (has_mp && match_die(c, o))) {
  480. link_mask(topology_core_cpumask, cpu, i);
  481. /*
  482. * Does this new cpu bringup a new core?
  483. */
  484. if (cpumask_weight(
  485. topology_sibling_cpumask(cpu)) == 1) {
  486. /*
  487. * for each core in package, increment
  488. * the booted_cores for this new cpu
  489. */
  490. if (cpumask_first(
  491. topology_sibling_cpumask(i)) == i)
  492. c->booted_cores++;
  493. /*
  494. * increment the core count for all
  495. * the other cpus in this package
  496. */
  497. if (i != cpu)
  498. cpu_data(i).booted_cores++;
  499. } else if (i != cpu && !c->booted_cores)
  500. c->booted_cores = cpu_data(i).booted_cores;
  501. }
  502. if (match_die(c, o) && !topology_same_node(c, o))
  503. x86_has_numa_in_package = true;
  504. }
  505. threads = cpumask_weight(topology_sibling_cpumask(cpu));
  506. if (threads > __max_smt_threads)
  507. __max_smt_threads = threads;
  508. }
  509. /* maps the cpu to the sched domain representing multi-core */
  510. const struct cpumask *cpu_coregroup_mask(int cpu)
  511. {
  512. return cpu_llc_shared_mask(cpu);
  513. }
  514. static void impress_friends(void)
  515. {
  516. int cpu;
  517. unsigned long bogosum = 0;
  518. /*
  519. * Allow the user to impress friends.
  520. */
  521. pr_debug("Before bogomips\n");
  522. for_each_possible_cpu(cpu)
  523. if (cpumask_test_cpu(cpu, cpu_callout_mask))
  524. bogosum += cpu_data(cpu).loops_per_jiffy;
  525. pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
  526. num_online_cpus(),
  527. bogosum/(500000/HZ),
  528. (bogosum/(5000/HZ))%100);
  529. pr_debug("Before bogocount - setting activated=1\n");
  530. }
  531. void __inquire_remote_apic(int apicid)
  532. {
  533. unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
  534. const char * const names[] = { "ID", "VERSION", "SPIV" };
  535. int timeout;
  536. u32 status;
  537. pr_info("Inquiring remote APIC 0x%x...\n", apicid);
  538. for (i = 0; i < ARRAY_SIZE(regs); i++) {
  539. pr_info("... APIC 0x%x %s: ", apicid, names[i]);
  540. /*
  541. * Wait for idle.
  542. */
  543. status = safe_apic_wait_icr_idle();
  544. if (status)
  545. pr_cont("a previous APIC delivery may have failed\n");
  546. apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
  547. timeout = 0;
  548. do {
  549. udelay(100);
  550. status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
  551. } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
  552. switch (status) {
  553. case APIC_ICR_RR_VALID:
  554. status = apic_read(APIC_RRR);
  555. pr_cont("%08x\n", status);
  556. break;
  557. default:
  558. pr_cont("failed\n");
  559. }
  560. }
  561. }
  562. /*
  563. * The Multiprocessor Specification 1.4 (1997) example code suggests
  564. * that there should be a 10ms delay between the BSP asserting INIT
  565. * and de-asserting INIT, when starting a remote processor.
  566. * But that slows boot and resume on modern processors, which include
  567. * many cores and don't require that delay.
  568. *
  569. * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
  570. * Modern processor families are quirked to remove the delay entirely.
  571. */
  572. #define UDELAY_10MS_DEFAULT 10000
  573. static unsigned int init_udelay = UINT_MAX;
  574. static int __init cpu_init_udelay(char *str)
  575. {
  576. get_option(&str, &init_udelay);
  577. return 0;
  578. }
  579. early_param("cpu_init_udelay", cpu_init_udelay);
  580. static void __init smp_quirk_init_udelay(void)
  581. {
  582. /* if cmdline changed it from default, leave it alone */
  583. if (init_udelay != UINT_MAX)
  584. return;
  585. /* if modern processor, use no delay */
  586. if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
  587. ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
  588. init_udelay = 0;
  589. return;
  590. }
  591. /* else, use legacy delay */
  592. init_udelay = UDELAY_10MS_DEFAULT;
  593. }
  594. /*
  595. * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
  596. * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
  597. * won't ... remember to clear down the APIC, etc later.
  598. */
  599. int
  600. wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
  601. {
  602. unsigned long send_status, accept_status = 0;
  603. int maxlvt;
  604. /* Target chip */
  605. /* Boot on the stack */
  606. /* Kick the second */
  607. apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
  608. pr_debug("Waiting for send to finish...\n");
  609. send_status = safe_apic_wait_icr_idle();
  610. /*
  611. * Give the other CPU some time to accept the IPI.
  612. */
  613. udelay(200);
  614. if (APIC_INTEGRATED(boot_cpu_apic_version)) {
  615. maxlvt = lapic_get_maxlvt();
  616. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  617. apic_write(APIC_ESR, 0);
  618. accept_status = (apic_read(APIC_ESR) & 0xEF);
  619. }
  620. pr_debug("NMI sent\n");
  621. if (send_status)
  622. pr_err("APIC never delivered???\n");
  623. if (accept_status)
  624. pr_err("APIC delivery error (%lx)\n", accept_status);
  625. return (send_status | accept_status);
  626. }
  627. static int
  628. wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
  629. {
  630. unsigned long send_status = 0, accept_status = 0;
  631. int maxlvt, num_starts, j;
  632. maxlvt = lapic_get_maxlvt();
  633. /*
  634. * Be paranoid about clearing APIC errors.
  635. */
  636. if (APIC_INTEGRATED(boot_cpu_apic_version)) {
  637. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  638. apic_write(APIC_ESR, 0);
  639. apic_read(APIC_ESR);
  640. }
  641. pr_debug("Asserting INIT\n");
  642. /*
  643. * Turn INIT on target chip
  644. */
  645. /*
  646. * Send IPI
  647. */
  648. apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
  649. phys_apicid);
  650. pr_debug("Waiting for send to finish...\n");
  651. send_status = safe_apic_wait_icr_idle();
  652. udelay(init_udelay);
  653. pr_debug("Deasserting INIT\n");
  654. /* Target chip */
  655. /* Send IPI */
  656. apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
  657. pr_debug("Waiting for send to finish...\n");
  658. send_status = safe_apic_wait_icr_idle();
  659. mb();
  660. /*
  661. * Should we send STARTUP IPIs ?
  662. *
  663. * Determine this based on the APIC version.
  664. * If we don't have an integrated APIC, don't send the STARTUP IPIs.
  665. */
  666. if (APIC_INTEGRATED(boot_cpu_apic_version))
  667. num_starts = 2;
  668. else
  669. num_starts = 0;
  670. /*
  671. * Run STARTUP IPI loop.
  672. */
  673. pr_debug("#startup loops: %d\n", num_starts);
  674. for (j = 1; j <= num_starts; j++) {
  675. pr_debug("Sending STARTUP #%d\n", j);
  676. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  677. apic_write(APIC_ESR, 0);
  678. apic_read(APIC_ESR);
  679. pr_debug("After apic_write\n");
  680. /*
  681. * STARTUP IPI
  682. */
  683. /* Target chip */
  684. /* Boot on the stack */
  685. /* Kick the second */
  686. apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
  687. phys_apicid);
  688. /*
  689. * Give the other CPU some time to accept the IPI.
  690. */
  691. if (init_udelay == 0)
  692. udelay(10);
  693. else
  694. udelay(300);
  695. pr_debug("Startup point 1\n");
  696. pr_debug("Waiting for send to finish...\n");
  697. send_status = safe_apic_wait_icr_idle();
  698. /*
  699. * Give the other CPU some time to accept the IPI.
  700. */
  701. if (init_udelay == 0)
  702. udelay(10);
  703. else
  704. udelay(200);
  705. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  706. apic_write(APIC_ESR, 0);
  707. accept_status = (apic_read(APIC_ESR) & 0xEF);
  708. if (send_status || accept_status)
  709. break;
  710. }
  711. pr_debug("After Startup\n");
  712. if (send_status)
  713. pr_err("APIC never delivered???\n");
  714. if (accept_status)
  715. pr_err("APIC delivery error (%lx)\n", accept_status);
  716. return (send_status | accept_status);
  717. }
  718. /* reduce the number of lines printed when booting a large cpu count system */
  719. static void announce_cpu(int cpu, int apicid)
  720. {
  721. static int current_node = -1;
  722. int node = early_cpu_to_node(cpu);
  723. static int width, node_width;
  724. if (!width)
  725. width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
  726. if (!node_width)
  727. node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
  728. if (cpu == 1)
  729. printk(KERN_INFO "x86: Booting SMP configuration:\n");
  730. if (system_state < SYSTEM_RUNNING) {
  731. if (node != current_node) {
  732. if (current_node > (-1))
  733. pr_cont("\n");
  734. current_node = node;
  735. printk(KERN_INFO ".... node %*s#%d, CPUs: ",
  736. node_width - num_digits(node), " ", node);
  737. }
  738. /* Add padding for the BSP */
  739. if (cpu == 1)
  740. pr_cont("%*s", width + 1, " ");
  741. pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
  742. } else
  743. pr_info("Booting Node %d Processor %d APIC 0x%x\n",
  744. node, cpu, apicid);
  745. }
  746. static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
  747. {
  748. int cpu;
  749. cpu = smp_processor_id();
  750. if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
  751. return NMI_HANDLED;
  752. return NMI_DONE;
  753. }
  754. /*
  755. * Wake up AP by INIT, INIT, STARTUP sequence.
  756. *
  757. * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
  758. * boot-strap code which is not a desired behavior for waking up BSP. To
  759. * void the boot-strap code, wake up CPU0 by NMI instead.
  760. *
  761. * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
  762. * (i.e. physically hot removed and then hot added), NMI won't wake it up.
  763. * We'll change this code in the future to wake up hard offlined CPU0 if
  764. * real platform and request are available.
  765. */
  766. static int
  767. wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
  768. int *cpu0_nmi_registered)
  769. {
  770. int id;
  771. int boot_error;
  772. preempt_disable();
  773. /*
  774. * Wake up AP by INIT, INIT, STARTUP sequence.
  775. */
  776. if (cpu) {
  777. boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
  778. goto out;
  779. }
  780. /*
  781. * Wake up BSP by nmi.
  782. *
  783. * Register a NMI handler to help wake up CPU0.
  784. */
  785. boot_error = register_nmi_handler(NMI_LOCAL,
  786. wakeup_cpu0_nmi, 0, "wake_cpu0");
  787. if (!boot_error) {
  788. enable_start_cpu0 = 1;
  789. *cpu0_nmi_registered = 1;
  790. if (apic->dest_logical == APIC_DEST_LOGICAL)
  791. id = cpu0_logical_apicid;
  792. else
  793. id = apicid;
  794. boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
  795. }
  796. out:
  797. preempt_enable();
  798. return boot_error;
  799. }
  800. void common_cpu_up(unsigned int cpu, struct task_struct *idle)
  801. {
  802. /* Just in case we booted with a single CPU. */
  803. alternatives_enable_smp();
  804. per_cpu(current_task, cpu) = idle;
  805. #ifdef CONFIG_X86_32
  806. /* Stack for startup_32 can be just as for start_secondary onwards */
  807. irq_ctx_init(cpu);
  808. per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
  809. #else
  810. initial_gs = per_cpu_offset(cpu);
  811. #endif
  812. }
  813. /*
  814. * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
  815. * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
  816. * Returns zero if CPU booted OK, else error code from
  817. * ->wakeup_secondary_cpu.
  818. */
  819. static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
  820. int *cpu0_nmi_registered)
  821. {
  822. volatile u32 *trampoline_status =
  823. (volatile u32 *) __va(real_mode_header->trampoline_status);
  824. /* start_ip had better be page-aligned! */
  825. unsigned long start_ip = real_mode_header->trampoline_start;
  826. unsigned long boot_error = 0;
  827. unsigned long timeout;
  828. idle->thread.sp = (unsigned long)task_pt_regs(idle);
  829. early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
  830. initial_code = (unsigned long)start_secondary;
  831. initial_stack = idle->thread.sp;
  832. /* Enable the espfix hack for this CPU */
  833. init_espfix_ap(cpu);
  834. /* So we see what's up */
  835. announce_cpu(cpu, apicid);
  836. /*
  837. * This grunge runs the startup process for
  838. * the targeted processor.
  839. */
  840. if (x86_platform.legacy.warm_reset) {
  841. pr_debug("Setting warm reset code and vector.\n");
  842. smpboot_setup_warm_reset_vector(start_ip);
  843. /*
  844. * Be paranoid about clearing APIC errors.
  845. */
  846. if (APIC_INTEGRATED(boot_cpu_apic_version)) {
  847. apic_write(APIC_ESR, 0);
  848. apic_read(APIC_ESR);
  849. }
  850. }
  851. /*
  852. * AP might wait on cpu_callout_mask in cpu_init() with
  853. * cpu_initialized_mask set if previous attempt to online
  854. * it timed-out. Clear cpu_initialized_mask so that after
  855. * INIT/SIPI it could start with a clean state.
  856. */
  857. cpumask_clear_cpu(cpu, cpu_initialized_mask);
  858. smp_mb();
  859. /*
  860. * Wake up a CPU in difference cases:
  861. * - Use the method in the APIC driver if it's defined
  862. * Otherwise,
  863. * - Use an INIT boot APIC message for APs or NMI for BSP.
  864. */
  865. if (apic->wakeup_secondary_cpu)
  866. boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
  867. else
  868. boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
  869. cpu0_nmi_registered);
  870. if (!boot_error) {
  871. /*
  872. * Wait 10s total for first sign of life from AP
  873. */
  874. boot_error = -1;
  875. timeout = jiffies + 10*HZ;
  876. while (time_before(jiffies, timeout)) {
  877. if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
  878. /*
  879. * Tell AP to proceed with initialization
  880. */
  881. cpumask_set_cpu(cpu, cpu_callout_mask);
  882. boot_error = 0;
  883. break;
  884. }
  885. schedule();
  886. }
  887. }
  888. if (!boot_error) {
  889. /*
  890. * Wait till AP completes initial initialization
  891. */
  892. while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
  893. /*
  894. * Allow other tasks to run while we wait for the
  895. * AP to come online. This also gives a chance
  896. * for the MTRR work(triggered by the AP coming online)
  897. * to be completed in the stop machine context.
  898. */
  899. schedule();
  900. }
  901. }
  902. /* mark "stuck" area as not stuck */
  903. *trampoline_status = 0;
  904. if (x86_platform.legacy.warm_reset) {
  905. /*
  906. * Cleanup possible dangling ends...
  907. */
  908. smpboot_restore_warm_reset_vector();
  909. }
  910. return boot_error;
  911. }
  912. int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
  913. {
  914. int apicid = apic->cpu_present_to_apicid(cpu);
  915. int cpu0_nmi_registered = 0;
  916. unsigned long flags;
  917. int err, ret = 0;
  918. lockdep_assert_irqs_enabled();
  919. pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
  920. if (apicid == BAD_APICID ||
  921. !physid_isset(apicid, phys_cpu_present_map) ||
  922. !apic->apic_id_valid(apicid)) {
  923. pr_err("%s: bad cpu %d\n", __func__, cpu);
  924. return -EINVAL;
  925. }
  926. /*
  927. * Already booted CPU?
  928. */
  929. if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
  930. pr_debug("do_boot_cpu %d Already started\n", cpu);
  931. return -ENOSYS;
  932. }
  933. /*
  934. * Save current MTRR state in case it was changed since early boot
  935. * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
  936. */
  937. mtrr_save_state();
  938. /* x86 CPUs take themselves offline, so delayed offline is OK. */
  939. err = cpu_check_up_prepare(cpu);
  940. if (err && err != -EBUSY)
  941. return err;
  942. /* the FPU context is blank, nobody can own it */
  943. per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
  944. common_cpu_up(cpu, tidle);
  945. err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
  946. if (err) {
  947. pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
  948. ret = -EIO;
  949. goto unreg_nmi;
  950. }
  951. /*
  952. * Check TSC synchronization with the AP (keep irqs disabled
  953. * while doing so):
  954. */
  955. local_irq_save(flags);
  956. check_tsc_sync_source(cpu);
  957. local_irq_restore(flags);
  958. while (!cpu_online(cpu)) {
  959. cpu_relax();
  960. touch_nmi_watchdog();
  961. }
  962. unreg_nmi:
  963. /*
  964. * Clean up the nmi handler. Do this after the callin and callout sync
  965. * to avoid impact of possible long unregister time.
  966. */
  967. if (cpu0_nmi_registered)
  968. unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
  969. return ret;
  970. }
  971. /**
  972. * arch_disable_smp_support() - disables SMP support for x86 at runtime
  973. */
  974. void arch_disable_smp_support(void)
  975. {
  976. disable_ioapic_support();
  977. }
  978. /*
  979. * Fall back to non SMP mode after errors.
  980. *
  981. * RED-PEN audit/test this more. I bet there is more state messed up here.
  982. */
  983. static __init void disable_smp(void)
  984. {
  985. pr_info("SMP disabled\n");
  986. disable_ioapic_support();
  987. init_cpu_present(cpumask_of(0));
  988. init_cpu_possible(cpumask_of(0));
  989. if (smp_found_config)
  990. physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
  991. else
  992. physid_set_mask_of_physid(0, &phys_cpu_present_map);
  993. cpumask_set_cpu(0, topology_sibling_cpumask(0));
  994. cpumask_set_cpu(0, topology_core_cpumask(0));
  995. }
  996. /*
  997. * Various sanity checks.
  998. */
  999. static void __init smp_sanity_check(void)
  1000. {
  1001. preempt_disable();
  1002. #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
  1003. if (def_to_bigsmp && nr_cpu_ids > 8) {
  1004. unsigned int cpu;
  1005. unsigned nr;
  1006. pr_warn("More than 8 CPUs detected - skipping them\n"
  1007. "Use CONFIG_X86_BIGSMP\n");
  1008. nr = 0;
  1009. for_each_present_cpu(cpu) {
  1010. if (nr >= 8)
  1011. set_cpu_present(cpu, false);
  1012. nr++;
  1013. }
  1014. nr = 0;
  1015. for_each_possible_cpu(cpu) {
  1016. if (nr >= 8)
  1017. set_cpu_possible(cpu, false);
  1018. nr++;
  1019. }
  1020. nr_cpu_ids = 8;
  1021. }
  1022. #endif
  1023. if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
  1024. pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
  1025. hard_smp_processor_id());
  1026. physid_set(hard_smp_processor_id(), phys_cpu_present_map);
  1027. }
  1028. /*
  1029. * Should not be necessary because the MP table should list the boot
  1030. * CPU too, but we do it for the sake of robustness anyway.
  1031. */
  1032. if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
  1033. pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
  1034. boot_cpu_physical_apicid);
  1035. physid_set(hard_smp_processor_id(), phys_cpu_present_map);
  1036. }
  1037. preempt_enable();
  1038. }
  1039. static void __init smp_cpu_index_default(void)
  1040. {
  1041. int i;
  1042. struct cpuinfo_x86 *c;
  1043. for_each_possible_cpu(i) {
  1044. c = &cpu_data(i);
  1045. /* mark all to hotplug */
  1046. c->cpu_index = nr_cpu_ids;
  1047. }
  1048. }
  1049. static void __init smp_get_logical_apicid(void)
  1050. {
  1051. if (x2apic_mode)
  1052. cpu0_logical_apicid = apic_read(APIC_LDR);
  1053. else
  1054. cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
  1055. }
  1056. /*
  1057. * Prepare for SMP bootup.
  1058. * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
  1059. * for common interface support.
  1060. */
  1061. void __init native_smp_prepare_cpus(unsigned int max_cpus)
  1062. {
  1063. unsigned int i;
  1064. smp_cpu_index_default();
  1065. /*
  1066. * Setup boot CPU information
  1067. */
  1068. smp_store_boot_cpu_info(); /* Final full version of the data */
  1069. cpumask_copy(cpu_callin_mask, cpumask_of(0));
  1070. mb();
  1071. for_each_possible_cpu(i) {
  1072. zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
  1073. zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
  1074. zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
  1075. }
  1076. /*
  1077. * Set 'default' x86 topology, this matches default_topology() in that
  1078. * it has NUMA nodes as a topology level. See also
  1079. * native_smp_cpus_done().
  1080. *
  1081. * Must be done before set_cpus_sibling_map() is ran.
  1082. */
  1083. set_sched_topology(x86_topology);
  1084. set_cpu_sibling_map(0);
  1085. smp_sanity_check();
  1086. switch (apic_intr_mode) {
  1087. case APIC_PIC:
  1088. case APIC_VIRTUAL_WIRE_NO_CONFIG:
  1089. disable_smp();
  1090. return;
  1091. case APIC_SYMMETRIC_IO_NO_ROUTING:
  1092. disable_smp();
  1093. /* Setup local timer */
  1094. x86_init.timers.setup_percpu_clockev();
  1095. return;
  1096. case APIC_VIRTUAL_WIRE:
  1097. case APIC_SYMMETRIC_IO:
  1098. break;
  1099. }
  1100. /* Setup local timer */
  1101. x86_init.timers.setup_percpu_clockev();
  1102. smp_get_logical_apicid();
  1103. pr_info("CPU0: ");
  1104. print_cpu_info(&cpu_data(0));
  1105. native_pv_lock_init();
  1106. uv_system_init();
  1107. set_mtrr_aps_delayed_init();
  1108. smp_quirk_init_udelay();
  1109. speculative_store_bypass_ht_init();
  1110. }
  1111. void arch_enable_nonboot_cpus_begin(void)
  1112. {
  1113. set_mtrr_aps_delayed_init();
  1114. }
  1115. void arch_enable_nonboot_cpus_end(void)
  1116. {
  1117. mtrr_aps_init();
  1118. }
  1119. /*
  1120. * Early setup to make printk work.
  1121. */
  1122. void __init native_smp_prepare_boot_cpu(void)
  1123. {
  1124. int me = smp_processor_id();
  1125. switch_to_new_gdt(me);
  1126. /* already set me in cpu_online_mask in boot_cpu_init() */
  1127. cpumask_set_cpu(me, cpu_callout_mask);
  1128. cpu_set_state_online(me);
  1129. }
  1130. void __init calculate_max_logical_packages(void)
  1131. {
  1132. int ncpus;
  1133. /*
  1134. * Today neither Intel nor AMD support heterogenous systems so
  1135. * extrapolate the boot cpu's data to all packages.
  1136. */
  1137. ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
  1138. __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
  1139. pr_info("Max logical packages: %u\n", __max_logical_packages);
  1140. }
  1141. void __init native_smp_cpus_done(unsigned int max_cpus)
  1142. {
  1143. pr_debug("Boot done\n");
  1144. calculate_max_logical_packages();
  1145. if (x86_has_numa_in_package)
  1146. set_sched_topology(x86_numa_in_package_topology);
  1147. nmi_selftest();
  1148. impress_friends();
  1149. mtrr_aps_init();
  1150. }
  1151. static int __initdata setup_possible_cpus = -1;
  1152. static int __init _setup_possible_cpus(char *str)
  1153. {
  1154. get_option(&str, &setup_possible_cpus);
  1155. return 0;
  1156. }
  1157. early_param("possible_cpus", _setup_possible_cpus);
  1158. /*
  1159. * cpu_possible_mask should be static, it cannot change as cpu's
  1160. * are onlined, or offlined. The reason is per-cpu data-structures
  1161. * are allocated by some modules at init time, and dont expect to
  1162. * do this dynamically on cpu arrival/departure.
  1163. * cpu_present_mask on the other hand can change dynamically.
  1164. * In case when cpu_hotplug is not compiled, then we resort to current
  1165. * behaviour, which is cpu_possible == cpu_present.
  1166. * - Ashok Raj
  1167. *
  1168. * Three ways to find out the number of additional hotplug CPUs:
  1169. * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
  1170. * - The user can overwrite it with possible_cpus=NUM
  1171. * - Otherwise don't reserve additional CPUs.
  1172. * We do this because additional CPUs waste a lot of memory.
  1173. * -AK
  1174. */
  1175. __init void prefill_possible_map(void)
  1176. {
  1177. int i, possible;
  1178. /* No boot processor was found in mptable or ACPI MADT */
  1179. if (!num_processors) {
  1180. if (boot_cpu_has(X86_FEATURE_APIC)) {
  1181. int apicid = boot_cpu_physical_apicid;
  1182. int cpu = hard_smp_processor_id();
  1183. pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
  1184. /* Make sure boot cpu is enumerated */
  1185. if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
  1186. apic->apic_id_valid(apicid))
  1187. generic_processor_info(apicid, boot_cpu_apic_version);
  1188. }
  1189. if (!num_processors)
  1190. num_processors = 1;
  1191. }
  1192. i = setup_max_cpus ?: 1;
  1193. if (setup_possible_cpus == -1) {
  1194. possible = num_processors;
  1195. #ifdef CONFIG_HOTPLUG_CPU
  1196. if (setup_max_cpus)
  1197. possible += disabled_cpus;
  1198. #else
  1199. if (possible > i)
  1200. possible = i;
  1201. #endif
  1202. } else
  1203. possible = setup_possible_cpus;
  1204. total_cpus = max_t(int, possible, num_processors + disabled_cpus);
  1205. /* nr_cpu_ids could be reduced via nr_cpus= */
  1206. if (possible > nr_cpu_ids) {
  1207. pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
  1208. possible, nr_cpu_ids);
  1209. possible = nr_cpu_ids;
  1210. }
  1211. #ifdef CONFIG_HOTPLUG_CPU
  1212. if (!setup_max_cpus)
  1213. #endif
  1214. if (possible > i) {
  1215. pr_warn("%d Processors exceeds max_cpus limit of %u\n",
  1216. possible, setup_max_cpus);
  1217. possible = i;
  1218. }
  1219. nr_cpu_ids = possible;
  1220. pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
  1221. possible, max_t(int, possible - num_processors, 0));
  1222. reset_cpu_possible_mask();
  1223. for (i = 0; i < possible; i++)
  1224. set_cpu_possible(i, true);
  1225. }
  1226. #ifdef CONFIG_HOTPLUG_CPU
  1227. /* Recompute SMT state for all CPUs on offline */
  1228. static void recompute_smt_state(void)
  1229. {
  1230. int max_threads, cpu;
  1231. max_threads = 0;
  1232. for_each_online_cpu (cpu) {
  1233. int threads = cpumask_weight(topology_sibling_cpumask(cpu));
  1234. if (threads > max_threads)
  1235. max_threads = threads;
  1236. }
  1237. __max_smt_threads = max_threads;
  1238. }
  1239. static void remove_siblinginfo(int cpu)
  1240. {
  1241. int sibling;
  1242. struct cpuinfo_x86 *c = &cpu_data(cpu);
  1243. for_each_cpu(sibling, topology_core_cpumask(cpu)) {
  1244. cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
  1245. /*/
  1246. * last thread sibling in this cpu core going down
  1247. */
  1248. if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
  1249. cpu_data(sibling).booted_cores--;
  1250. }
  1251. for_each_cpu(sibling, topology_sibling_cpumask(cpu))
  1252. cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
  1253. for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
  1254. cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
  1255. cpumask_clear(cpu_llc_shared_mask(cpu));
  1256. cpumask_clear(topology_sibling_cpumask(cpu));
  1257. cpumask_clear(topology_core_cpumask(cpu));
  1258. c->cpu_core_id = 0;
  1259. c->booted_cores = 0;
  1260. cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
  1261. recompute_smt_state();
  1262. }
  1263. static void remove_cpu_from_maps(int cpu)
  1264. {
  1265. set_cpu_online(cpu, false);
  1266. cpumask_clear_cpu(cpu, cpu_callout_mask);
  1267. cpumask_clear_cpu(cpu, cpu_callin_mask);
  1268. /* was set by cpu_init() */
  1269. cpumask_clear_cpu(cpu, cpu_initialized_mask);
  1270. numa_remove_cpu(cpu);
  1271. }
  1272. void cpu_disable_common(void)
  1273. {
  1274. int cpu = smp_processor_id();
  1275. remove_siblinginfo(cpu);
  1276. /* It's now safe to remove this processor from the online map */
  1277. lock_vector_lock();
  1278. remove_cpu_from_maps(cpu);
  1279. unlock_vector_lock();
  1280. fixup_irqs();
  1281. lapic_offline();
  1282. }
  1283. int native_cpu_disable(void)
  1284. {
  1285. int ret;
  1286. ret = lapic_can_unplug_cpu();
  1287. if (ret)
  1288. return ret;
  1289. clear_local_APIC();
  1290. cpu_disable_common();
  1291. return 0;
  1292. }
  1293. int common_cpu_die(unsigned int cpu)
  1294. {
  1295. int ret = 0;
  1296. /* We don't do anything here: idle task is faking death itself. */
  1297. /* They ack this in play_dead() by setting CPU_DEAD */
  1298. if (cpu_wait_death(cpu, 5)) {
  1299. if (system_state == SYSTEM_RUNNING)
  1300. pr_info("CPU %u is now offline\n", cpu);
  1301. } else {
  1302. pr_err("CPU %u didn't die...\n", cpu);
  1303. ret = -1;
  1304. }
  1305. return ret;
  1306. }
  1307. void native_cpu_die(unsigned int cpu)
  1308. {
  1309. common_cpu_die(cpu);
  1310. }
  1311. void play_dead_common(void)
  1312. {
  1313. idle_task_exit();
  1314. /* Ack it */
  1315. (void)cpu_report_death();
  1316. /*
  1317. * With physical CPU hotplug, we should halt the cpu
  1318. */
  1319. local_irq_disable();
  1320. }
  1321. static bool wakeup_cpu0(void)
  1322. {
  1323. if (smp_processor_id() == 0 && enable_start_cpu0)
  1324. return true;
  1325. return false;
  1326. }
  1327. /*
  1328. * We need to flush the caches before going to sleep, lest we have
  1329. * dirty data in our caches when we come back up.
  1330. */
  1331. static inline void mwait_play_dead(void)
  1332. {
  1333. unsigned int eax, ebx, ecx, edx;
  1334. unsigned int highest_cstate = 0;
  1335. unsigned int highest_subcstate = 0;
  1336. void *mwait_ptr;
  1337. int i;
  1338. if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
  1339. return;
  1340. if (!this_cpu_has(X86_FEATURE_MWAIT))
  1341. return;
  1342. if (!this_cpu_has(X86_FEATURE_CLFLUSH))
  1343. return;
  1344. if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
  1345. return;
  1346. eax = CPUID_MWAIT_LEAF;
  1347. ecx = 0;
  1348. native_cpuid(&eax, &ebx, &ecx, &edx);
  1349. /*
  1350. * eax will be 0 if EDX enumeration is not valid.
  1351. * Initialized below to cstate, sub_cstate value when EDX is valid.
  1352. */
  1353. if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
  1354. eax = 0;
  1355. } else {
  1356. edx >>= MWAIT_SUBSTATE_SIZE;
  1357. for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
  1358. if (edx & MWAIT_SUBSTATE_MASK) {
  1359. highest_cstate = i;
  1360. highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
  1361. }
  1362. }
  1363. eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
  1364. (highest_subcstate - 1);
  1365. }
  1366. /*
  1367. * This should be a memory location in a cache line which is
  1368. * unlikely to be touched by other processors. The actual
  1369. * content is immaterial as it is not actually modified in any way.
  1370. */
  1371. mwait_ptr = &current_thread_info()->flags;
  1372. wbinvd();
  1373. while (1) {
  1374. /*
  1375. * The CLFLUSH is a workaround for erratum AAI65 for
  1376. * the Xeon 7400 series. It's not clear it is actually
  1377. * needed, but it should be harmless in either case.
  1378. * The WBINVD is insufficient due to the spurious-wakeup
  1379. * case where we return around the loop.
  1380. */
  1381. mb();
  1382. clflush(mwait_ptr);
  1383. mb();
  1384. __monitor(mwait_ptr, 0, 0);
  1385. mb();
  1386. __mwait(eax, 0);
  1387. /*
  1388. * If NMI wants to wake up CPU0, start CPU0.
  1389. */
  1390. if (wakeup_cpu0())
  1391. start_cpu0();
  1392. }
  1393. }
  1394. void hlt_play_dead(void)
  1395. {
  1396. if (__this_cpu_read(cpu_info.x86) >= 4)
  1397. wbinvd();
  1398. while (1) {
  1399. native_halt();
  1400. /*
  1401. * If NMI wants to wake up CPU0, start CPU0.
  1402. */
  1403. if (wakeup_cpu0())
  1404. start_cpu0();
  1405. }
  1406. }
  1407. void native_play_dead(void)
  1408. {
  1409. play_dead_common();
  1410. tboot_shutdown(TB_SHUTDOWN_WFS);
  1411. mwait_play_dead(); /* Only returns on failure */
  1412. if (cpuidle_play_dead())
  1413. hlt_play_dead();
  1414. }
  1415. #else /* ... !CONFIG_HOTPLUG_CPU */
  1416. int native_cpu_disable(void)
  1417. {
  1418. return -ENOSYS;
  1419. }
  1420. void native_cpu_die(unsigned int cpu)
  1421. {
  1422. /* We said "no" in __cpu_disable */
  1423. BUG();
  1424. }
  1425. void native_play_dead(void)
  1426. {
  1427. BUG();
  1428. }
  1429. #endif