tsc_msr.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * TSC frequency enumeration via MSR
  4. *
  5. * Copyright (C) 2013, 2018 Intel Corporation
  6. * Author: Bin Gao <bin.gao@intel.com>
  7. */
  8. #include <linux/kernel.h>
  9. #include <asm/apic.h>
  10. #include <asm/cpu_device_id.h>
  11. #include <asm/intel-family.h>
  12. #include <asm/msr.h>
  13. #include <asm/param.h>
  14. #include <asm/tsc.h>
  15. #define MAX_NUM_FREQS 9
  16. /*
  17. * If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
  18. * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
  19. * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
  20. * so we need manually differentiate SoC families. This is what the
  21. * field msr_plat does.
  22. */
  23. struct freq_desc {
  24. u8 msr_plat; /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
  25. u32 freqs[MAX_NUM_FREQS];
  26. };
  27. /*
  28. * Penwell and Clovertrail use spread spectrum clock,
  29. * so the freq number is not exactly the same as reported
  30. * by MSR based on SDM.
  31. */
  32. static const struct freq_desc freq_desc_pnw = {
  33. 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 }
  34. };
  35. static const struct freq_desc freq_desc_clv = {
  36. 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 }
  37. };
  38. static const struct freq_desc freq_desc_byt = {
  39. 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 }
  40. };
  41. static const struct freq_desc freq_desc_cht = {
  42. 1, { 83300, 100000, 133300, 116700, 80000, 93300, 90000, 88900, 87500 }
  43. };
  44. static const struct freq_desc freq_desc_tng = {
  45. 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 }
  46. };
  47. static const struct freq_desc freq_desc_ann = {
  48. 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 }
  49. };
  50. static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
  51. INTEL_CPU_FAM6(ATOM_SALTWELL_MID, freq_desc_pnw),
  52. INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET, freq_desc_clv),
  53. INTEL_CPU_FAM6(ATOM_SILVERMONT, freq_desc_byt),
  54. INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, freq_desc_tng),
  55. INTEL_CPU_FAM6(ATOM_AIRMONT, freq_desc_cht),
  56. INTEL_CPU_FAM6(ATOM_AIRMONT_MID, freq_desc_ann),
  57. {}
  58. };
  59. /*
  60. * MSR-based CPU/TSC frequency discovery for certain CPUs.
  61. *
  62. * Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy
  63. * Return processor base frequency in KHz, or 0 on failure.
  64. */
  65. unsigned long cpu_khz_from_msr(void)
  66. {
  67. u32 lo, hi, ratio, freq;
  68. const struct freq_desc *freq_desc;
  69. const struct x86_cpu_id *id;
  70. unsigned long res;
  71. id = x86_match_cpu(tsc_msr_cpu_ids);
  72. if (!id)
  73. return 0;
  74. freq_desc = (struct freq_desc *)id->driver_data;
  75. if (freq_desc->msr_plat) {
  76. rdmsr(MSR_PLATFORM_INFO, lo, hi);
  77. ratio = (lo >> 8) & 0xff;
  78. } else {
  79. rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
  80. ratio = (hi >> 8) & 0x1f;
  81. }
  82. /* Get FSB FREQ ID */
  83. rdmsr(MSR_FSB_FREQ, lo, hi);
  84. /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
  85. freq = freq_desc->freqs[lo & 0x7];
  86. /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
  87. res = freq * ratio;
  88. #ifdef CONFIG_X86_LOCAL_APIC
  89. lapic_timer_frequency = (freq * 1000) / HZ;
  90. #endif
  91. /*
  92. * TSC frequency determined by MSR is always considered "known"
  93. * because it is reported by HW.
  94. * Another fact is that on MSR capable platforms, PIT/HPET is
  95. * generally not available so calibration won't work at all.
  96. */
  97. setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
  98. /*
  99. * Unfortunately there is no way for hardware to tell whether the
  100. * TSC is reliable. We were told by silicon design team that TSC
  101. * on Atom SoCs are always "reliable". TSC is also the only
  102. * reliable clocksource on these SoCs (HPET is either not present
  103. * or not functional) so mark TSC reliable which removes the
  104. * requirement for a watchdog clocksource.
  105. */
  106. setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
  107. return res;
  108. }